BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a pattern of scanning lines and common lines formed by a scanning line and common line forming process.
FIG. 2 is a diagram showing a pattern of common electrodes formed by a common electrode forming process.
FIG. 3 is a diagram showing a pattern of semiconductor layers formed by a semiconductor layer forming process.
FIG. 4 is a diagram showing a pattern of signal lines and drain electrodes formed by a signal line and drain electrode forming process.
FIG. 5 is a diagram showing a pattern of contact holes formed by a contact hole forming process.
FIG. 6 is a plan view showing all the patterns of FIGS. 1 to 5 overlapping with each other without taking their vertical positional relationship into consideration.
FIG. 7 is a diagram showing pixel electrodes formed by a pixel electrode forming process.
FIG. 8 is a plan view showing the patterns of FIGS. 6 and 7 overlapping with each other without taking their vertical positional relationship into consideration.
FIG. 9 is a diagram showing a pattern of a black matrix provided on a color filter substrate.
FIG. 10 is a diagram showing the pattern of FIG. 9 overlapped on the pattern of FIG. 7.
FIG. 11 is a schematic plan view of one pixel of an IPS mode LCD panel.
FIG. 12 is a schematic sectional view taken along the line XII-XII of FIG. 11.
FIG. 13 is a schematic plan view of one pixel of an FFS mode LCD panel.
FIG. 14 is a schematic sectional view taken along the line XIV-XIV of FIG. 13.
FIG. 15 is a plan view of one pixel of an FFS mode LCD panel with inclined slits.
FIG. 16 is a plan view of one pixel of an FFS mode LCD panel in a dual-domain structure.
FIG. 17 is a schematic plan view of several pixels of an FFS mode LCD panel 70D in which pixels are provided in a delta arrangement.