Patent Application
20250216626
Demands for artificial intelligence (AI) computing, such as machine learning (ML) and deep learning (DL), are increasing faster than they can be met by increases in available processing capacity. This rising demand and the growing complexity of AI models drive the need to connect many chips into a system where the chips can send data between each other with low latency and at high speed. Performance when processing a workload is limited by memory and interconnect bandwidth. In many conventional systems, data movement leads to significant power consumption, poor performance, and excessive latency.
Implementations of this specification provide apparatus, systems, and techniques for photonic interconnects. The photonic interconnects can be used to route data between nodes on a same chip (intra-chip routing) and between nodes on different chips (inter-chip routing). Both inter-chip and intra-chip routing can include routing data over electrical channels, over photonic channels, or over both electrical channels and photonic channels, between nodes, chips, packages, systems, and any suitable platforms.
The photonic interconnect techniques enable disaggregation of compute and memory, which allows each component to be leveraged and scaled effectively to deliver more than one order of magnitude higher bandwidth and memory capacity while reducing latency and power consumption by up to one order of magnitude compared to existing optical interconnect alternatives and copper. For example, the techniques can deliver data directly to the point of compute using the photonic interconnects, while supporting high memory bandwidth and latency requirements at low single digit pJ/bit power, which enables terabyte class bandwidth between compute nodes at low latency and power. The techniques can address key concerns across performance and energy efficiency to ensure systems, models and algorithms, e.g., hyperscalers, data centers, artificial intelligence (AI) models, to continue to innovate and scale.
The photonic interconnects feature fiber array unit (FAU) assemblies that facilitate use of non-polarization maintain fibers for carrying optical signals between nodes and light sources. In certain implementations, the FAU assemblies feature detachable sub-assemblies facilitating manual detachment and reattachment of FAUs to photonic integrated circuits.
Other features and advantages will be apparent from the following description, the drawings, and the claims.
Like reference numbers and designations in the various drawings indicate like elements.
This specification describes computing systems including compute and memory, implemented by one or more circuit packages with photonic interconnects, which achieve reduced power consumption and/or increased processing speed as a result of the data-movement-related technologies described in this specification. In particular, power consumed for data movement is reduced by increasing data locality in each circuit package and reducing energy losses when data movement is needed compared to conventional computer systems. Power-efficient data movement, in turn, can be accomplished by moving data over small distances in the electronic domain, while leveraging photonic channels for data movement in scenarios where the resistance in the electronic domain and/or the speed at which the data can move in the electronic domain leads to bandwidth limitations. Thus, in some examples, each circuit package includes an electronic integrated circuit (EIC) that includes multiple compute nodes that are connected by bidirectional photonic channels, e.g., implemented in a PIC in a separate layer or chip of the package, into a hybrid, electronic-photonic (also referred to as an electro-photonic) network-on-chip (NoC). Multiple such NoCs may be connected, by inter-chip bidirectional photonic channels, e.g., channels implemented over optical fibers, between respective circuit packages, into a larger electro-photonic network, to scale the computing system to arbitrary size without incurring significant power or speed losses.
While the described computing systems and their various novel aspects are generally applicable to a wide range of processing tasks, they are particularly suited to implementing machine learning (ML) models, in particular, artificial neural networks (ANNs). As applied to ANNs, a circuit package and system of interconnected circuit packages as described in this specification are also referred to as an “ML processor” and “ML accelerator,” respectively.
Neural networks are machine learning models that include one or more layers of artificial neurons that compute neuron output activations from weighted sums of a set of input activations. These computations correspond to Multiply-Accumulate (MAC) operations. For a given neural network, the flow of activations between nodes and layers is fixed. Further, once training of the neural network is complete, the neuron weights in the weighted summation, and any other parameters associated with computing the activations, are likewise fixed. Thus, a NoC lends itself to implementing a neural network by assigning neural nodes to compute nodes, pre-loading the fixed weights associated with the neural nodes into memory of the respective compute nodes and configuring data routing between the compute nodes based on the predetermined flow of data between the neural nodes. The weighted summation can be efficiently performed using a dot product engine, also called a “digital neural network (DNN)” due to its applicability to ANNs.
Reference will now be made in detail to implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the implementations.
Several features are described hereafter that can each be used independently of one another or with any combination of other features. However, any individual feature may not address any of the problems discussed above or might only address one of the problems discussed above. Some of the problems discussed above might not be fully addressed by any of the features described herein. Although headings are provided, information related to a particular heading, but not found in the section having that heading, may also be found elsewhere in this description.
In some implementations, the system 100 includes a server, a computing center, or a data center. The first system 110 can be a computing system including one or more computing elements, e.g., microprocessors (MPU), central processing units (CPUs), graphics processing units (GPUs), artificial intelligence (AI) accelerators, and/or digital application-specific integrated circuits (ASICs). The second system 120 can be a data storage system including one or more memory elements, e.g., NAND Flash memory, solid-state drive (SSD) memory, NOR Flash memory, complementary metal-oxide-semiconductor (CMOS) memory, thin film transistor-based memory, phase change memory (PCM), storage class memory (SCM), read-only memory (ROM), random-access memory (RAM), magneto-resistive RAM (MRAM), resistive
RAM, static random access memory (SRAM), dynamic RAM (DRAM), synchronous dynamic random-access memory (SDRAM), Double Data Rate (DDR)-based DRAM, high bandwidth memory (HBM), and/or dual in-line memory module (DIMM) memory such as DDR-DIMM.
In some implementations, e.g., as illustrated with further details in
To ensure high data transmission with low latency between the first system 110 (e.g., the computing system) and the second system 120 (e.g., the storage system), photonic interconnect is implemented in the system 100. The first system 110 includes a first circuit package 140 that includes a first photonic interface 112, and the second system 120 includes a second circuit package 160 that includes a second photonic interface 122. The first circuit package 140 and the second circuit package 160 are configured to communicate with each other through one or more photonic channels between the first photonic interface 140 and the second photonic interface 160 that can be coupled to each other through optical fibers 130. The optical fibers 104 and 130 are attached to the first photonic interface 112 by a fiber array unit (FAU) assembly 111 and optical fibers 108 and 130 are attached to the second photonic interface 122 by a FAU assembly 121. The fiber array unit assemblies 111 and 121 position a respective fiber array unit with respect to photonic ports in the surface of a photonic integrated circuit (PIC) of the circuit packages to align optical fibers to transmit light between optical fibers and waveguides in the PICs.
As discussed with further details below (e.g.,
In some implementations, the EIC includes multiple compute nodes. The compute nodes can communicate with each other over one or more intra-chip bidirectional channels. The intra-chip bidirectional channels can include one or more bidirectional photonic channels, e.g., implemented with optical waveguides in the PIC, and/or one or more electronic channels, e.g., implemented in the circuitry of the EIC. The compute nodes may but need not in all examples be electronic circuits identical or at least substantially similar in design, and as shown, may form “tiles” of the same size arranged in a grid or any other arrangement suitable for performing the computations described herein. Each compute node in the EIC can include one or more circuit blocks serving as processing engines, e.g., a dot product engine, DNN, or a tensor engine. In examples, the compute node can have any combination of processing elements such as CPUs, GPUs, TPUs, and the like, and the DNN and tensor engine can also be included or omitted depending on the application. Each compute node can include a message router. The message routers interface with channels, e.g., electronic and/or photonic channels to facilitate data flow to and from the compute nodes. Further, the compute node can have a memory system, e.g., including level-one static random-access memory (L1SRAM) and level-two static random access memory (L2SRAM). In some implementations, a compute node includes a compute block which may include various processing, storage, and/or communication functions, and an Analog Mixed Signal (AMS) block that can include analog/mixed signal circuits for interfacing with the PIC, e.g., as illustrated with further details in
A photonic integrated circuit (PIC) can include optical modulators and photodiodes, and an electronic integrated circuit (EIC) (e.g., an AMS block) can include modulator drivers and transimpedance amplifiers (TIAs). An optical modulator and a modulator driver can form an optical transmitter (TX), and a photodiode and a TIA can form an optical receiver (RX). In such a way, the circuit package can have at least one photonic transceiver (TX and RX) whose functionality resides partially in the PIC and/or partially in the EIC, which enables the photonic transceivers to send and receive data packets in the optical domain as modulated electromagnetic waves via photonic channels and/or as digital packets via electrical interconnections.
A photonic interface (e.g., 112, 122) can include one or more transmitters and/or one or more receivers. The one or more transmitters can be referred to as an electrical-to-optical (EO) interface, and the one or more receivers can be referred to as an optical-to-electrical (OE) interface. That is, a photonic interface (e.g., 112, 122) can include at least one of an EO interface or an OE interface. A transmitter in one photonic interface can connect with a receiver in another photonic interface to form a one-to-one unidirectional optical path (or an optical lane) (e.g., as illustrated with further details in
To provide a large number of optical paths for high bandwidth data communication between photonic interfaces (e.g., 112, 122), circuit packages (e.g., 140, 160), and/or systems (e.g., 110, 120), wavelength-division multiplexing (WDM) or Dense wavelength-division multiplexing (DWDM) technology can be utilized, such that light with multiple wavelengths can be utilized. In some examples, a photonic channel includes multiple bidirectional optical paths, and a number of the multiple bidirectional optical paths is identical to a number of the multiple wavelengths. A number of unidirectional optical paths can be twice of the number of multiple wavelengths.
As illustrated in
In some implementations, a light source can be implemented into the PIC or implemented separately from the PIC either within or externally to the circuit package and coupled to the PIC by suitable optical couplers. For example, as illustrated in
An optical modulator can be an electro-absorption modulator (EAM), which is a semiconductor device that modulates the intensity of an optical signal by varying absorption of the optical signal as it traverses the modulator based on an electric voltage applied to the EAM. An operation of an EAM can be based on the Franz-Keldysh effect, e.g., a change in the absorption spectrum caused by an applied electric field, which changes the bandgap energy, and thus the photon energy of an absorption edge, but usually does not involve the excitation of carriers by the electric field. EAMs can be made in the form of a waveguide with electrodes for applying an electric field in a direction perpendicular to the modulated optical signal. In some examples, the EAM is implemented in a layer of germanium silicon, e.g., an epitaxially-grown layer of GeSi. Germanium can stoichiometrically constitute 90% or more of the GeSi material, e.g., 95% or more, 96% or more, 97% or more, 98% or more, or 99% or more.
One or more photonic channels (unidirectional optical paths and/or bidirectional optical paths) can be formed between the circuit packages 140, 160, or the photonic interfaces 112, 122. For example, light from a first light source 102 can be coupled through optical fibers 104 and grating couplers 151a into a first PIC 150 of the first circuit package 140 and be further guided to optical modulators 153 such as EAMs through an optical guiding system 152a (e.g., as illustrated with further details in
In some implementations, one or more intra-chip unidirectional optical paths (or lanes) can be also formed from optical modulators to corresponding PDs in a same PIC, and accordingly, one or more intra-package unidirectional data paths can be also formed in a same circuit package, e.g., as illustrated in
In some implementations, as shown in
Similarly, light from a second light source 106 can be coupled through optical fibers 108 and grating couplers 171a into the second PIC 170 of the second circuit package 160 and be further guided to optical modulators 173 such as EAMs through an optical guiding system 172a. The optical modulators 173 modulates the light with data by corresponding modulator drivers in the second EIC of the second circuit package 160 to generate modulated light. When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single wavelengths from the optical modulators 173 can be guided (optionally through an optical guiding system 172b to a multiplexer 174. The multiplexer 174 can multiplex the multiple light beams into a multiplexed light beam. The multiplexed light beam can be coupled out of the second PIC 170 through grating couplers 171b into the optical fibers 130 and then to the first circuit package 140. The multiplexed light beam can be coupled into the first PIC 150 in the first circuit package 140 through grating couplers 151c into a demultiplexer 155. The demultiplexer 155 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the corresponding single wavelength can be guided (optionally through an optical guiding system 152c) to photodiodes 156. The photodiodes 156 can convert detected light into electrical data that can be transmitted to corresponding TIAs in the EIC of the first circuit package 140. In such a way, one or more unidirectional optical paths (or lanes) are formed from the optical modulators 173 in the second PIC 170 to the corresponding PDs 156 in the first PIC 150. Accordingly, one or more unidirectional data paths are formed from the modulator drivers in the second EIC to the TIAs in the first EIC.
In some implementations, as shown in
In some implementations, the grating couplers 151a, 151b, 151c in the first PIC 150 can be arranged in an array, that can be coupled (in and out) with the optical fibers 130, 104 together using a first fiber array unit (FAU) assembly (e.g., as illustrated with further details in
In some implementations, the optical guiding systems 152a, 152b, and 152c in the first PIC 150 can be configured such that light can be guided in or out from corresponding components in the first PIC 150 in an ordered, efficient way and in a miniaturized area. For example, optical modulators 153 and PDs 156 for each photonic channel are positioned in a same corresponding channel area, and light beams with corresponding single wavelengths can be guided as two groups respectively to the optical modulators 153 and the PDs 156 in the corresponding channel area. Channel areas for different photonic channels are arranged adjacent to each other. The multiplexers 154 and the demultiplexers 156 are arranged further from the channel areas and closer to the grating couplers 151a, 151b, 151c, and can be arranged parallel to one another. A multiplexer 154 and a demultiplexer 156 for a same photonic channel can be arranged adjacent to each other. In such a way, light from the optical modulators 153 to the multiplexer 154 and light from the demultiplexer 156 to the PDs 156 can be guided in corresponding waveguides adjacent to each other between a corresponding channel area and an area close to the grating couplers. Similarly, the optical guiding systems 172a, 172b, and 172c in the second PIC 170 can be configured such that light can be guided in or out from corresponding components in the second PIC 170 in an ordered, efficient way and in a miniaturized area.
In a first optical path 201a, first light with the single wavelength λ0 from a first light source such as a laser diode 202a is coupled through an optical fiber 203a (e.g., the optical fiber 104 or 108 of
In a second optical path 201b, second light with the single wavelength λ0 from a second light source such as a laser diode 202b is coupled through an optical fiber 203b (e.g., the optical fiber 104 or 108 of
As discussed above and below, the first optical modulator 204a and the second photodetector 204b can be integrated in a first PIC 204 (e.g., the PIC 150 or 170 of
A first circuit 214 in a first PIC (e.g., the PIC 150 or 170 of
Each optical modulator 214a in the first circuit 214 is configured to receive a light beam with a corresponding single wavelength (e.g., λ0, λ1, λ2, or λ3) from a corresponding laser diode 212a through a corresponding optical fiber 213a. The optical multiplexer 217a in the first circuit 214 multiplexes the multiple light beams from the multiple optical modulators 214a to obtain a multiplexed light beam that can be transmitted through an optical fiber 215a to the corresponding demultiplexer 218a in the second PIC 216. The demultiplexer 218a demultiplexes the multiplexed light beam into multiple light portions each with a corresponding single wavelength to corresponding photodetectors 216b (e.g., λ0, λ1, λ2, or λ3). Thus, a first group 210a of unidirectional optical paths with the multiple wavelengths is formed between the first circuit 214 and the second circuit 216.
Similarly, in the second PIC 216, each optical modulator 216a in the second circuit 216 is configured to receive a light beam with a corresponding single wavelength (e.g., λ0, λ1, λ2, or λ3) from a corresponding laser diode 212b through a corresponding optical fiber 213b. The optical multiplexer 217b in the second circuit 216 multiplexes the multiple light beams from the multiple optical modulators 216a to obtain a multiplexed light beam that can be transmitted through an optical fiber 215b to the corresponding demultiplexer 218b in the first circuit 214. The demultiplexer 218b demultiplexes the multiplexed light beam into multiple light portions each with a corresponding single wavelength to corresponding photodetectors 214b (e.g., λ0, λ1, λ2, or λ3). Thus, a second group 210b of unidirectional optical paths with the multiple wavelengths is formed between the first circuit 214 and the second circuit 216.
In some examples, the number of wavelengths is 4. For a photonic channel 210, there can include 4 optical modulators, 4 photodetectors, one optical multiplexer, and one optical demultiplexer in each of the first circuit 214 and the second circuit 216.
The depicted structure of the circuit package 300 is merely one of several possible ways to assemble and package the various components. In some examples, some or all of the EIC 310 is disposed on the substrate. In some examples, some or all of the PIC 320 is placed on top of the EIC 310. In some examples, it is also possible to create the EIC 310 and PIC 320 in different layers of a single semiconductor chip. In some examples, the photonic circuit layer includes or is made of multiple PICs 320 in multiple sub-layers. Multiple layers of PICs 320, or a multi-layer PIC 320, may help to reduce waveguide crossings. Moreover, the structure may be modified to included multiple EICs 301 connected to a single PIC 320. For example, the multiple EICs 301 may be connected to each other by photonic channels in the PIC 320.
In some implementations, the EICs and PICs can be manufactured using standard wafer fabrication processes. Further, in some examples, heterogeneous material platforms and integration processes are used. For example, various active photonic components, e.g., the laser light sources and/or optical modulators and photodetectors used in the photonic channels, may be implemented using group III-V semiconductor components.
The laser light source(s) can be implemented either in the circuit package 300 or externally. When implemented externally, a connection to the circuit package 300 may be made optically using a grating coupler in the PIC 320 underneath an FAU assembly 302 as shown and/or using an edge coupler. In some cases, lasers are implemented in the circuit package 300 by using an interposer containing several lasers that can be co-packaged and edge-coupled with the PIC 320. In some cases, the lasers are integrated directly into the PIC 320 using heterogenous or homogenous integration. Homogenous integration allows lasers to be directly implemented in the silicon substrate in which the waveguides of the PIC 320 are formed, and allows for lasers of different materials, such as indium phosphide (InP), and architectures such as quantum dot lasers. Heterogenous assembly of lasers on the PIC 320 allows for group III-V semiconductors or other materials to be precision-attached onto the PIC 320 and optically coupled to a waveguide implemented on the PIC 320.
Light from fibers or to fibers can be coupled into and out of a PIC using a number of different ways. In some examples, as illustrated in
In some implementations, multiple circuit packages 300 may be interconnected to result in a single system providing a large electro-photonic network, e.g., by connecting several chip-level electro-photonic networks. Multiple circuit packages configured as ML processors may be interconnected to form a larger ML accelerator. For example, the photonic channels within the several circuit packages or ML processors, the optical connections, the laser light sources, the passive optical components, and the external optical fibers on the PCB, may be utilized in various combinations and configurations along with other photonic elements to form the photonic fabric of a multi-package system or multi-ML-processor accelerator.
In various embodiments, in a design like the circuit package 300, an EIC is directly coupled to a PIC, such as shown in
In various embodiments, the EAM is an optical modulation element that enables light to pass between a cathode and an anode. Additionally, the EAM provides thermal stability at over 30 degrees Centigrade and enables the PIC 320 to be packaged directly with one or more processors of the EIC 310 and/or memory chips. The EAM can provide optical connectivity both within a chip and chip-to-chip. In some examples, the EAM can be about 50 microns in size and/or operate at data rates between 50-115 Gbps, at less than 1.0 volt of power (but up to 2.0 volts).
The circuit package 330 includes two compute nodes 334-1 and 334-2, collectively, compute nodes 334, which each include a respective compute block 358-1 and 358-2 which may include various processing, storage, and/or communication functions. The compute nodes 334 each include an Analog Mixed Signal (AMS) block 360-1 and 360-2, collectively AMS blocks 360, that includes analog/mixed signal circuits for interfacing with the PIC 320. The compute blocks 358 each include an interface 357-1 and 357-2, collectively interfaces 357, for communicating with the AMS blocks 360, or more specifically, with the componentry of the AMS blocks 360.The AMS blocks 360 each include a modulator driver 362-1 and 362-2, collectively drivers 362, and each include a transimpedance amplifier (TIA) 364-1 and 364-2, collectively TIAs 364. The PIC 320 includes a pair of modulators 356-1 and 356-2 and a pair of photodetectors 366-1 and 366-2. The PIC 320 also includes a grating coupler 354 or other optical interface (OI) configured to receive and pass on light to one or more components and an optical splitter 326.
A light engine 350 can provide light as an optical carrier signal for communication between the first compute node 334-1 and second compute node 334-2. The light engine 350 provides the carrier signal to a FAU 332 of the circuit package 330, such as through an optical fiber. The FAU 332 is optically coupled to the grating coupler 354 which directs the optical carrier signal on to other components of the circuit package 330. The splitter 326 receives the optical carrier signal from the grating coupler 354 and splits the optical signal along two optical paths 370 and 372. More generally, the splitter 326 may distribute the optical carrier signal over any number of photonic paths. The optical paths 370 and 372 may be implemented as any suitable optical transmission medium and may include a mixture of waveguides and optical fibers, or any other suitable transmission medium. In the present example, the optical paths 370 and 372 can be implemented as waveguides in the PIC 320.
The optical paths 370 and 372 pass from the splitter 326 to the optical modulators 356-1 and 356-2, respectively. Each optical modulator modulates the optical carrier signal it receives from the splitter 326 based on information from its respective optical driver 362-1 and 362-2 and transmits the modulated signal along the respective optical path. A first photodetector 366-1 receives the modulated signal from the optical path, e.g., from the associated modulator 356-2. As depicted, the optical path from modulator 356-1 connects to photodetector 366-2 and the optical path from modulator 356-2 connects to photodetector 266-1. The photodetectors 366-1, 366-2 convert the received modulated signal into respective electrical signal and pass the electrical signals to a transimpedance amplifier 364-1, 364-2 through which the compute nodes 334-1 and 334-2 receive the information encoded in the signals. In this way, communication occurs between the compute nodes through the various components just described. Accordingly, the PIC 320 described here includes an intra-chip bidirectional photonic channel, including two unidirectional photonic links for communicating both to and from each compute node. Here, the first unidirectional photonic link is defined by the modulator driver 362-1, the optical modulator 356-1, the optical path 370, the photodiode 366-2, and the transimpedance amplifier 364-2. Similarly, the second unidirectional link is defined by the modulator driver 362-2, the optical modulator 356-2, the optical path 370, the photodiode 366-1, and the transimpedance amplifier 364-1. The first and second unidirectional links operate in opposite directions. Additionally, one or more of the compute nodes 334 may include one or more serializers and/or deserializers for communicating signals between the compute nodes 334. In this way, the two unidirectional photonic links form the intra-chip bidirectional photonic channel.
Referring to
One type of optical fiber useful for such applications is polarization-maintaining optical fiber (PMF), which preserves the polarization state of light as it propagates through the fiber. It can be useful in applications where maintaining a specific polarization orientation of light is advantageous, for example, when it is coupled with a polarizing grating coupler where the efficiency of light coupling may vary based on the orientation of the incoming optical signal's polarization. A polarized optical signal can be s-polarized, i.e., with electric field vector perpendicular (transverse) to the plane of incidence, or p-polarized, i.e., with electric field vector parallel to the plane of incidence.
Another type of optical fibers is non-polarization-maintaining optical fiber. Unlike PMFs, non-polarization-maintaining optical fibers does not maintain polarization as light propagates through the fiber. For example, a non-polarization-maintaining optical fiber can change the polarization state (predictably or randomly) and/or allow polarized light to depolarize as it propagates.
Typically, photonic integrated circuits (PICs) transmit data using polarized light. Accordingly, PMFs are sometimes used to maintain the polarization state of the light as it propagates between PICs. However, polarization maintaining fibers are generally more expensive than conventional, non-polarization maintaining fiber.
In some implementations, the systems described in this specification can take advantage of conventional, non-polarization maintaining fiber for delivery of light to and from a PIC. Such systems can include an FAU assembly for surface coupling an unpolarized or arbitrarily polarized optical signal into a PIC. The assembly splits the optical signal from an optical fiber into two optical signals having orthogonal polarization states and couples the two optical signals into a pair of photonic ports in the PIC.
During operation, light 403 from the fiber diverges as it emerges from the FAU 404 and is collimated by the lens 406 before being incident on the beam splitter 408. The beam splitter 408 splits the incident light 403 into two beams, a first polarized optical signal 403a, and a second polarized optical signal 403b, which is orthogonally polarized to the first signal 403a. In some implementations, the first polarized optical signal 403a is s-polarized, and the second polarized optical signal 403b is p-polarized. In some implementations, the reflector 410 is arranged to fold the path of either or both the first polarized optical signal 103a or the second polarized optical signal 103b to direct it towards the surface of the PIC 401 (examples are described below)
The second polarized optical signal 403b is incident on the polarization rotator 412 which rotates the polarization state by 90°. As a result, the second polarized optical signal 403b emerging from the polarization rotator 412 has the same polarization state as the first signal 403a, e.g., both can be s-polarized when the rotator 412 transforms p-pol into s-pol. The lens 414 and the lens 416 respectively focus like-polarized light beams onto respective photonic ports, e.g., a grating coupler, at the surface of the PIC 401, through which each of the two light beams is coupled into a respective one of a pair of waveguides in the PIC 401.
In general, the FAU 404 has multiple channels, including one or more transmitter channels, one or more receiver channels, one or more power channels, and one or more alignment channels. For example, in certain cases, the FAU 404 has 42 total channels, including 16 channels for transmitters, 16 channels for receivers, 8 channels for power, i.e., channels that provide laser light for modulation into data signals, and 2 dummy channels, e.g., for alignment purpose.
In some implementations the assembly 400 has a horizontal configuration. In a horizontal configuration, the FAU 404 emits light parallel to the surface of the PIC 401 and reflectors in the optical assembly are used to fold the light path towards the photonic ports. Horizontal configurations can be more robust against external forces acting in the lateral direction, e.g., the first direction, compared to configurations where the fibers are arranged perpendicular to the PIC surface. In addition, a horizontal configuration may allow for a more compact system configuration along the vertical direction.
Referring to
The assembly 500 delivers two polarized optical signals 503a and 503b′ to the PIC 401 from a conventional optical fiber. The assembly 500 includes, in order along the light path, a FAU 514, a lens 516, a transparent (e.g., glass) spacer 512, a polarizing beam splitter (PBS) 522 with a polarizing interface 522a, a reflector 520 (e.g., a prism, e.g., with a reflective surface), a transparent spacer 524, a polarization rotator 532, and a lens array 518 that includes lenses 534 and 536.
The lens 516 collimates the light 103 emitted from a fiber in FAU 514 before the beam 103 is incident on the PBS 522. The spacer 512 provides an offset separating the lens 516 from the PBS 522.
The PBS 212 transmits p-polarized light through the interface 522a, while reflecting the orthogonal s-polarized light. The reflected beam, 103a propagates along a first path through the spacer 524 before being focused by the lens 534 onto a first photonic port on the surface 401a of the PIC 401. The second beam transmitted by the PBS 522 reflects from reflector 520 and passes through the polarization rotator 532. This rotator rotates the polarization state of the beam by 90°. As a result, the beam 503b′ emerging from the polarization rotator 112 has the same polarization state as beam 503a (s-pol). The lens 536 focuses the beam 503b′ onto a second photonic port adjacent the first port on the surface 401a. The photonic ports at the PIC surface 401a are separated by a distance corresponding to the difference in path lengths between the first and second beams. This distance can be relatively small, e.g., 1 mm or less, 0.8 mm or less, 0.5 mm or less, 0.4 mm or less, 0.25 mm or less, 0.2 mm or less, for example, about 0.1 mm.
In some implementations, the signals 503a and 503b′ can be delivered to a photodetector, e.g., a photodiode, in the PIC 401. For example, referring to
The grating couplers 544, 545 can have a periodic structure of grooves or ridges etched on into a layer or layers of the PIC 401 that also includes the waveguides. These periodic structures act as a diffraction grating and can efficiently couple light entering the PIC from the photonic port into the waveguides.
The waveguide 546 and 547 can have different optical path lengths, e.g., to compensate for the optical path length difference between the two beams due to the different paths in the assembly 500. The optical path length difference between the waveguides can be 1 mm or less, e.g., 0.8 mm or less, 0.5 mm or less, 0.4 mm or less, 0.25 mm or less, 0.2 mm or less, e.g., about 0.1 mm. In some implementations, the assembly 500 and waveguides 546, 547 are configured so that the two optical signals have the same frequency and net group delay when they reach the photodetector 542. The intensity of each signal can be the same or different.
In some examples, an optical assembly delivers light from a fiber in an FAU to a modulator in the PIC, which encodes data into the optical signal. Referring to
The modulator 552 can be an electro-absorption modulator (EAM), which is a semiconductor device that modulates the intensity of an optical signal by varying absorption of the optical signal as it traverses the modulator 552 based on an applied electric voltage to the EAM. Generally, the principle of operation of an EAM is based on the Franz-Keldysh effect, i.e., a change in the absorption spectrum caused by an applied electric field, which changes the bandgap energy, and thus the photon energy of an absorption edge, but usually does not involve the excitation of carriers by the electric field. EAMs can be made in the form of a waveguide with electrodes for applying an electric field in a direction perpendicular to the modulated optical signal. In certain examples, the EAM is implemented in a layer of germanium silicon, e.g., an epitaxially-grown layer of GeSi.
While in the foregoing examples the assembly 500 is used to deliver light to the PIC 401, the assembly can also (or alternatively) be used to couple light out of the PIC and into a fiber. For example,
In some implementations, the outcoupled signal can be delivered to the polarization rotator 532 and reflector 520, having its polarization state rotated before being coupled into the fiber.
In the prior examples, PBS 522 is composed of a pair of prisms that are bonded at the interface 522a with a coating at the interface to facilitate the polarized beam splitting. More generally, other beam splitters can be used. For example,
Referring to
Generally, assembly 700 can be configured to couple any reasonable number, N, of fibers to a PIC. In some examples, the assembly can couple an array of 20 to 100 fibers (e.g., 40 fibers or more, 60 fibers or less). Generally, the lens array 708 includes a 1×N array of lenses and the array 718 includes a 2×N array of lenses, each aligned with a corresponding photonic port on the surface 401a.
In assembly 700, the PBS is butt coupled to the reflector, the reflector is butt coupled to the polarization rotator, and the polarization rotator is butt coupled to the lens array 718. Butt coupling can provide some advantages, including increasing coupling efficiency by aligning optical elements in direct contact and enhancing the transfer of optical power between them. It may also reduce the reflections at the interface and thus reduce signal loss. In addition, it allows for a compact design.
While the assembly 700 includes a number of optical components butt coupled together, examples can also include free space in the optical path. For example, referring to
Configurations with free space between lenses and adjacent optical components can provide some advantages, such as greater alignment tolerance, reduced contamination risk, and greater flexibility for component interchangeability.
Other configurations are possible. For example,
In some examples, the glass substrate 1302 does not need to be co-extensive with the upper glass substrate 1304. For example, referring to
The smaller surface may allow for a more compact system configuration and an increased packaging density. It may also allow for a space-efficient design for the PIC 401 such that a more substantial portion of the PIC 401 can be dedicated to active devices.
A further example assembly is assembly 1500 shown in
The optical assemblies described in
Light emitted from the fibers of the FAU 714 propagate towards the surface 401a of the PIC. After being collimated by lenses of the lens array 716, the s-polarized light is transmitted through the PBS while the p-polarized light is reflected and traverses plate 710 before being reflected by the reflector surface back towards the PIC. The path of the s-polarized light is shown as arrow 1703a and the path of the p-polarized light is shown by an arrow 1703b. The PBS and reflector spatially separate the two components which are focused by lens array 1718 onto respective photonic ports on the surface of the PIC.
A vertical configuration, such as the assembly 1700's configuration, can be more robust against external forces acting in the vertical direction, compared to horizontal configurations. In addition, the vertical configuration can have a smaller coupling interface with the PIC 401, which allows for a more compact system configuration and an increased packaging density.
Further, as noted above, the butt coupling of components in the assembly 1700 can provide some advantages, including increasing coupling efficiency by aligning optical elements in direct contact and enhance the transfer of optical power between them. It may also reduce the reflections at the interface and thus reduce signal loss. In addition, it allows for a compact design.
Vertically configured assemblies can also include components that are spaced apart, rather than butt coupled into an integrated package. For example, referring to
While the assemblies 1700 and 1900 are vertically configured so that light from the fibers are incident on the surface of the PIC nominally perpendicular (the focused light will subtend a cone with an axis approximately perpendicular to the surface), in some examples an optical assembly can be configured to deliver light at non-perpendicular incidence. For example, assemblies can include a slanted surface to mount the assembly off-perpendicular, e.g., so that the incident beams have a nominal incidence angle in a range that is greater than 0° but less than 45°, such as in a range from 5° to 20°, from 5° to 15°, from 5° to 10°, such as about 7°.
Referring to
Next, as illustrated in
As illustrated in
As illustrated in
As illustrated in
Attaching the assembly 2300 to the PIC 401 involves coupling a first surface 2304b of the glass wedge 2304 to a top surface 401a of the PIC 401. The alignment tolerance between the assembly 2300 to the PIC 401 can be within ±10 microns. An index matching gel or adhesive is used between the glass wedge 2304 and the PIC 401.
As illustrated in
The assemblies described above can include one or more kinematic alignment features (e.g., kinematically adjustable actuators) to facilitate the alignment of each optical channel to its corresponding photonic port. For example, an assembly can include actuators for kinematic adjustment of the assembly along at least one axis (e.g., two axes, three axes, four axes, five axes, or six axes). In some cases, kinematic adjustment along at least one linear axis and at least one rotation axis is possible. The actuators can be manually adjusted actuators, e.g., for adjustment by a hex-key or screw adjustment. Alternatively, or additionally, in some implementations at least one of the actuators can be an active actuator, e.g., that provides electro-mechanical adjustment along at least one axis.
The optical assemblies described previously can, in certain implementations be arranged as a pair of subassemblies that can be attached and detached from each other in a way that facilitates quick assembly or replacement of one part of the assembly with another. One of the subassemblies can be securely affixed to the PIC while the other can be quickly connected or disconnected. The subassemblies can include registration features that guide the alignment of the optical components so that the complete optical assembly is properly aligned for use upon attachment of one subassembly with another. One or both of the subassemblies can include one or more actuators for kinematic adjustment.
Referring to
The detachable sub-assembly 1610 includes a FAU 1604, which connects to an array of optical fibers. Both sub-assemblies include optical elements to shape and guide light propagating along a path 1603 between the FAU 1604 in the array and a photonic port 1618 at the surface of the PIC 401. As shown, sub-assembly 1610 includes a lens 1607 and sub-assembly 1620 includes a reflector 1608 and a lens 1609. The sub-assembly 1610 includes an interface 1610a with a pair of protruding connecting pins 1612, which mate with corresponding sockets 1613 in the sub-assembly 1620. Other implementations can have more or fewer pins and/or additional pins arranged at different locations of the interface along the Y-axis. Generally, the pins and sockets are arranged to not obscure the optical path 1603 and to provide a robust connection between the sub-assemblies with sufficient alignment accuracy to reliably align the optical elements in the two sub-assemblies along the path 1603. Moreover, the sub-assemblies can be connected by hand, without any special tooling or machine alignment. The sub-assemblies can also facilitate easy replacement of optical components in the assembly, such as a lens array, PBS, or the FAU, without having to realign optics with the photonic ports of the PIC upon replacement.
The interfaces can provide translational alignment along one or more axes to an accuracy of 20 microns or less, e.g., 15 microns or less, 10 microns or less, such as about 5 microns. The interfaces can provide angular alignment to within 0.3° or less, e.g., 0.2° or less, 0.1° or less, 0.05° or less, such as about 0.02°.
While the present example includes pins exclusively on the first sub-assembly and sockets exclusively on the second sub-assembly, other implementations are possible. For example, the second sub-assembly can include exclusively pins or both sub-assemblies can include both pins and sockets. Generally, the pins and sockets can be provided in any suitable pattern and can have any shape suitable for facilitating secure and precise attachment. For example, the pins can be cylindrical, conical, or have a polygonal (e.g., square, rectangular, cross-shaped) or other cross-sectional shape (e.g., a segment of a circle). In certain examples, the pins can have length on the order of 0.1 mm to 10 mm and an aspect ratio in a range from 0.1 to 10 (e.g., cross-sectional dimension of 0.05 mm to 1 mm). The pins can be formed from any material that has suitable mechanical strength and is compatible with fabrication techniques that yield sufficient precision for alignment of the sub-assemblies. In some examples, the pins can be formed from a metal (e.g., aluminum or copper) or metals (e.g., a metal alloy, e.g., steel), a polymer, or a ceramic.
Furthermore, in certain examples, the connecting interfaces of sub-assemblies can include alternative mating features in addition or as an alternative to the sockets/pins. Moreover, other surfaces at the interfaces can serve as fiducial surfaces for alignment. For example, in some examples the interfaces include planar surfaces that touch each other when the sub-assemblies are connected, providing alignment along a corresponding axis (e.g., orthogonal to the surfaces).
While the assembly depicted in
In this configuration, the sub-assemblies connect through vertical interfaces (with respect to the PIC surface) and at a number of different components. However, in some cases, sub-assemblies can connect at horizontal interfaces. For example, referring to
Other sub-assembly divisions are possible. For example, the interface can include both horizontal and vertical portions, or can connect along segments defined by more complex shapes (e.g., steps, diagonal lines, and/or curves). Moreover, regarding assembly 1300, there are several alternative divisions of the optical components with respect to the two sub-assemblies. For instance, the interface can be formed between lens array 516 and spacer 512, between spacer 512 and PBS 522, between PBS 522 and reflector 520, and/or between reflector 520 and polarization rotator 532. Generally, the division of components can be selected based on which components can tolerate a larger degree of misalignment without significantly affecting optical signal transmissions.
As described herein in detail, the present disclosure includes a number of practical applications having features described herein that provide benefits and/or solve problems associated with providing a multi-node computing system with sufficient memory, processing, bandwidth, and energy efficiency constraints for effective operation of AI and/or ML models. Some example benefits are described herein with reference to various features and functionalities provided by the computing system as described. It will be appreciated that benefits explicitly described with reference to one or more examples described herein are provided by way of example and are not intended to be an exhaustive list of all possible benefits of the computing system.
For example, the various circuit packages described herein, and connections thereof may enable the construction of complex topologies of compute and memory nodes that can best serve a specific application. In a simple example, a set of photonic channels connect memory circuit packages with memory nodes (e.g., memory resources) to one or more compute circuit packages with compute nodes. The compute circuit packages, and memory circuit packages can be connected and configured in any number of network topologies which may be facilitated through the use of one or more photonic channels include optical fibers. This may provide the benefit of relieving distance constraints between nodes (compute and/or memory) and, for example, the memory circuit packages can physically be placed arbitrarily far from the compute circuit packages (within the optical budget of the photonic channels).
The various network topologies may provide significant speed and energy savings. For example, photonic transport of data is typically more efficient than an equivalent high-bandwidth electrical interconnect in an EIC of the circuit package itself. By implementing one or more photonic channels, the electrical cost of transmitting data may be significantly reduced. Additionally, photonic channels are typically much faster than electrical interconnects, and thus the use of photonic channels permits the grouping and topology configurations of memory and compute circuit packages that best serve the bandwidth and connectivity needs of a given application. Indeed, the architectural split of memory and compute networks allows each to be optimized for the magnitude of data, traffic patterns, and bandwidth of each network applications. A further added benefit is that of being able to control the power density of the system by spacing memory and compute circuit packages to optimize cooling efficiency, as the distances and arrangements are not dictated by electrical interfaces.
The described compute and memory nodes and fabric of communication links including the modulators and electrical interconnects described above provide a distributed data processing environment, which may be referred to as a fabric-based environment, on which programs can be run. A compute node or memory node in such an environment will generally have installed on it a software stack that runs on one or more processors of the node to provide an operating environment, which may be referred to as a layer, on which program software deployed to the node can run.
The compute and memory nodes of a particular environment can be homogeneous, i.e., all the compute nodes are basically the same and all the memory nodes are basically the same, or they can be heterogeneous.
A compute node has one or more processors that can perform data processing operations, e.g., by executing program instructions, by performing operations implemented in hardware or firmware, by routing a data packet through the electrical interface, or otherwise. The processors can include, for example, CPUs, accelerators of various kinds, e.g., GPUs (graphics processing units), TPUs (tensor processing units), DPUs (data processing units), or programmed FPGAs (field-programmable gate arrays) or other special purpose ASICs (application specific integrated circuits), or by a combination of two or more of them.
A compute node generally has or is directly connected electrically to local memory, e.g., HBM, DDR, L1 and L2 caches, registers and the like.
A memory node, while it may have processors to run software and may have other characteristics of a compute node, has as its primary purpose in a fabric-based environment the purpose of providing access to data, specifically, for example, for use by compute processes running on compute nodes, and to enable other nodes to read and write data over photonic channels connecting the memory node to the other nodes. The memory devices a memory node has for storing data can be of one or more types. They are connected through respective memory controllers, message routers, and photonic interfaces through which other nodes read and write data by sending messages to ports implemented on the memory node.
Compute and memory nodes can have memory devices of one or more kinds, including, for example, flash memory, read-only memory, random-access memory (RAM), static RAM, dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) based DRAM, or high bandwidth memory (HBM) memory, or a combination of two or more of them.
Unidirectional photonic links have a photonic transmitter at one end and a photonic receiver at the other end linked by an optical waveguide, e.g., a semiconductor waveguide or an optical fiber.
Generally, a photonic channel used in a fabric-based environment is a bidirectional photonic channel, which has at least two unidirectional photonic links that transmit in opposite directions, providing, for example, for the transmission of messages in one direction and acknowledgements in the other.
In some implementations, the nodes of a fabric-based environment include routers to route data from one node, directly or through intermediary nodes, to another. Generally, data is transferred in messages over photonic or electrical channels in response to programs executing on the nodes or to operations of memory controllers or similar devices, for example. Such messages can be sent point-to-point, when the two nodes have links directly connect them, or through routers on one or more intermediary nodes that route messages according to addressing data that is part of the messages.
In some implementations, a compute node will have multiple ports, electrical or photonic or both, each directly connected by a link or channel, e.g., bidirectional channel, to a respective other node; and the messages sent by the compute node will be routed to the messages' target nodes by a router on the compute node that directs the messages to the appropriate port on the compute node. When a data message is received over a port, the router on the receiving node will examine the message header to determine the destination node in the fabric, either the node itself or another node, and process the message accordingly.
The addressing of messages through the fabric-based environment can be implemented in a variety of ways. In some implementations, multiple methods are implemented in the same fabric-based environment. In some addressing methods, messages carry the actual address of the message destination, and routers in the fabric implement what in effect are routing tables to transmit messages toward their destination addresses. In some implementations, the routing tables are updated dynamically in response to information about device failures or losses of connections, for example. In other addressing methods, messages are routed by relative addresses, i.e., addresses expressed as directional steps from the current node. Modeling nodes as points on a 2D, 3D, or higher dimensional grid, a target destination can be represented in a message header as a number of steps, which may be positive, negative, or zero, in each of the dimensions. When a message has been transmitted, the receiving node can update the message header of the message to account for the steps taken by the message from the sender in each dimension, with the result that the message header now contains a relative address relative to the receiving node. In other addressing methods, a combination of direct and relative addresses is used.
Memory nodes can be interconnected by photonic links, e.g., in the form of bidirectional photonic channels, to form a memory fabric. The memory fabric can be part of a server and generally includes multiple nodes in one or more packages. A package can include hundreds of nodes extending in multiple dimensions. A fabric made up of multiple packages can have hundreds of thousands of nodes or more, connected by photonic channels in a 2D, 3D, or higher dimensional memory fabric when the nodes have a sufficient number of photonic ports.
Generally, a fabric-based environment is implemented using packages of nodes. A package, sometimes called a System in Package (SiP), includes multiple nodes that are interconnected potentially both at an electrical layer of the package and on an interconnection substrate, e.g., a PIC, and which can be enclosed in a single casing. Each of the nodes in a package can have electrical connections, photonic connections, or both to other nodes within the package. Connections within a package are referred to as intra-chip connections, with the substrate being considered a chip. Connections between nodes in different packages are referred to as inter-chip connections.
In an environment with multiple packages, some, or all of the nodes in one package have inter-chip photonic connections to nodes in one or more other packages. Generally, these inter-chip photonic connections are made by bidirectional photonic channels.
Generally, a program that runs on a fabric-based environment will be made up of program modules, each constructed to run on one of the nodes of the environment. Generally, each module includes instructions to invoke the services of the software stack on which it is running or of the underlying physical devices of the node, to load and store data, locally or remotely, to perform computing and control operations, and to communicate and coordinate with other modules of the program running on the same node or on other nodes on which the program has also been deployed.
Each of the one or more modules that make up a program can be coded separately for a respective particular kind of node. Or a large program can be broken up automatically, e.g., by a compiler, into separately deployable components to run on the nodes of a fabric-based environment. The environment and the resources available in its nodes and the characteristics of its connections, are described by a physical topology, to define, for example, the target for which the compiler is generating executable code.
A program or the modules of a program can generally be programmed using any suitable procedural, interpreted, or declarative language, or combinations of them, from which executable or interpretable code is automatically generated, e.g., by a compiler, to run on some run-time environment, for example, on some node hardware or some software layer or layers installed on the hardware.
A physical topology generally describes the locations of the nodes, any intra-chip connections, and inter-chip connections each node has to other nodes. In some fabric-based environments, nodes are implemented in packages, and the location of a node may also include the package in which it is found. A physical topology may be stored in a topology file that defines an environment for a compiler or for deployment management software.
Program modules and components of the software stack will generally be deployed to nodes through electrical links from a control computer, which may be one of the nodes of the fabric-based environment programmed to perform this function, or which may be a separate control computer. These links can be direct or indirect, and may be provided by an electrical bus, e.g., a PCIe (Peripheral Component Interconnect Express) bus. In some implementations, the photonic links of the fabric-based environment may also be used to deploy modules and components to nodes.
Executable code can be deployed to nodes directly, or, for example, in containers which can be managed by a container management or orchestration system.
A fabric-based environment will generally include one or more nodes that are connected, or can be connected dynamically, to devices external to the fabric. External devices can include devices, for example, to provide human interaction for programs running on the fabric, or to provide data to, or to receive results from, such programs.
The fabric-based environment can be or be part of a general computing environment for executing programs. The computing environment can include or be associated with a compilation environment. The compilation environment takes a program input, e.g., an input machine learning model, and transforms it into machine-readable form by executing a compiler and a code generator. An input machine learning model can be provided in the form of a TensorFlow model, for example.
The application code generated by the compiler and code generator is, in some implementations, provided to a runtime environment running on the nodes of the computing environment. The runtime environment provides services to the running application code on the computing environment. In some implementations, the nodes of the computing environment include firmware that performs hardware-related operations, e.g., monitoring and driving hardware components of the computing environment, used by the runtime environment and the application code.
The application and runtime environment run on the compute nodes and use, if and as requested by the application, the resources of the fabric-based environment, including, for example, the compute nodes, memory nodes, memory devices, links and channels, routers, and ports.
As discussed herein in detail, the present disclosure includes a number of practical applications having features described herein that provide benefits and/or solve problems associated with providing a multi-node computing system with sufficient memory, processing, bandwidth, and energy efficiency constraints for effective operation of AI and/or ML models. Some example benefits are discussed herein in connection with various features and functionalities provided by the computing system as described.
For example, the various circuit packages described herein, and connections thereof may enable the construction of complex topologies of compute and memory nodes that can best serve a specific application. In a simple example, a set of photonic channels connect memory circuit packages with memory nodes (e.g., memory resources) to one or more compute circuit packages with compute nodes. The compute circuit packages, and memory circuit packages can be connected and configured in any number of network topologies which may be facilitated through the use of one or more photonic channels include optical fibers. This may provide the benefit of relieving distance constraints between nodes (compute and/or memory) and, for example, the memory circuit packages can physically be placed arbitrarily far from the compute circuit packages (within the optical budget of the photonic channels).
The various network topologies may provide significant speed and energy savings. For example, photonic transport of data is typically more efficient than an equivalent high-bandwidth electrical interconnect in an EIC of the circuit package itself. By implementing one or more photonic channels, the electrical cost of transmitting data may be significantly reduced. Additionally, photonic channels are typically much faster than electrical interconnects, and thus the use of photonic channels permits the grouping and topology configurations of memory and compute circuit packages that best serve the bandwidth and connectivity needs of a given application. Indeed, the architectural split of memory and compute networks allows each to be optimized for the magnitude of data, traffic patterns, and bandwidth of each network applications. A further added benefit is that of being able to control the power density of the system by spacing memory and compute circuit packages to optimize cooling efficiency, as the distances and arrangements are not dictated by electrical interfaces.
This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed, perform the operations or actions. That special-purpose circuitry is configured to perform particular operations or actions means that the circuitry circuit elements that, when put into operation, perform the operations or actions.
This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed, perform the operations or actions. That special-purpose circuitry is configured to perform particular operations or actions means that the circuitry circuit elements that, when put into operation, perform the operations or actions.
The articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements in the preceding descriptions. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one example” or “an example” of the present disclosure are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features. For example, any element described in relation to an example herein may be combinable with any element of any other example described herein. Numbers, percentages, ratios, or other values stated herein are intended to include that value, and also other values that are “about” or “approximately” the stated value, as would be appreciated by one of ordinary skill in the art encompassed by examples of the present disclosure. A stated value should therefore be interpreted broadly enough to encompass values that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated values include at least the variation to be expected in a suitable manufacturing or production process, and may include values that are within 5%, within 1%, within 0.1%, or within 0.01% of a stated value.
A person having ordinary skill in the art should realize in view of the present disclosure that equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made to examples disclosed herein without departing from the spirit and scope of the present disclosure. Equivalent constructions, including functional “means-plus-function” clauses are intended to cover the structures described herein as performing the recited function, including both structural equivalents that operate in the same manner, and equivalent structures that provide the same function. It is the express intention of the applicant not to invoke means-plus-function or other functional claiming for any claim except for those in which the words ‘means for’ appear together with an associated function. Each addition, deletion, and modification to the examples that falls within the meaning and scope of the claims is to be embraced by the claims.
The terms “approximately,” “about,” and “substantially” as used herein represent an amount close to the stated amount that still performs a desired function or achieves a desired result. For example, the terms “approximately,” “about,” and “substantially” may refer to an amount that is within less than 5% of, within less than 1% of, within less than 0.1% of, and within less than 0.01% of a stated amount. Further, it should be understood that any directions or reference frames in the preceding description are merely relative directions or movements. For example, any references to “up” and “down” or “above” or “below” are merely descriptive of the relative position or movement of the related elements.
The following numbered paragraphs are non-limiting examples of various embodiments of the present disclosure.
Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims.
This application claims the benefit of priority to Provisional Application No. 63/616,465, filed on Dec. 29, 2023, the contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63616465 | Dec 2023 | US |
