BACKGROUND OF THE INVENTION
The present invention is an electronic circuit design method that incorporates fiber optic lines between individual logic gates for transmitting data. Using fiber optics as data transmission between logic circuits would make a simplified logic circuit construction best. Although the design of any logic circuit does not necessarily have to follow this or any suggested design the use of fiber optics for transmitting data between the logic gates is the core of this design method. What's important is the function of the desired circuit. For this reason, schematic symbols are used in electrical, electronic, and computer engineering to represent small complete circuits that have known function. As long as the design proves the truth table, that is associated with that particular logic circuit, correct then the circuit works.
SUMMARY OF THE INVENTION
Each transistor and diode has what is called a propagation delay. This is the amount of time the transistor or diode takes to go from on to off and vice versa. Realizing this the more electronic switches used in a particular device the slower the circuit will be in performing the appropriate function. Using fiber optics to transmit data between logic gates increases the speeds and provides other benefits as well such as lower power consumption and lower possibility of faulty information being transmitted and received. This invention is primarily intended for data transmission and not for power amplification, transformation, or the increasing or decreasing of voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrate the schematic symbol for the buffer circuit.
FIG. 1a illustrates the truth table for the buffer circuit.
FIG. 1b illustrates the buffer circuit using a single BJT transistor.
FIG. 1c illustrates the buffer circuit using a single FET transistor.
FIG. 2 illustrates the schematic symbol for the AND gate circuit.
FIG. 2a illustrates the truth table for the AND gate circuit.
FIG. 2b illustrates the AND gate circuit using two BJT's connected in series.
FIG. 2c illustrates the AND gate circuit using two FET's connected in series.
FIG. 3 illustrates the schematic symbol for the OR gate circuit.
FIG. 3a illustrates the truth table for the OR gate circuit.
FIG. 3b illustrates the OR gate circuit using two BJT's connected in parallel.
FIG. 3c illustrates the OR gate circuit using two FET's connected in parallel.
FIG. 4 illustrates the schematic symbol for the inverter or NOT gate circuit.
FIG. 4a illustrates the truth table for the inverter or NOT gate circuit.
FIG. 4b illustrates the inverter or NOT gate circuit using a single BJT.
FIG. 4c illustrates the inverter or NOT gate circuit using a single FET.
FIG. 5 illustrates the schematic symbol for the NAND gate circuit.
FIG. 5a illustrates the truth table for the NAND gate circuit.
FIG. 5b illustrates the NAND gate circuit using two BJT's connected in series.
FIG. 5c illustrates the NAND gate circuit using two FET's connected in series.
FIG. 6 illustrates the schematic symbol for the NOR gate circuit.
FIG. 6a illustrates the truth table for the NOR gate circuit.
FIG. 6b illustrates the NOR gate circuit using two BJT's connected in parallel.
FIG. 6c illustrates the NOR gate circuit using two FET's connected in parallel.
FIG. 7 illustrates a circuit design using the schematic symbols for the logic gate circuits.
FIG. 7a illustrates a detailed schematic of how the logic gates would connect to each other using BJT transistors.
FIG. 7b illustrates a detailed schematic of how the logic gates would connect to each other using FET transistors.
DETAILED DESCRIPTION
The schematic symbols in FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are like a short hand that is used to describe know functions of certain circuits. Instead of drawing the complete circuits the industry uses these symbols to describe a particular function on a schematic.
The truth tables in FIG. 1a, FIG. 2a, FIG. 3a, FIG. 4a, FIG. 5a, and FIG. 6a, are a mathematical description of the function of how each logic gate functions. The letters at the top of the truth table correspond to inputs and outputs on the circuits with the same labels. The numbers, 1's and 0's, are a universal representation of binary communication. The 1's are logical highs and in this case represent an input or output that is equal to the power source. The 0's are logical lows and in this case represent no input or output or 0 volts.
FIG. 1b is an illustration of a buffer circuit using a single BJT (Bipolar Junction Transistor), Q1. The photodiode, D1 is in it's photoconductive mode or reverse biased and is connected to the base of Q1. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the base of Q1 turning it on. Once Q1 is turned on it will connect a positive voltage to the anode of the LED, D2, forward biasing it. Once D2 is forward biased it will turn on and apply light though the fiber-optic lines through output ‘Y’. This would prove the truth table in FIG. 1a correct in that every logical high input will yield a logical high output. This design method is applicable to all types of BJT's.
FIG. 1c is an illustration of a buffer circuit using a single FET (Field Effect Transistor), Q1. The photodiode, D1 is in it's photoconductive mode or reverse biased and is connected to the gate of Q1. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the gate of Q1 turning it on. Once Q1 is turned on it will connect a positive voltage to the anode of the LED, D2, forward biasing it. Once D2 is forward biased it will turn on and apply light though the fiber-optic lines through output ‘Y’. This arrangement would prove the truth table in FIG. 1a correct in that every logical high input will yield a logical high output. This design method is applicable to all types of FET's.
FIG. 2b is an illustration of an AND gate circuit using more than one BJT (Bipolar Junction Transistor), Q1 and Q2 connected in series from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the base of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the base of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the base of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the base of Q2 turning it on. Once both Q1 and Q2 is turned on they will connect a positive voltage to the anode of the LED, D3, forward biasing it. Once D2 is forward biased it will turn on and apply light though the fiber-optic lines through output ‘Y’. This arrangement would prove the truth table for an AND gate in FIG. 2a correct in that all logical high inputs will yield a logical high output. This design method includes all types of BJT's.
FIG. 2c is an illustration of an AND gate circuit using more than one FET (Field Effect Transistor), Q1 and Q2 connected in series from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the gate of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the gate of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the gate of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the gate of Q2 turning it on. Once both Q1 and Q2 is turned on they will connect a positive voltage to the anode of the LED, D3, forward biasing it. Once D2 is forward biased it will turn on and apply light though the fiber-optic lines through output ‘Y’. This arrangement would prove the truth table for an AND gate in FIG. 2a correct in that all logical high inputs will yield a logical high output. This design method includes all types of FET's.
FIG. 3b is an illustration of an OR gate circuit using more than one BJT (Bipolar Junction Transistor), case Q1 and Q2 connected in parallel from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the base of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the base of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the base of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the base of Q2 turning it on. Once either Q1 or Q2 is turned on they will connect a positive voltage to the anode of the LED, D3, forward biasing it. Once D2 is forward biased it will turn on and apply light though the fiber-optic lines through output ‘Y’. This arrangement would prove the truth table for an OR gate in FIG. 3a correct in that any logical high input will yield a logical high output. This design method includes all types of BJT's.
FIG. 3c is an illustration of an OR gate circuit using more than one FET (Field Effect Transistor), Q1 and Q2 connected in parallel from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the gate of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the gate of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the gate of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the gate of Q2 turning it on. Once either Q1 or Q2 is turned on they will connect a positive voltage to the anode of the LED, D3, forward biasing it. Once D2 is forward biased it will turn on and apply light though the fiber-optic lines labeled output ‘Y’. This arrangement would prove the truth table for an OR gate in FIG. 3a correct in that any logical high input will yield a logical high output. This design method includes all types of FET's.
FIG. 4b is an illustration of a inverter or (NOT gate) circuit using a single BJT (Bipolar Junction Transistor), Q1. The photodiode, D1 is in it's photoconductive mode or reverse biased and is connected to the base of Q1. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the base of Q1 turning it on. Once Q1 is turned on it will shunt current away from the LED, D2, turning it off. Once D2 is off it will not apply light though the fiber-optic lines labeled output ‘Y’. This would prove the truth table in FIG. 4a correct in that every logical high input will yield a logical low output. This design method is applicable to all types of BJT's.
FIG. 4c is an illustration of an inverter or (NOT gate) circuit using a single FET (Field Effect Transistor), Q1. The photodiode, D1 is in it's photoconductive mode or reverse biased and is connected to the gate of Q1. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the gate of Q1 turning it on. Once Q1 is turned on it will shunt current away from the LED, D2, turning it off. Once D2 is off it will not apply light though the fiber-optic lines labeled output ‘Y’. This would prove the truth table in FIG. 4a correct in that every logical high input will yield a logical low output. This design method is applicable to all types of FET's.
FIG. 5b is an illustration of a NAND gate circuit using more than one BJT (Bipolar Junction Transistor), Q1 and Q2 connected in series from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the base of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the base of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the base of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the base of Q2 turning it on. Once both Q1 and Q2 is turned on they will shunt current away from the LED, D3, turning it off. If D3 is off it will not apply light though the fiber-optic lines labeled output ‘Y’. This arrangement would prove the truth table for an NAND gate in FIG. 5a correct in that all logical high inputs will yield a logical low output. This design method includes all types of BJT's.
FIG. 5c is an illustration of a NAND gate circuit using more than one FET (Field Effect Transistor), Q1 and Q2 connected in series from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the gate of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the gate of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the gate of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the gate of Q2 turning it on. Once both Q1 and Q2 is turned on they will shunt current away from the LED, D3, turning it off. If D3 is off it will not apply light though the fiber-optic lines labeled output ‘Y’. This arrangement would prove the truth table for an NAND gate in FIG. 5a correct in that all logical high inputs will yield a logical low output. This design method includes all types of FET's.
FIG. 6b is an illustration of an NOR gate circuit using more than one BJT (Bipolar Junction Transistor), Q1 and Q2 connected in parallel from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the base of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the base of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the base of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the base of Q2 turning it on. Once either Q1 or Q2 is turned on they will shunt current away from the LED, D3, turning it off. Once D3 is off it will not apply light though the fiber-optic lines labeled output ‘Y’. This arrangement would prove the truth table for an OR gate in FIG. 5a correct in that any logical high input will yield a logical low output. This design method includes all types of BJT's.
FIG. 6c is an illustration of an NOR gate circuit using more than one FET (Field Effect Transistor), Q1 and Q2 connected in parallel from power to ground. The photodiode, D1, is in it's photoconductive mode or reverse biased and is connected to the gate of Q1. The photodiode, D2 is in it's photoconductive mode or reverse biased and is connected to the gate of Q2. When light is applied to the fiber-optic line through input ‘A’, D1 will connect a positive voltage to the gate of Q1 turning it on. When light is applied to the fiber-optic line through input ‘B’, D2 will connect a positive voltage to the gate of Q2 turning it on. Once either Q1 or Q2 is turned on they will shunt current away from the LED, D3, turning it off. Once D3 is off it will not apply light though the fiber-optic lines labeled output ‘Y’. This arrangement would prove the truth table for an OR gate in FIG. 6a correct in that any logical high input will yield a logical low output. This design method includes all types of FET's.
As seen in FIG. 7a illustrates how the logic gates themselves will connect to each other by fiber-optic transmission lines using BJT's. FIG. 7b illustrates how the logic gates themselves will connect to each other by fiber-optic transmission lines using FET's. enabling the design of faster, more efficient, and less error prone integrated circuits. Each of them have inputs labeled ‘A’, ‘B’, ‘C’, and ‘D’ and an output labeled ‘Y’. These illustrations are examples of connections between logic circuits and not actual logic gates themselves.
Patent Application
20200083887
