Field emission devices having structure for reduced emitter tip to gate spacing

Abstract

An improved structure and method are provided to decouple the gate dielectric thickness and the emitter tip to gate layer distance by etching the dielectric using ion bombardment. The ion bombardment, or ion etch, is performed prior to depositing the gate layer. The improved structure and method will allow a smaller distance between the emitter tip and the gate structure without having to decrease the thickness of the gate insulator layer. The smaller emitter tip to gate distance lowers the turn-on voltage which is highly desirable in such areas as beam optics and power dissipation.

Description

FIELD OF THE INVENTION

The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a structure and method for reduced emitter tip to gate spacing in field emission devices.

BACKGROUND OF THE INVENTION

Recent years have seen an increased interest in field emission devices. This is attributable to the fact that such displays can fulfill the goal of consumer affordable hang-on-the-wall flat panel television displays with diagonals in the range of 20 to 60 inches. Certain field emission devices, or flat panel displays, operate on the same physical principle as fluorescent lamps. A gas discharge generates ultraviolet light which excites a phosphor layer that fluoresces visible light. Other field emission devices operate on the same physical principles as cathode ray tube (CRT) based displays. Excited electrons are guided to a phosphor target to create a display. Silicon-based field emitter arrays are one source for creating similar displays.

Single crystalline silicon structures have been under investigation for some time for use in fabricating field emission devices. However, large area, TV size, displays are likely to be expensive and difficult to manufacture from single crystal silicon wafers. Polycrystalline silicon, on the other hand, provides a viable substitute to single crystal silicon since it can be deposited over large areas on glass or other substrates.

The resolution of a field emission display is a function of a number of factors, including emitter tip sharpness, alignment and spacing of the gates, or grid openings, which surround the tips. One of the key issues in the development of field emission devices (FEDs) is the emitter tip to gate distance. This distance partly determines the turn-on voltage, the voltage difference required between the tip and the grid to start emitting electrons. Typically, the smaller the distance, the lower the turn-on voltage for a given field emitter, and hence lower power dissipation. A low turn-on voltage also improves the beam optics. Thus it is desirable to minimize the emitter tip to gate distance in the development of field emission devices (FED).

There are numerous methods to fabricate FEDs. One such popular technique in the industry includes the “Spindt” method, named after an early patented process. Spindt, et. al. discuss field emission cathode structures in U.S. Pat. Nos. 3,665,241, 3,755,704, and 3,812,559. Generally, the Spindt technique entails the conventional steps of masking insulator layers and then includes lengthy etching, oxidation, and deposition steps. In the push for more streamlined fabrication processes, the Spindt method is no longer the most efficient approach. Moreover, the Spindt process does not resolve or necessarily address the problem of gate to emitter tip distance.

The emitter tip to gate spacing is generally determined by the thickness of the dielectric layer in place between the two. One method of achieving a smaller emitter tip to gate distance is to deposit a thinner dielectric, or insulator layer. However, this approach has the negative consequence of increasing the capacitance between the gate and substrate regions. In turn, the increased capacitance increases the response time of the field emission device.

A more recent technique includes the use of chemical mechanical planarization (CMP) and an insulator reflow step. One such method is presented in U.S. Pat. No. 5,229,331, entitled “Method to Form Self-Aligned Gate Structures Around Cold Cathode Emitter Tips Using Chemical Mechanical Polishing Technology.” Unfortunately, an insulator reflow process generally involves the use of an extra processing step to lay down an extra insulator layer. Also, the typical reflow dielectric materials employed, e.g., borophosphorus silicate glass (BPSG), require high processing temperatures to generate the reflow. This fact negatively impacts the thermal budget available in the fabrication sequence.

Thus, what are needed are a structure and method to decouple the gate dielectric, or insulator, thickness and the emitter tip to gate distance. It is further desirable to develop such a structure and method which can be incorporated into large population density field emitter arrays without compromising the responsiveness and reliability of the resulting field emission devices. Likewise, it is desirable to obtain these results through an improved and streamlined manufacturing technique.

SUMMARY OF THE INVENTION

The above-mentioned problems with field emission devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method which accord improved performance are provided.

In particular, an illustrative embodiment of the present invention includes a method for forming a self-aligned gate structure around an electron emitting tip. The method includes forming a cathode on a substrate. The cathode includes an emitter tip. An insulator layer is formed over the cathode and the emitter tip. The insulator is ion etched and a gate is formed on the insulator layer.

In another embodiment, a method of forming a field emission device on a substrate is provided. The method includes forming a cathode emitter tip in a cathode region of the substrate. A gate insulator layer is formed on the emitter tip and the substrate. An ion etch process is used in order to reduce the thickness of the gate insulator layer in the cathode region more rapidly than in the isolation region. Further, the method includes forming a gate on the gate insulator layer and an anode is formed opposing the emitter tip.

In another embodiment, a field emitter array is provided. The field emitter array includes a number of cathodes which are formed in rows along a substrate. A gate insulator is formed along the substrate and surrounds the cathodes. A number of gate lines are formed on the gate insulator. And, a number of anodes are formed in columns orthogonal to and opposing the rows of cathodes. The field emitter array is formed according to a method which includes the following: forming a number of cathode emitter tips in cathode regions of the substrate, forming a gate insulator layer on the emitter tips and the substrate such that forming the gate insulator layer includes ion etching the insulator layer such that the insulator layer is formed thinner around the emitter tips than in an isolation region of the substrate, forming a number of gate lines on the gate insulator layer, and forming a number of anodes opposite the emitter tips.

Thus, an improved structure and method are provided which will allow a smaller distance between the emitter tip and the gate structure without having to decrease the thickness of the gate dielectric which increases capacitance. A smaller emitter tip to gate distance lowers the turn-on voltage which is highly desirable in such areas as beam optics and power dissipation. The improved method and structure include the use of an energetic ion etch. Including the etch process removes portions of the sloped surface of a conformally covered emitter tip more rapidly than the flat portions of the gate isolation layer or surface. The method promotes a streamlined fabrication sequence and yields a structure with improved performance.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1F illustrate an embodiment of a process of fabrication of a field emission device according to the teachings of the present invention.

FIG. 2 is a planar view of an embodiment of a portion of an array of polysilicon field emitters according to the teachings of the present invention.

FIG. 3 is a block diagram which illustrates an embodiment of a flat panel display system according to the teachings of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

FIGS. 1A-1F illustrate an embodiment of a process of fabrication of a field emission device according to the teachings of the present invention. The field emission device is formed using a self-aligned technique for positioning a gate around cathode emitter tips. In FIG. 1A , a cathode emitter tip 101 is illustrated formed on a substrate 100 . In one embodiment the substrate 100 includes a single crystalline silicon layer 100 . In an alternative embodiment, the substrate includes an insulator layer formed from glass, wherein glass includes silicon dioxide (SiO 2 ) alone or in combination with other suitable/appropriate elements as understood by one of ordinary skill in the art. The cathode emitter tip 101 is formed in a cathode region 125 of the substrate 100 . The cathode emitter tip 101 , or emitter tip 101 , is formed using any suitable technique such as the method provided in U.S. Pat. No. 5,229,331, entitled “Method to Form Self-Aligned Gate Structures Around Cold Cathode Emitter Tips Using Chemical Mechanical Polishing Technology.” The emitter tip 101 is formed as a polysilicon cone 101 . In one embodiment, the emitter tip 101 includes a low work function material 118 , as shown in FIG. 1F , coated on the emitter tip 101 . The low work function material can include forming a metal silicide 118 on the field emitter tip 101 . Forming metal silicide 118 will be understood by one of ordinary skill in the art of semiconductor fabrication.

FIG. 1B illustrates the structure following the next sequence of processing steps. In FIG. 1B , a gate insulator layer 102 , or insulator layer 102 , is formed over the emitter tip 101 and the substrate 100 . The insulator layer 102 surrounds the emitter tip 101 . The regions of the insulator layer 102 which surround the emitter tip 101 constitute an insulator region 112 for the field emitter device. In one embodiment, the insulator layer 102 includes silicon dioxide (SiO 2 ). In an alternative embodiment, the insulator layer 102 includes silicon nitride (Si 3 N 4 ), or any other suitable gate insulator material as recognized by one of ordinary skill in the art. The insulator layer 102 may be formed by any suitable technique as such techniques are understood by those of ordinary skill in the art of semiconductor and field emission device fabrication. One exemplary technique for forming the insulator layer 102 includes chemical vapor deposition (CVD).

FIG. 1C illustrates the device following the next sequence of fabrication steps. In FIG. 1C the insulator layer 102 undergoes an ion etching process. In the ion etching process, the ions impinge on the insulator layer 102 in perpendicular fashion to the insulator 102 surface, as indicated by arrows 130 . In one embodiment, the ion etch is performed using an ion gun for sourcing the ions toward the insulator layer 102 . Various ion guns, suitable in this process, are commercially available as will by recognized by one of ordinary skill in the art semiconductor and field emission device fabrication. In an alternative embodiment, the ions are plasma generated and become targeted toward the insulator layer 102 upon a proper biasing of the insulator layer 102 and substrate 100 . Additionally, any suitable gas may be chosen as the ion source gas in the plasma chamber. In one embodiment, an Oxygen gas is employed. In an alternative embodiment, Argon is utilized as the reactant gas.

The ion etching process serves to reduce the insulator layer 102 thickness more rapidly in the cathode region 125 , surrounding the emitter tip 101 . The etch rate, using energetic ions, depends not only on the energy of the ions and the nature of the material being etched but also depends highly on the angle at which the ions bombard the surface. The ions impinge at a ninety (90) degree angle relative to the substrate 100 . However, as indicated by arrows 130 , the ions impinge the surface of the insulator layer 102 in the cathode region 125 at an angle of less than ninety degrees (<90). This is due to the fact that the insulator layer 102 in the cathode region 125 is formed conformal to the cathode emitter tip 101 . Thus, in comparison the insulator layer 102 assumes a sloped form over the cathode region 125 and a planar structure in the insulator region 112 . The ion bombardment impinging the sloped insulator layer 102 covering the emitter tip 101 reduces the insulator layer 102 thickness over the emitter tip 101 more rapidly than over the planar, insulator regions 112 . The insulator layer 102 is etched back in this manner to a desired thickness. In one embodiment, to protect the emitter tip 101 from over etching, a sacrificial buffer layer is deposited over the emitter tip 101 prior to etching. The buffer layer can be either a dielectric layer, such as silicon nitride (Si 3 N 4 ), or a conductive layer with a slower etch rate than the insulator layer 102 . The structure is now as appears in FIG. 1 C.

FIG. 1D illustrates the structure following the next sequence of fabrication steps. A gate, or gate layer 116 , is formed on the insulator layer 102 . The gate layer 116 includes any conductive layer material and can be formed using any suitable technique. One exemplary technique includes chemical vapor deposition (CVD). In one embodiment the gate layer 116 is formed of doped polysilicon material. In an alternative embodiment, the gate layer 116 is a refractory metal. In this embodiment, the refractory metal can include any one from the selection of molybdenum (Mo), tungsten (W), or Titanium (Ti). Forming the gate layer 116 includes depositing the conductive gate material to a thickness sufficient to cover the entire insulator layer 102 including the portion of the insulator layer 102 above the emitter tip 101 .

FIG. 1E illustrates the structure following the next series of processing steps. Following deposition, the gate layer 116 undergoes a removal step using chemical mechanical planarization (CMP). The gate layer 116 is removed using CMP until a portion of the insulator layer 102 , covering the emitter tip 101 , is revealed. The earlier ion etching step has here resulted in an aperture 129 defined by the gate layer 116 opening above the emitter tip 101 . The thickness of the insulator layer 102 , between the gate layer 116 and the emitter tip 101 is significantly less than the thickness of the insulator layer 102 extending between the gate layer 116 and the substrate 100 .

FIG. 1F illustrates the structure after the next sequence of processing steps. Here, a portion of the insulator layer 102 is removed from surrounding the emitter tip 101 . The portion of the insulator layer 102 is removed using any suitable technique as will be understood by one of ordinary skill in the field of semiconductor processing and field emission device fabrication. In one exemplary embodiment, a wet etch is used such as a buffered oxide etch process (BOE), to remove portions of the insulator layer 102 . A low work function material 118 can be deposited on the emitter tip 101 at this stage. The low work function material 118 may be deposited using a CVD process. An anode 127 is further formed opposing the emitter tip 101 in order to complete the field emission device. The formation of the anode, and completion of the field emission device structure, can be achieved in numerous ways as will be understood by those of ordinary skill in the art of semiconductor and field emission device fabrication. The formation of the anodes, and completion of the field emission device itself, do not form part of the present invention and as such are not presented in full detail here.

Embodiments of the present invention include the fabrication of a field emitter array which is fabricated according to the method and teachings provided above. FIG. 2 is a planar view of an embodiment of a portion of an array of field emitter devices, 50 A, 50 B . . . 50 N, each constructed according to the teachings of the present invention. The field emitter array 205 is suited to inclusion in a field emission device. The field emitter array 205 includes a number of cathodes, 201 1 , 201 2 , 201 3 , . . . 201 n formed in rows along a substrate 200 . A gate insulator 202 is formed along the substrate 200 and surrounds the cathodes. A number of gate lines 216 are on the gate insulator. A number of anodes, 227 1 , 227 2 , 227 3 , . . . 227 n are formed in columns orthogonal to and opposing the rows of cathodes. The anodes, 227 1 , 227 2 , 227 3 , . . . 227 n include multiple phosphors. And, the intersection of the rows of cathodes, 201 1 , 201 2 , 201 3 , . . . 201 n and columns of anodes, 227 1 , 227 2 , 227 3 , . . . 227 n form pixels.

Each field emitter device in the array, 50 A, 50 B, . . . , 50 N, is constructed in a similar manner. Thus, only one field emitter device 50 N is described herein in detail. All of the field emitter devices are formed along the surface of a substrate 200 according to the method presented in connection with FIGS. 1A-1F . In one embodiment, the substrate includes a doped silicon substrate 200 . In an alternate embodiment, the substrate is a glass substrate 200 , including silicon dioxide (SiO 2 ) alone or in combination with other appropriate elements as understood by one of ordinary skill in the art. Field emitter device 50 N includes a cathode 201 formed in a cathode region 225 of the substrate 200 . The cathode 201 includes an emitter tip 201 which is a polysilicon cone 201 . In one exemplary embodiment, the polysilicon cone 201 includes a metal silicide 218 on the polysilicon cone 201 . The metal silicide 218 can include any one from a number of refractory metals, e.g. molybdenum (Mo), tungsten (W), or titanium (Ti), which has been deposited on the polysilicon cone 201 . Formation of the metal silicide 218 includes using the process of chemical vapor deposition (CVD) to deposit the refractory metal, and then, includes a rapid thermal anneal (RTA) to form the silicide. A gate insulator 202 is formed in an isolation region 212 of the substrate 200 . The gate insulator 202 includes any suitable insulator material, e.g., silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). The gate insulator layer 202 is formed conformally to the polysilicon cone 201 by any suitable process such as by CVD. Next the insulator layer 202 undergoes an ion etch process which is explained in detail and presented above in connection with FIGS. 1A-1F . The insulator layer 202 remains only in the isolation regions 212 of the array 205 .

The gate 216 is formed on the gate insulator 202 . In one embodiment, the gate 216 is formed of doped polysilicon. In an alternate embodiment, the gate 216 is formed of any other suitable conductor material, e.g., a refractory metal or, alternatively doped polysilicon. The gate 216 and the polysilicon cone 201 are formed using a self-aligned technique which is discussed above in connection with fabricating a field emitter device. An anode 227 opposes the emitter tip 201 . The separation of the gate 216 and the emitter tip 201 by the insulator layer 202 is significantly thinner than the separation distance of the gate 216 and the substrate 200 by the insulator layer 202 . The thinner separation thickness of the insulator layer 202 between the gates 216 and the emitter tips 201 is produced using an ion etch process as described above in connection with FIGS. 1A-1F .

FIG. 3 is a block diagram which illustrates an embodiment of a flat panel display system 300 according to the teachings of the present invention. A flat panel display includes a field emitter array 304 formed on a glass substrate. The field emitter array includes the field emitter array described and presented above in connection with FIG. 2. A row decoder 306 and a column decoder 308 each couple to the field emitter array 304 in order to selectively access the array. Further, a processor 310 is included which is adapted to receiving input signals and providing the input signals to address the row and column decoders, 306 and 308 respectively.

Conclusion

Thus, an improved structure and method are provided which will allow a smaller distance between the emitter tip and the gate structure. The structure is achieved without having to decrease the thickness of the gate dielectric, or insulator layer, which would carry the negative effect of increased capacitance. A smaller emitter tip to gate distance lowers the turn-on voltage which is highly desirable in such areas as beam optics and power dissipation. The improved method and structure include the use of an energetic ion etch. Including the etch process removes portions of the sloped insulator layer surface of a conformally covered emitter tip more rapidly than flat portions out in the isolation region. This technique avoids the shortcomings and problems of thermal budgets and additional process steps encountered when using reflow techniques. The method promotes a streamlined fabrication sequence and yields a structure with improved performance.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A field emitter array, comprising:a number of cathode emitter tips formed in rows along a substrate; a single gate insulator having a thickness that is thinner than a height of the number of cathode emitter tips, formed along the substrate and surrounding the cathode emitter tips; a number of gate lines formed on the gate insulator; and a number of anodes formed in columns orthogonal to and opposing the rows of cathodes, the field emitter array formed by a method comprising: forming a number of cathode emitter tips in cathode regions of the substrate; forming a single gate insulator layer on the emitter tips and the substrate, wherein forming the single gate insulator layer includes ion etching the insulator layer such that the insulator layer is formed thinner around the emitter tips than in an isolation region of the substrate; forming a number of gate lines on the gate insulator layer; and forming a number of anodes opposite the emitter tips, and wherein a distance separating the number of cathode emitter tips from the number of gates lines is significantly thinner than a separation distance separating the number of gate lines and the substrate.

2. The field emitter array of claim 1, wherein the number of gate lines and the number of cathode emitter tips are formed using a self-aligned technique.

3. The field emitter array of claim 1, wherein the number of cathode emitter tips include polysilicon cones.

4. The field emitter array of claim 3, wherein the number of cathode emitter tips include metal silicides on the polysilicon cones.

5. The field emitter array of claim 1, wherein the substrate includes glass.

6. The field emitter array of claim 1, wherein the number of gate lines include refractory metals.

7. The field emitter array of claim 1, wherein the number of gate lines include doped polysilicon.

8. A flat panel display, comprising:a field emitter array formed on a glass substrate, wherein the field emitter array includes: a number of cathode emitter tips formed in rows along the substrate; a single gate insulator formed along the substrate and surrounding the cathode emitter tips; a number of gate lines formed on the single gate insulator; and a number of anodes formed in columns orthogonal to and opposing the rows of cathodes, wherein the anodes include multiple phosphors, and wherein the intersection of the rows and columns form pixels, the field emitter array formed by a method comprising: forming a number of cathode emitter tips in cathode regions of the substrate; forming a single gate insulator layer on the emitter tips and the substrate, wherein forming the single gate insulator layer includes ion etching the insulator layer such that the insulator layer is formed thinner around the emitter tips than in an isolation region of the substrate; forming a number of gate lines on the gate insulator layer; and forming a number of anodes opposite the emitter tips; wherein a distance separating the number of cathode emitter tips from the number of gates lines is significantly thinner than a separation distance separating the number of gate lines and the substrate; a row decoder and a column decoder each coupled to the field emitter array in order to selectively access the pixels; and a processor adapted to receiving input signals and providing the input signals to the row and column decoders.

9. The flat panel display of claim 8, wherein the number of gate lines and the number of cathode emitter tips are formed using a self-aligned technique.

10. The flat panel display of claim 8, wherein the number of cathode emitter tips include metal silicides on the polysilicon cones.

11. The flat panel display of claim 8, wherein the number of gate lines include refractory metals.

12. A field emitter array, comprising:a number of cathode emitter tips in rows along a substrate; a single gate insulator located along the substrate and surrounding the cathode emitter tips, the single gate insulator having a gate line region thickness that is thinner than a height of the number of cathode emitter tips; a number of gate lines coupled to the gate insulator, wherein a gate line to cathode emitter tip distance between a portion of the gate line and the cathode emitter tip is substantially thinner than the gate line region thickness; and a number of anodes located in columns orthogonal to and opposing the rows of cathode emitter tips.

13. The field emitter array of claim 12, wherein the number of cathode emitter tips include polysilicon cones.

14. The field emitter array of claim 12, wherein the number of gate lines include refractory metals.

15. The field emitter array of claim 12, wherein the number of gate lines include doped polysilicon.

16. A field emitter array, comprising:a number of cathode emitter tips in rows along a substrate; a single gate insulator located along the substrate and surrounding the cathode emitter tips, the single gate insulator having a gate line region thickness that is thinner than a height of the number of cathode emitter tips; a number of gate lines coupled to the gate insulator, wherein a gate line to cathode emitter tip distance between a portion of the gate line and the cathode emitter tip is substantially thinner than the gate line region thickness; and a number of anodes located in columns orthogonal to and opposing the rows of cathode emitter tips; wherein the number of cathode emitter tips include metal silicides on the polysilicon cones.

17. A field emitter array, comprising:a number of cathode emitter tips in rows along a substrate; a single gate insulator located along the substrate and surrounding the cathode emitter tips, the single gate insulator having a gate line region thickness; a number of gate lines coupled to the single gate insulator, wherein a gate line to cathode emitter tip distance between a portion of the gate line and the cathode emitter tip is substantially thinner than the gate line region thickness; and a number of anodes located in columns orthogonal to and opposing the rows of cathode emitter tips.

18. A flat panel display, comprising:a field emitter array formed on a glass substrate, wherein the field emitter array includes: a number of cathode emitter tips in rows along a substrate; a single gate insulator located along the substrate and surrounding the cathode emitter tips, the single gate insulator having a gate line region thickness that is thinner than a height of the number of cathode emitter tips; a number of gate lines coupled to the gate insulator, wherein a gate line to cathode emitter tip distance between a portion of the gate line and the cathode emitter tip is substantially thinner than the gate line region thickness; a number of anodes located in columns orthogonal to and opposing the rows of cathode emitter tips; and a row decoder and a column decoder each coupled to the field emitter array; and a processor adapted to receiving input signals and providing the input signals to the row and column decoders.

19. The flat panel display of claim 18, wherein the number of gate lines and the number of cathode emitter tips are formed using a self-aligned technique.

20. The flat panel display of claim 18, wherein the number of cathode emitter tips include metal silicides on polysilicon cones.

21. The flat panel display of claim 18, wherein the number of gate lines include refractory metals.

22. A flat panel display, comprising:a field emitter array formed on a glass substrate, wherein the field emitter array includes: a number of cathode emitter tips in rows along a substrate; a single gate insulator located along the substrate and surrounding the cathode emitter tips, the single gate insulator having a gate line region thickness that is thinner than a height of the number of cathodes; a number of gate lines coupled to the gate insulator, wherein a gate line to cathode emitter tip distance between a portion of the gate line and the cathode emitter tip is substantially thinner than the gate line region thickness; a number of anodes located in columns orthogonal to and opposing the rows of cathode emitter tips, wherein the anodes include multiple phosphors, and wherein the intersection of the rows and columns form pixels; and a row decoder and a column decoder each coupled to the field emitter array in order to selectively access the pixels; and a processor adapted to receiving input signals and providing the input signals to the row and column decoders.

23. The flat panel display of claim 22, wherein the number of gate lines and the number of cathode emitter tips are formed using a self-aligned technique.

24. The flat panel display of claim 22, wherein the number of cathode emitter tips include metal silicides on polysilicon cones.

25. The flat panel display of claim 22, wherein the number of gate lines include refractory metals.