FIELD EMISSION DISPLAY APPARATUS

Abstract

A field emission display apparatus including a field emission display panel and a driving device for the field emission display panel. The driving device includes a power supply unit, the power supply unit including an abnormal current detection unit and a discharge circuit. The abnormal current detection unit generates an arc-current detection signal when the value of a current flowing between a negative anode voltage terminal of the field emission display panel and a common ground line is larger than an upper limit. The discharge circuit generates a short circuit between an anode plate of the field emission display panel and the negative anode voltage terminal when the arc-current detection signal is generated from the abnormal current detection unit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a field emission display apparatus according to an embodiment of the present invention.

FIG. 2 is an exploded perspective view of the field emission display panel illustrated in FIG. 1.

FIG. 3 is a block diagram showing potentials supplied from the power supply unit illustrated in FIG. 1 to each of the other units illustrated in FIG. 1.

FIG. 4 is a block diagram of the power supply unit illustrated in FIG. 1.

FIG. 5 is a block diagram of the rectifying unit illustrated in FIG. 4.

FIG. 6 is a circuit diagram showing the direct-current to direct-current (DC to DC) conversion units illustrated in FIG. 5.

FIG. 7 is a block diagram of the boosting unit illustrated in FIG. 4.

FIG. 8 is a circuit diagram of the abnormal current detection unit illustrated in FIG. 4.

FIG. 9 is a circuit diagram of the abnormal voltage detection unit illustrated in FIG. 4.

FIG. 10 is a circuit diagram of the OR logic circuit illustrated in FIG. 4.

FIG. 11 is a circuit diagram of the discharge circuit illustrated in FIG. 4.

FIG. 12 illustrates a connection of the circuits illustrated in FIGS. 8 and 9.

DETAILED DESCRIPTION

Referring to FIGS. 1 and 3, the field emission display apparatus according to an embodiment of the present invention includes a field emission display panel 11 and a driving device for the field emission display panel 11. The driving device includes a power supply unit 19, a scan driving unit 17, a data driving unit 18, a frame memory 12, and a control device 15.

The power supply unit 19 applies a system ground potential V_SG and an operational potential V_12H to the frame memory 12, the system ground potential V_SG and an operational potential V_15H to the control device 15, the system ground potential V_SG and an operational potential V_17H to the scan driving unit 17, an operational potential V_18H and the system ground potential V_SG to the data driving unit 18, an anode potential V_AH to an anode plate 22 (shown in FIG. 2) included in the field emission display panel 11, and a focusing potential V_FH to a focusing electrode plate 36 (shown in FIG. 2) included in the field emission display panel 11.

The scan driving unit 17 drives gate electrode lines G₁ through G_n, which are scan electrode lines of the field emission display panel 11. The data driving unit 18 drives cathode electrode lines C_R1 through C_Bm, which are data electrode lines of the field emission display panel 11. The frame memory 12 temporarily stores digital image data.

The control device 15 is formed of a monolithic integrated circuit device, for example, a field-programmable gate array (FPGA), and performs a variety of functions. The control device 15 converts input image signals S_IM into digital image data, temporarily stores the digital image data in the frame memory 12, and pulse width modulation (PWM) data and timing control signals which are used for gray scale display. The control device 15 also provides PWM data S_DD and timing control signals S_DT to the data driving unit 18 and provides timing control signals S_S to the scan driving unit 17.

Referring now to FIG. 2, the field emission display panel 11 illustrated in FIG. 1 includes a front panel 2 and a rear panel 3 which are supported by exterior space bars 401, 402, 403, 404. A plurality of additional interior space bars (not shown) are also situated on the focusing electrode plate 36.

The rear panel 3 includes a rear substrate 31, cathode electrode lines C_R1 through C_Bm, electron emitter sources E_R11 through E_Bnm, a first insulation layer 33, gate electrode lines G₁ through G_n, a second insulation layer 35, and the focusing electrode plate 36.

The cathode electrode lines C_R1 through C_Bm, to which data signals are applied, are electrically connected to the electron emitter sources E_R11 through E_Bnm. The first insulation layer 33, the gate electrode lines G₁ through G_n, the second insulation layer 35, and the focusing electrode plate 36 have through-holes H_R11 through H_Bnm respectively corresponding to the electron emitter sources E_R11 through E_Bnm. Accordingly, the gate electrode lines G₁ through G_n have the through-holes H_R11 through H_Bnm in their areas that are overlapped by the cathode electrode lines C_R1 through C_Bm. The focusing potential V_FH (shown in FIG. 4) is applied to the focusing electrode plate 36.

The front panel 2 includes a front transparent substrate 21, an anode plate 22, and fluorescent cells F_R11 through F_Bnm. The fluorescent cells F_R11 through F_Bnm respectively correspond to the through-holes H_R11 through H_Bnm, of the focusing electrode plate 36. A high positive potential V_AF (shown in FIG. 4) of 1-4 KV is applied to the anode plate 22 so that electrons from the electron emitter sources E_R11 through E_Bnm can move to fluorescent cells.

FIG. 4 is a block diagram of the power supply unit 19 illustrated in FIG. 1. Referring to FIG. 4, the power supply unit 19 includes an electromagnetic interference (EMI) filter 41, a power factor correction unit 42, a rectifying unit 43, a main control unit 44, a voltage detection unit 45, a boosting unit 46, an abnormal current detection unit 48, a discharge circuit 49, an abnormal voltage detection unit 47, and an OR logic circuit 40.

The EMI filter 41 filters out EMI noise from a power voltage V_ACIN, for example, a 220V alternating current (AC) voltage. The power factor correction unit 42 reduces power consumption by correcting the power factor of input AC power. The rectifying unit 43 rectifies an AC voltage V_AC received from the power factor correction unit 42 and simultaneously generates power voltages V_12H through V_PH required by the units included in the field emission display apparatus illustrated in FIG. 1. The boosting unit 46 boosts a first voltage V_PH from the rectifying unit 43 to generate an anode voltage V_A+.

The voltage detection unit 45 detects a voltage input to the power factor correction unit 42 and inputs a result of the detection to the main control unit 44.

The main control unit 44 generates a signal S_SH for controlling the operation of the rectifying unit 43, according to a detection voltage from the voltage detection unit 45 and an arc generation signal S_DI from the OR logic circuit 40.

The abnormal current detection unit 48 generates an arc-current detection signal S_CE when a current flowing between a negative terminal V_A− of an anode voltage V_AH of the field emission display panel 11 illustrated in FIG. 1 and a common ground line V_AL is greater than a predetermined upper limit. In this case, the arc generation signal S_DI is generated by the OR logic circuit 40, and thus the discharge circuit 49 is driven by the arc generation signal S_DI. Accordingly, the discharge circuit 49 generates a short-circuit between the anode plate 22 (shown in FIG. 2) of the field emission display panel 11 and the negative terminal V_A− of the anode voltage V_AH. Internal structures of the abnormal current detection unit 48, the OR logic circuit 40, and the discharge circuit 49 will be described in greater detail later with reference to FIGS. 8, 10, and 11.

As described above, generation or non-generation of an arc discharge is determined from the value of current flowing between the negative terminal V_A− of the anode voltage V_AH and the common ground line V_AL. Accordingly, the determination is rapidly made because the fact that an anode current flows suddenly when an arc discharge is generated in a field emission display panel was used.

Thus, when an arc discharge is generated in the field emission display panel 11 illustrated in FIG. 1, the arc-current detection signal S_CE may be rapidly generated by the abnormal current detection unit 48, and an application of the anode voltage may be rapidly blocked by the discharge circuit 49.

Referring to FIG. 8, a resistor R₁ is used to measure the value of the current flowing between the negative terminal V_A− of the anode voltage V_AH and the common ground line V_AL. Thus, an initial current caused by the arc discharge may be prevented.

Accordingly, it may be possible to include an effective protection circuit capable of coping with an arc discharge.

Furthermore, in the abnormal voltage detection unit 47, an inductor I₁ (shown in FIG. 9) is connected between the positive terminal V_A+ of the anode voltage of the field emission display panel 11 and the anode plate 22 (shown in FIG. 2) of the field emission display panel 11. The abnormal voltage detection unit 47 generates an arc-voltage detection signal S_VE when a difference between the voltages of both ends of the inductor I₁ is greater than a predetermined upper limit.

Thus, the protection circuit capable of coping with an arc discharge can be reinforced. In other words, when the potential of the anode plate 22 (shown in FIG. 2) of the field emission display panel 11 is suddenly lowered due to an arc discharge, the potential of the positive terminal V_A+ of the anode voltage is prevented from suddenly decreasing by the action of the inductor I₁. Therefore, the internal circuitry of the power supply unit 19 can be protected.

The abnormal voltage detection unit 47 will be described in greater detail with reference to FIG. 9.

When the arc-current detection signal S_CE is generated from the abnormal current detection unit 48 or the arc-voltage detection signal S_VE is generated from the abnormal voltage detection unit 47, the OR logic circuit 40 outputs the arc generation signal S_DI to operate the discharge circuit 49.

FIG. 5 is a block diagram of the rectifying unit 43 illustrated in FIG. 4. In FIG. 5, the same reference characters as those illustrated in FIG. 4 denote the same elements.

Referring to FIGS. 4 and 5, the rectifying unit 43 includes a relay 57, an alternating-current to direct-current (AC-to-DC) conversion unit 58, and first through sixth DC-to-DC conversion units 51 through 56.

The relay 57 passes or blocks the AC power V_AC under the control of the main control unit 44. The AC-to-DC conversion unit 58 converts the input AC potential into a DC potential V_DCIN.

Each of the first through sixth DC-to-DC conversion units 51, 52, 53, 54, 55, 56 converts the DC potential V_DCIN from the AC to DC conversion unit 58 so as to generate a system ground potential V_SG, a first potential V_PH, and operational potentials V_12H, V_15H, V_17H, V_18H, V_FH. As described above, the first potential V_PH is applied to the boosting unit 46.

FIG. 6 is a circuit diagram showing the internal circuitry of the DC to DC conversion units 51 through 56 illustrated in FIG. 5. In FIG. 6, the same reference characters as those illustrated in FIGS. 4 and 5 denote the same elements.

Referring to FIGS. 4 through 6, each of the DC-to-DC conversion units 51, 52, 53, 54, 55, 56 includes switching devices TR11, TR12, an AC generation capacitor C11, a transformer 61, a rectifying unit 50 which includes diodes D11, D12 and polarized capacitor C12, and a switching controller 513.

The AC generation capacitor C11 and the switching devices TR11, TR12 switch the DC potential V_DCIN of the AC to DC conversion unit 58 so as to generate an AC potential. Accordingly, the transformer 61 transforms the AC voltage generated by the switching devices TR11, TR12.

The rectifying unit 50 converts the AC voltage transformed by the transformer 61 into a DC voltage with a driving potential.

The switching controller 513 periodically turns on and off the switching devices TR11, TR12 and controls the turned-on durations of the switching devices TR11, TR12 so that the output voltage of the switching devices TR11, TR12 is inversely proportional to that of the rectifying unit 50. Therefore, the output voltage of the rectifying unit 50 can be kept constant.

FIG. 7 is a block diagram of the boosting unit 46 illustrated in FIG. 4. In FIG. 7, the same reference characters as those illustrated in FIGS. 4 and 5 denote the same elements.

Referring to FIGS. 4, 5, and 7, the boosting unit 46 includes switching devices TR71, TR72, an AC generation capacitor C71, a transformer 73, a rectifying unit 70, which includes diodes D71, D72 and polarized capacitor C72, and a switching controller 463.

The AC generation capacitor C71 and the switching devices TR71, TR72 switch the first AC voltage V_PH of the rectifying unit 43 so as to generate an AC voltage. Accordingly, the transformer 73 transforms the AC voltage generated by the switching devices TR71, TR72.

The rectifying unit 70 converts the AC voltage transformed by the transformer 73 into an anode voltage (that is, a difference between potentials of the positive and negative terminals V_A+ and V_A−) that is a DC voltage.

The switching controller 463 periodically turns on and off the switching devices TR71, TR72 and controls the turned-on durations of the switching devices TR71, TR72 so that the output voltage of the switching devices TR71, TR72 is inversely proportional to the anode voltage (that is, the difference between potentials of the positive and negative terminals V_A+ and V_A−) output from the rectifying unit 70. Therefore, the anode voltage output from the rectifying unit 70 can be kept constant.

FIG. 8 is a circuit diagram of the abnormal current detection unit 48 illustrated in FIG. 4. In FIG. 7, the same reference characters as those illustrated in FIG. 4 denote the same elements. FIG. 12 illustrates a connection of the circuits illustrated in FIGS. 8 and 9. Referring to FIGS. 4, 5, 8, and 12, the abnormal current detection unit 48 includes the first resistor R₁, an amplification unit 81, and a comparator 82.

The first resistor R₁ is connected between the negative terminal V_A− of the anode voltage of the field emission display panel 11 and the common ground line V_AL.

The amplification unit 81 includes a first operational amplifier OP₁, resistor R81 and capacitor C81 and amplifies a voltage dropped across the first resistor R₁.

The comparator 82 includes a second operational amplifier OP₂ and generates the arc-current detection signal S_CE when the output voltage of the amplification unit 81 is greater than a predetermined reference voltage V_REF.

Accordingly, the abnormal current detection unit 48 generates the arc-current detection signal S_CE when the value of the current flowing between the negative terminal V_A− of the anode voltage (i.e., a difference between potentials of the positive and negative terminals V_A+, V_A−) of the field emission display panel 11 and the common ground line V_AL is greater than the predetermined upper limit.

As described above with reference to FIG. 4, generation or non-generation of an arc discharge is determined from the value of the current flowing between the negative terminal V_A− of the anode voltage V_AH of the field emission display panel 11 and the common ground line V_AL. Accordingly, the determination is rapidly made because the fact that an anode current flows suddenly when an arc discharge is generated in a field emission display panel was used.

Thus, when an arc discharge is generated in the field emission display panel 11 illustrated in FIG. 1, the arc-current detection signal S_CE may be rapidly generated by the abnormal current detection unit 48, and an application of the anode voltage may be rapidly blocked by the discharge circuit 49.

The resistor R₁ (shown in FIG. 8) is used to measure the value of the current flowing between the negative terminal V_A− of the anode voltage V_AH and the common ground line V_AL. Thus, an initial current caused by the arc discharge may be prevented.

Accordingly, it may be possible to include an effective protection circuit capable of coping with an arc discharge.

FIG. 9 is a circuit diagram of the abnormal voltage detection unit 47 illustrated in FIG. 4. In FIG. 9, the same reference characters as those illustrated in FIG. 4 denote the same elements. Referring to FIGS. 4, 9, and 12, the abnormal voltage detection unit 47 includes the inductor I₁, a both-end voltage detection unit 91, and a comparator 92.

As described above with reference to FIG. 9, the inductor I₁ is connected between the positive terminal V_A+ of the anode voltage of the field emission display panel 11 and the anode plate 22 (shown in FIG. 2) of the field emission display panel 11.

The both-end voltage detection unit 91 detects the voltage V_A+ of the positive terminal of the anode voltage of the field emission display panel by using resistors R₃, R₄, R₅ and detects the voltage V_AH of the anode plate of the field emission display panel.

The comparator 92 generates the arc-voltage detection signal S_VE when a difference between the two voltages (i.e., V_A+−V_AH) of the voltage detection unit 91 is larger than the predetermined upper limit. When an arc discharge occurs, the difference (i.e., V_A+−V_AH) increases as the voltage V_AH of the anode plate of the field emission display panel drops.

Accordingly, the abnormal voltage detection unit 47 generates an arc-voltage detection signal S_VE when a difference between the voltages of both ends of the inductor I₁ is greater than a predetermined upper limit.

As described above with reference to FIG. 4, the protection circuit capable of coping with an arc discharge can be reinforced due to the abnormal voltage detection unit 47. In other words, when the potential of the anode plate 22 (shown in FIG. 2) of the field emission display panel 11 is suddenly lowered due to an arc discharge, the potential of the positive terminal V_A+ of the anode voltage is prevented from suddenly decreasing by the action of the inductor I₁. Therefore, the internal circuitry of the power supply unit 19 can be protected.

FIG. 10 is a circuit diagram of the OR logic circuit 40 illustrated in FIG. 4. In FIG. 10, the same reference characters as those illustrated in FIG. 4 denote the same elements. Referring to FIGS. 4, 10, and 12, the OR logic circuit 40 includes diodes D₁₀₁, D₁₀₂ for preventing the current flowing in reverse, and signal-level control resistors R₁₀₁, R₁₀₂.

Accordingly, the OR logic circuit 40 outputs the arc generation signal S_DI to operate the discharge circuit 49 when the arc-current detection signal S_CE is generated from the abnormal current detection unit 48 or the arc-voltage detection signal S_VE is generated from the abnormal voltage detection unit 47.

FIG. 11 is a circuit diagram of the discharge circuit 49 illustrated in FIG. 4. In FIG. 11, the same reference characters as those illustrated in FIG. 4 denote the same elements, and reference character V₁₂ denotes a 12 V DC supply potential. Referring to FIGS. 4, 11, and 12, the discharge circuit 49 includes a silicon control rectifier 111, first through third transformers 112, 113, 114, resistors R₁₁₁, R₁₁₂, R₁₁₃, R₁₁₄, R₁₁₅ R₁₁₆, first through third field effect transistors (FETs) F₁₁₁, F₁₁₂, F₁₁₃, and first through third capacitors C₁₁₁, C₁₁₂ C₁₁₃.

The silicon control rectifier 111 is turned on when the arc-voltage detection signal S_VE is generated from the OR logic circuit 40.

In each of the first through third transformers 112, 113, 114, as the silicon control rectifier 111 is turned on, a current flows in a first coil and a voltage is induced across a second coil.

The resistors R₁₁₁, R₁₁₂, R₁₁₃, R₁₁₄, R₁₁₅ R₁₁₆, are used to control the levels of a current and a voltage.

The first through third field effect transistors F₁₁₁, F₁₁₂, F₁₁₃ are serially connected between the anode plate (i.e., the potential of V_AH) of the field emission display panel and a system ground potential end (i.e., the potential of V_SG). At both ends of the second coil of each of the first through third transformers 112 through 114 corresponding to the first through third field effect transistors F₁₁₁, F,₁₁₂, F₁₁₃, gates and sources of the first through third field effect transistors F₁₁₁, F₁₁₂, F₁₁₃are connected to each other via the resistors R₁₁₁, R₁₁₂, R₁₁₃, R₁₁₄, R₁₁₅ R₁₁₆.

The first through third field effect transistors F₁₁₁, F₁₁₂, F₁₁₃ are turned on as a voltage is inducted across a second coil of each of the transformers 112, 113, 114, and generate a short-circuit between the anode plate (i.e., the potential of V_AH) of the field emission display panel and the system ground potential end (i.e., the potential of V_SG). The first through third capacitors C₁₁₁, C₁₁₂ C₁₁₃ induce a fast current flow.

As described above, in a field emission display apparatus according to the present invention, generation or non-generation of an arc discharge is determined from the value of a current flowing between the negative terminal of an anode voltage and a common ground line. Accordingly, the determination is rapidly made because the fact that an anode current flows suddenly when an arc discharge is generated in a field emission display panel was used.

Thus, when an arc discharge is generated in the field emission display panel, an arc-current detection signal may be rapidly generated by an abnormal current detection unit, and an application of the anode voltage by a discharge circuit may be rapidly blocked.

A resistor is used to measure the value of the current flowing between the negative terminal of the anode voltage and the common ground line. Thus, an initial current caused by the arc discharge may be prevented.

Accordingly, the field emission display apparatus according to the present invention provides an effective protection circuit capable of coping with an arc discharge.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A field emission display apparatus comprising: a field emission display panel, the field emission display panel having a common ground line of a system ground potential, fluorescent cells, electron emitter sources and an anode plate, the anode plate being responsive to an anode voltage from a positive anode voltage terminal and a negative anode voltage terminal for emitting electrons from the electron emitter sources to the fluorescent cells; anda driving device coupled to the field emission display panel for driving the field emission display panel, the driving device including a power supply unit, the power supply unit comprising: an abnormal current detection unit for generating an arc-current detection signal when current flowing between the negative anode voltage terminal and the common ground line is larger than an upper current limit; anda discharge circuit for generating a short circuit between the anode plate and the negative anode voltage terminal in response to the arc-current detection signal.

2. The field emission display apparatus of claim 1, wherein the abnormal current detection unit comprises: a current monitoring resistor between the negative anode voltage terminal and the common ground line;an amplification unit amplifying a voltage dropped across the current monitoring resistor; anda comparator generating the arc-current detection signal when an output voltage of the amplification unit is higher than a reference voltage.

3. The field emission display apparatus of claim 1, wherein the discharge circuit comprises: a silicon control rectifier turned on in response to the arc-current detection signal;at least one transformer having a first coil through which a current flows and a second coil across which a voltage is induced as the silicon control rectifier is turned on; andat least one transistor turned on as the voltage is induced across the second coil, generating a short-circuit between the anode plate and the system ground potential.

4. The field emission display apparatus of claim 3, wherein in the discharge circuit a plurality of field effect transistors are in series between the anode plate and the system ground potential, and a gate and a source of each of the field effect transistors are connected to both output ends of respective ones of a plurality of transformers.

5. The field emission display apparatus of claim 1, wherein the power supply unit further comprises: an abnormal voltage detection unit comprising a voltage monitoring inductor between the positive anode voltage terminal and the anode plate, the abnormal voltage detection unit generating an arc-voltage detection signal when a difference between voltages at both ends of the voltage monitoring inductor is larger than an upper limit; andan OR logic circuit outputting an arc generation signal for operating the discharge circuit in response to the arc-current detection signal or in response to the arc-voltage detection signal.

6. The field emission display apparatus of claim 5, wherein the abnormal voltage detection unit comprises: the voltage monitoring inductor;a voltage detection unit for detecting a voltage of the positive anode voltage terminal and a voltage of the anode plate; anda comparator generating the arc-voltage detection signal when a difference between the voltage of the positive anode voltage terminal and the voltage of the anode plate is greater than the upper limit.

7. The field emission display apparatus of claim 6, wherein in the comparator of the abnormal voltage detection unit, as the voltage of the anode plate drops, the difference between the voltage of the positive anode voltage terminal and the voltage of the anode plate increases.

8. The field emission display apparatus of claim 1, wherein the field emission display panel further comprises: data electrode lines electrically connected to the electron emitter sources; andscan electrode lines intersecting the data electrode lines.

9. The field emission display apparatus of claim 8, wherein the data electrode lines are cathode electrode lines.

10. The field emission display apparatus of claim 9, wherein the scan electrode lines are gate electrode lines having through-holes corresponding to respective electron emitter sources, the through-holes being formed in areas of the gate electrode lines overlapped by the cathode electrode lines.

11. The field emission display apparatus of claim 10, wherein the fluorescent cells face the through-holes of the gate electrode lines.