Claims
- 1. A field emission display comprising:
a n-tank that is peripherally surrounded by a p-region of semiconductor material; an emitter formed on and electrically coupled to the n-tank; an insulating region formed at a lower boundary of the n-tank, the insulating region electrically isolating the n-tank along at least a portion of the lower boundary; a dielectric layer formed on the substrate and including an opening surrounding the emitter; an extraction grid formed on the dielectric layer and including a respective opening surrounding a tip of the emitter; and a faceplate including a cathodoluminescent layer formed on a transparent conductive layer in turn formed on a transparent insulator, the faceplate disposed in a plane parallel to the surface of the substrate with the cathodoluminescent layer facing the substrate.
- 2. The display of claim 1 wherein the insulating region comprises a buried oxide region.
- 3. The display of claim 1 wherein the insulating region comprises an implanted region.
- 4. The display of claim 1 wherein the insulating region comprises an oxygen-implanted region.
- 5. The display of claim 1 wherein the insulating region comprises oxygen implanted at an energy of 300,000 electron volts or greater and to a dose of 1018 per cm2 or greater.
- 6. The display of claim 1, further comprising a FET formed in the p-region adjacent the n-tank wherein the n-tank acts as a drain for the FET.
- 7. The display of claim 1 wherein the n-tank includes a n-tank having a surface donor concentration of about two times 1016 per cm3.
- 8. The display of claim 1 wherein the p-region includes a p-region having an acceptor concentration between one and five times 1015 per cm3.
- 9. The display of claim 1, further comprising:
a source electrode formed on the surface in the p-region; an oxide layer extending from near the source to a boundary between the n-tank and the p-region; a gate formed on at least a portion of the oxide layer; and a drain comprising the n-tank, wherein the source electrode, gate electrode and drain form a FET.
- 10. A display comprising:
a substrate including a silicon surface layer, the silicon surface layer including a p-region formed on a surface thereof, the p-region surrounding a periphery of an n-tank; an emitter formed on and electrically coupled to the n-tank; an insulating region formed at a lower boundary of the n-tank, the insulating region electrically isolating the emitter and the n-tank along at least a portion of the lower boundary; and a faceplate disposed in a plane parallel to the surface of the substrate, the faceplate including a cathodoluminescent layer formed on a transparent conductive layer in turn formed on a transparent insulator, the cathodoluminescent layer disposed adjacent the substrate.
- 11. The display of claim 10 wherein the substrate comprises a silicon on insulator substrate and the insulator comprises the insulating region.
- 12. The display of claim 10 wherein the substrate comprises a p-type silicon substrate and an oxygen-implanted region comprises the insulator.
- 13. The display of claim 10, further comprising a FET formed on the p-region adjacent the n-tank, wherein the n-tank forms a drain for the FET.
- 14. The display of claim 10, further comprising:
a dielectric layer formed on the substrate and including an opening surrounding the emitter; and an extraction grid formed on the dielectric layer and including an opening surrounding a tip of the emitter such that the tip is in close proximity to the conductive layer.
- 15. A computer system comprising:
a central processing unit; a memory device coupled to the central processing unit, the memory device storing instructions and data for use by the central processing unit; an input device; and a display, the display including:
a faceplate comprising a cathodoluminescent material-coated first surface; a plurality of emitters formed on a second surface of a substrate, the first surface disposed parallel to and near the second surface, each emitter of the plurality of emitters formed on and electrically coupled to a n-tank, each n-tank formed within p-type material, each n-tank also including an insulating region formed at a lower boundary of the n-tank the insulating region electrically isolating the emitter and the n-tank along at least a portion of the lower boundary; a dielectric layer formed on the second surface, the dielectric layer having a thickness slightly less than a height of the emitters in the plurality of emitters, the dielectric layer including openings each formed about one of the plurality of emitters; and an extraction grid comprising conductive material formed on the dielectric layer, the extraction grid substantially in a plane defined by tips of the plurality of emitters and including openings each formed surrounding a tip of one of the plurality of emitters.
- 16. A method for operating a field emission display, the method comprising steps of:
biasing an extraction grid to a first potential sufficient to extract electrons from an emitter tip surrounded by an opening in the extraction grid; biasing a substrate to a second potential less than the first potential to form a depletion region between the substrate and a n-tank disposed in the substrate beneath the emitter; and displacing the depletion region from an area that can be illuminated by photons traveling through the opening.
- 17. The method of claim 16, further comprising a step of applying an accelerating potential to a cathodoluminescent-coated anode disposed near the substrate, the accelerating potential for accelerating a portion of the electrons emitted from the emitter to the anode to strike the cathodoluminescent coating to provide light.
- 18. The method of claim 16, further comprising a step of applying a control signal to a gate of a field effect transistor, wherein the n-tank forms a drain of the field effect transistor, the control signal controlling the number of electrons emitted from the emitter per unit time.
- 19. The method of claim 16, including steps of:
applying control signals to a plurality of gates of field effect transistors to spatially modulate the number of electrons emitted from emitters; and applying an accelerating potential to a cathodoluminescent-coated anode disposed near the substrate, the accelerating potential for accelerating a portion of the electrons emitted from the emitters to the anode to strike the cathodoluminescent coating to provide light and form a visible image.
- 20. The method of claim 16 wherein the displacing step includes a step of displacing the depletion region by an insulating region.
- 21. The method of claim 20 wherein the displacing step includes a step of displacing the depletion region by an insulating region that extends beyond an area that may be illuminated by photons traveling through the opening or a portion of the extraction grid that is exposed to incident photons.
- 22. A method for fabricating a field emission display baseplate, the method comprising:
forming an n-tank within a p-region of semiconductor material, the n-tank being peripherally surrounded by the p-region; forming an insulator beneath the n-tank, the insulator electrically isolating at least a portion of a lower boundary of the n-tank from the p-region; forming an emitter on the n-tank above the insulator; and forming a layer of other structures in which an opening is formed to expose the emitter, the opening being formed over the insulator.
- 23. The method of claim 22, further comprising:
forming a source electrode in the p-region; forming a gate oxide extending from a first area near the source electrode to an area near a junction between the n-tank and the p-region; forming a gate electrode extending across at least a portion of the gate oxide; and forming a drain comprising the n-tank, wherein the drain, source electrode and gate electrode form a FET.
- 24. The method of claim 22, further comprising:
forming a dielectric layer on the emitter and the substrate; forming a conductive layer on the dielectric layer; and forming openings in the conductive and dielectric layers, each of the openings surrounding the emitters such that a tip of the emitter is in close proximity to the conductive layer.
- 25. The method of claim 24, further comprising:
forming a faceplate having a cathodoluminescent material-coated second surface; and placing the faceplate adjacent the substrate such that the surface is near the tip of the emitter.
- 26. The method of claim 22 wherein the step of forming an insulator includes implanting oxygen into a layer at a lower edge of the n-tank.
- 27. The method of claim 22 wherein the step of forming a p-region includes forming a p-region that is doped to have an acceptor concentration between one to five times 1015 per cm3.
- 28. The method of claim 22 wherein the step of forming a n-tank includes forming a n-tank that has a surface donor concentration of about two times 1016 per cm3.
- 29. The method of claim 22 wherein:
the step of forming a p-region includes forming a p-region that is doped to have an acceptor concentration between one to five times 1015 per cm3; and the step of forming a n-tank includes forming a n-tank that has a surface donor concentration of about two times 1016 per cm3.
GOVERNMENT RIGHTS
[0001] This invention was made with government support under Contract No. DABT63-93-C-0025 awarded by Advanced Research Projects Agency (ARPA). The government has certain rights in this invention.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09126695 |
Jul 1998 |
US |
Child |
09907845 |
Jul 2001 |
US |