Claims
- 1. A field emission display comprising:a p-type semiconductor substrate; a n-tank formed at a surface of the p-type semiconductor substrate; a depletion portion formed adjacent to a peripheral boundary of the n-tank; an emitter formed oil and electrically coupled to the n-tank; an insulating region formed adjacent to a lower boundary of the n-tank opposite from the emitter, the insulating region electrically isolating the n-tank from the p-type semiconductor substrate along at least a portion of the lower boundary; a dielectric layer formed on the substrate and including an opening surrounding the emitter, the depletion portion being substantially outwardly displaced by the insulating region from an area that is illuminable by photons passing through the opening; an extraction grid formed on the dielectric layer and including a respective opening surrounding a tip of the emitter; and a faceplate including a cathodoluminescent layer formed on a transparent conductive layer in turn formed on a transparent insulator, the faceplate disposed in a plane parallel to the surface of the substrate with the cathodoluminescent layer facing the substrate.
- 2. The display of claim 1 wherein the insulating region comprises a buried oxide region.
- 3. The display of claim 1 wherein the insulating region comprises an implanted region.
- 4. The display of claim 1 wherein the insulating region comprises an oxygen-implanted region.
- 5. The display of claim 1 wherein the insulating region comprises oxygen implanted at an energy of 300,000 electron volts or greater and to a dose of 1018 per cm2 or greater.
- 6. The display of claim 1, further comprising a FET adjacent the n-tank wherein the n-tank acts as a drain for the FET.
- 7. The display of claim 1 wherein the n-tank includes a n-tank having a surface donor concentration of about two times 1016 per cm3.
- 8. The display of claim 1 wherein the p-type semiconductor substrate includes a p-region having an acceptor concentration between one and five times 1015 per cm3.
- 9. The display of claim 1, further comprising:a source electrode formed on the surface of the p-type substrate; an oxide layer extending from near the source to a boundary between the n-tank and the p-type substrate; a gate formed on at least a portion of the oxide layer; and a drain comprising the n-tank, wherein the source electrode, gate electrode and drain form a FET.
- 10. A display comprising:a substrate including a silicon surface layer, the silicon surface layer including a p-region formed on a surface thereof, and a depletion region formed within the p-region, the depletion region being adjacent to and surrounding a periphery of an n-tank; an emitter formed on and electrically coupled to the n-tank; an insulating region formed at a lower boundary of the n-tank opposite from the emitter, the insulating region electrically isolating the n-tank from the substrate along at least a portion of the lower boundary, the depletion region being substantially outwardly displaced by the insulating region from an area that is illuminable by photons; and a faceplate disposed in a plane parallel to the surface of the substrate, the faceplate including a cathodoluminescent layer formed on a transparent conductive layer in turn formed on a transparent insulator, the cathodoluminescent layer disposed adjacent the substrate.
- 11. The display of claim 10 wherein the substrate comprises a silicon on insulator substrate and the insulator comprises the insulating region.
- 12. The display of claim 10 wherein the substrate comprises a p-type silicon substrate and an oxygen-implanted region comprises the insulator.
- 13. The display of claim 10, further comprising a FET formed on the p-region adjacent the n-tank, wherein the n-tank forms a drain for the FET.
- 14. The display of claim 10, further comprising:a dielectric layer formed on the substrate and including an opening surrounding the emitter; and an extraction grid formed on the dielectric layer and including an opening surrounding a tip of the emitter such that the tip is in close proximity to the conductive layer.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of pending U.S. Pat. application Ser. No. 09/126,695, filed Jul. 30, 1998.
GOVERNMENT RIGHTS
This invention was made with government support under Contract No. DABT63-93-C-0025 awarded by Advanced Research Projects Agency (ARPA). The government has certain rights in this invention.
US Referenced Citations (6)
Non-Patent Literature Citations (1)
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