Claims
- 1. A field emission display baseplate, comprising:a substrate; a plurality of emitters formed on the substrate; a dielectric layer formed on the substrate, the dielectric layer having an opening formed about each of the emitters; and an extraction grid formed on the dielectric layer and including a first non-germanium layer adjacent the dielectric layer and a second light-blocking layer formed on the first layer, the second light-blocking layer comprising germanium and having an optical transmissivity of less than one percent, the extraction grid formed substantially in a plane defined by the tips of the emitters and having an opening surrounding each tip of a respective one of the emitters.
- 2. The baseplate of claim 1 wherein:the first layer comprises a polysilicon layer having a thickness of between 0.05 microns and 0.15 microns; and the second light-blocking layer includes a germanium-containing layer having a thickness of about 0.15 microns.
- 3. The baseplate of claim 1 wherein the first and second layers together include a layer having a sheet resistance between 500 and 5,000 ohms per square.
- 4. The baseplate of claim 1 wherein the extraction grid further includes a third layer formed on the second layer.
- 5. The baseplate of claim 4 wherein the first and third layers include polysilicon.
- 6. The baseplate of claim 1 wherein the extraction grid provides a sheet resistance of about 1,000 ohms per square.
- 7. The baseplate of claim 1 wherein:the substrate includes silicon; and the plurality of emitters include n+ silicon, each of the plurality of emitters being formed on a n-tank including n-doped silicon, each of the n-tanks in turn formed in p-doped silicon, each of the plurality of emitters comprising a drain of a FET.
- 8. The baseplate of claim 1 wherein the second lightblocking layer comprises polycrystalline germanium.
- 9. The baseplate of claim 1 wherein the second lightblocking layer comprises amorphous germanium.
- 10. A field emission display baseplate, comprising:a substrate; a plurality of emitters formed on the substrate; a dielectric layer formed on the substrate, the dielectric layer having an opening formed about each of the emitters; and an extraction grid formed on the dielectric layer and including a first non-germanium layer adjacent the dielectric layer and a second light-blocking layer formed on the first layer, the second light-blocking layer comprising germanium, the extraction grid having an opening surrounding each tip of a respective one of the emitters.
- 11. The baseplate of claim 10 wherein the first layer of the extraction grid comprises a polysilicon layer.
- 12. The baseplate of claim 11 wherein:the first layer comprises a polysilicon layer having a thickness of between 0.05 microns and 0.15 microns; and the second light-blocking layer includes a germanium-containing layer having a thickness of about 0.15 microns.
- 13. The baseplate of claim 10 wherein the first and second layers together includes a layer having a sheet resistance between 500 and 5,000 ohms per square.
- 14. The baseplate of claim 10 wherein the extraction grid further includes a third layer formed on the second layer.
- 15. The baseplate of claim 14 wherein the first and third layers include polysilicon.
- 16. The baseplate of claim 10 wherein the extraction grid provides a sheet resistance of about 1,000 ohms per square.
- 17. The baseplate of claim 10 wherein:the substrate includes silicon; and the plurality of emitters include n+ silicon, each of the plurality of emitters being formed on a n-tank including n-doped silicon, each of the n-tanks in turn formed in p-doped silicon, each of the plurality of emitters comprising a drain of a FET.
- 18. The baseplate of claim 10 wherein the second light-blocking layer comprises polycrystalline germanium.
- 19. The baseplate of claim 10 wherein the second light-blocking layer comprises amorphous germanium.
- 20. A field emission display comprising:a substrate including p-doped silicon; a plurality of silicon emitters formed on the substrate, each of the emitters being formed on a respective n-tank of n-doped silicon formed in the substrate; a dielectric layer formed on the substrate, the dielectric layer having an opening formed about each of the emitters; an extraction grid formed on the dielectric layer and including a first non-germanium layer adjacent the dielectric layer and a second light-blocking layer formed on the first layer, the second light-blocking layer comprising germanium and having an optical attenuation factor of at least two orders of magnitude, the extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters, the extraction grid providing a sheet resistance of about 1,000 ohms per square; and a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters.
- 21. The display of claim 20 wherein the first layer comprises a polysilicon layer having a thickness of between 0.05 microns and 0.15 microns; andthe second light-blocking layer includes a germanium-containing layer having a thickness of about 0.15 microns.
- 22. The display of claim 20 wherein the second light-blocking layer comprises amorphous germanium.
- 23. The display of claim 20 wherein the second light-blocking layer comprises polycrystalline germanium.
- 24. An active display comprising:a semiconductor substrate; a plurality of emitters formed on the substrate, each emitter of the plurality comprising a drain of a FET; a dielectric layer formed on the substrate and having an opening surrounding each one of the plurality of emitters; an extraction grid formed on the dielectric layer and including a first non-germanium layer adjacent the dielectric layer and a second light-blocking layer formed on the first layer, the second light-blocking layer comprising germanium, the extraction grid having an opening surrounding each tip of a respective one of the emitters; and a faceplate disposed in a plane parallel to a plane of tips of the emitters, the faceplate including a cathodoluminescent layer formed on a transparent conductive layer in turn formed on a transparent insulator.
- 25. The display of claim 24 wherein the first layer of the extraction grid comprises a polysilicon layer.
- 26. The display of claim 24 wherein the first layer and the second light-blocking layer together provide a layer having a sheet resistance of about 1,000 ohms per square.
- 27. The display of claim 24 wherein the extraction grid comprises:a first polysilicon layer formed on the dielectric layer; a germanium layer formed on the first polysilicon layer; and a second polysilicon layer formed on the germanium layer.
- 28. The display of claim 27 wherein the first and second polysilicon layers and the germanium layer collectively form a layer having a sheet resistance of about 1,000 ohms per square.
- 29. The display of claim 24 wherein the second light-blocking layer has a thickness of 0.15 microns.
- 30. The display of claim 24 wherein the second light-blocking layer comprises amorphous germanium.
- 31. The display of claim 24 wherein the second light-blocking layer comprises polycrystalline germanium.
- 32. A computer system comprising:a central processing unit; a memory device coupled to the central processing unit, the memory device storing instructions and data for use by the central processing unit; an input interface; and a display, the display comprising: a cathodoluminescent layer formed on a conductive surface of a transparent faceplate; a group of emitters formed on a planar surface of a substrate, the substrate disposed parallel to and near the cathodoluminescent layer formed on the faceplate; a dielectric layer formed on the substrate, the dielectric layer having an opening formed about each of the emitters; and an extraction grid formed on the dielectric layer and including a first non-germanium layer adjacent the dielectric layer and a second light-blocking layer comprising germanium and formed on the first layer, the extraction grid substantially in a plane defined by tips of the emitters and having an opening formed surrounding a tip of a respective one of the emitters.
- 33. The computer system of claim 32 wherein each emitter of the group of emitters comprises a drain of a FET.
- 34. The computer system of claim 32 wherein the first layer comprises a polysilicon layer and the second layer comprisesa germanium layer.
- 35. The computer system of claim 32 wherein the extraction grid comprises a layer having a sheet resistance of about 1,000 ohms per square.
- 36. The computer system of claim 32 wherein the extraction grid comprises:a first polysilicon layer formed on the dielectric layer; a germanium layer formed on the first polysilicon layer; and a second polysilicon layer formed on the germanium layer.
- 37. The computer system of claim 36 wherein the first and second polysilicon layers and the germanium layer collectively form a layer having a sheet resistance of about 1,000 ohms per square.
- 38. The display of claim 32 wherein the second light-blocking layer of the extraction grid includes a polycrystalline germanium layer.
- 39. The display of claim 32 wherein the second light-blocking layer of the extraction grid includes an amorphous germanium layer.
GOVERNMENT RIGHTS
This invention was made with government support under Contract No. DABT63-93-C-0025 awarded by Advanced Research Projects Agency (ARPA). The government has certain rights in this invention.
US Referenced Citations (6)
Non-Patent Literature Citations (1)
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