Field-Programmable Gate Array (FPGA) Routing Congestion Prediction Method and System

Information

  • Patent Application
  • 20240193342
  • Publication Number
    20240193342
  • Date Filed
    August 13, 2021
    3 years ago
  • Date Published
    June 13, 2024
    5 months ago
  • CPC
    • G06F30/398
    • G06F30/394
  • International Classifications
    • G06F30/398
    • G06F30/394
Abstract
The disclosure relates to a Field-Programmable Gate Array (FPGA) routing congestion prediction method and system. The method includes: first, an FPGA routing congestion prediction problem is modeled as an image conversion problem; feature information parameters are extracted according to the image conversion problem; and a cycle-consistency generative adversarial network model is defined to solve the image conversion problem, and a result of routing congestion prediction is obtained. Through the FPGA routing congestion prediction method and system designed by the disclosure, the result of routing congestion can be accurately predicted according to a series of intermediate and result files in a placement stage, thus reducing the time needed for routing iteration, further improving the working efficiency of an FPGA Electronic Design Automation (EDA) tool, and providing strong support for a healthy and sustainable development of the FPGA.
Description

The disclosure claims priority to Chinese Patent Application No. 202110691125.3 filed to the China National Intellectual Property Administration on Jun. 22, 2021 and entitled “Field-Programmable Gate Array (FPGA) Routing Congestion Prediction Method and System”, the disclosure of which is hereby incorporated by reference in its entirety.


TECHNICAL FIELD

The disclosure relates to an FPGA routing congestion prediction method and system, belonging to the field of integrated circuit design automation.


BACKGROUND

As a semi-custom circuit, FPGA has been widely applied to high-performance computing, Internet of Things, aerospace, artificial intelligence and other fields due to its short development cycle, flexible design, low development cost, etc. However, with the continuous development of science and technology, the device complexity and system capacity of the FPGA have been greatly improved, and new requirements are also made for the design process of an FPGA Electronic Design Automation (EDA) tool.


Through the EDA design tool, a to-be-implemented circuit or system function can be compiled into a binary code bitstream file. By using the binary code bitstream file, the state of an internal device of the FPGA can be configured, so that a required function can be implemented on an FPGA chip. However, with the continuous improvement of the circuit scale and the integration of the FPGA chip, time required for the EDA tool to compile an FPGA circuit is getting longer and longer, which seriously restricts the rapid development of the FPGA.


Routing is one of the most time-consuming steps in the FPGA EDA tool flow. How to accurately predict routing congestion and reduce the time needed for routing iteration is particularly important.


SUMMARY

The disclosure aims to overcome the shortcomings of a conventional art, and provide an FPGA routing congestion prediction method and system. A result of routing congestion is accurately predicted in a placement stage, the difficulty in accurately predicting the result of FPGA routing congestion is solved, the time required for routing iteration is reduced, and the result quality and execution efficiency of an FPGA automatic placement and routing tool are improved.


In order to solve the above problem, at least some embodiments of the disclosure disclose the FPGA routing congestion prediction method and system.


The FPGA routing congestion prediction method includes the following steps.


Step S1, modeling FPGA routing congestion prediction: modeling an FPGA routing congestion prediction problem as an image conversion problem.


Step S2, extracting feature information parameters to obtain an image file after placement imgp.


Step S3, obtaining an image file after routing img, based on a routing result and converting the image file after routing imgr into an image file capable of representing a result of FPGA routing congestion.


Step S4, defining a cycle-consistency generative adversarial network model to solve the image conversion problem, and a result of FPGA routing congestion prediction is obtained.


In some embodiments, the step S1, modeling the FPGA routing congestion prediction problem into the image conversion problem includes:

    • obtaining an image file after FPGA placement imgp based on a result file of FPGA placement;
    • obtaining an image file after FPGA routing img, based on a result file after FPGA routing;
    • wherein the image file after FPGA placement imgp and the image file after FPGA routing img, are multi-channel images.


Wherein, there is a one-to-one mapping relationship between the image file after FPGA placement imgp and the heat map imgrhm representing the result of FPGA routing congestion, and the solution of the heat map imgrhm is transformed into a process of generating the heat map imgrhm representing the result of FPGA routing congestion by using the known image file after FPGA placement imgp, that is, completing the modeling of the FPGA routing congestion prediction problem.


In some embodiments, the step S2, extracting the feature information parameters to obtain the image file after placement imgp includes:

    • the feature information parameters include a connection relationship between netlists, pin density after placement and a macro module.


Generating feature images corresponding to each feature information parameter based on the feature information parameters, wherein the feature images comprise an image of the connection relationship between the netlists, an image of the pin density after placement and a macro module image;

    • wherein generating the image file after placement imgp based on the feature images includes:
    • stacking the image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image to obtain the image file after placement imgp.


In some embodiments, the step S3 obtaining the image file after routing based on the routing result and converting the image file after routing img, into the heat map file imgrhm capable of representing the result of FPGA routing congestion includes:

    • acquiring a result file after routing;
    • converting the result file after routing into the image file after routing img,;
    • transforming the image file after routing img, into the heat map file imgrhm to represent the result of FPGA routing congestion.


In some embodiments, the step S4, defining the cycle-consistency generative adversarial network to solve the image conversion problem and obtaining the result of FPGA routing congestion prediction includes;

    • step S401, a loss function of the cycle-consistency generative adversarial network is defined as:












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    • wherein custom-charactergan(Gimgp, Disimgrhm, Ximgp, Yimgrhm) represents a forward loss function of the cycle-consistency generative adversarial network, the forward loss function is expressed as:

















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    • wherein Disimgrhm represents a forward discriminate function of the cycle-consistency generative adversarial network, Gimg, represents a forward generation function of the cycle-consistency generative adversarial network, ximg, ∈Ximg, represents a set of samples of the image file imgp after placement, Pdata(Ximgp) represents a distribution function of a sample Ximgp, E represents mathematical expectation, yimgrhm ∈Yimgrhm represents a set of samples of the heat map file imgrhm, and Pdata(Yimgrhm) represents the distribution function of a sample Yimgrhm.






custom-character
gan(Fimgrhm, Disimgp, Yimgrhm, Ximgp) represents a reverse loss function of the cycle-consistency r generative adversarial network, the reverse loss function is expressed as:














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    • wherein Fimgrhm represents a reverse generation function of the cycle-consistency generative adversarial network, and Disimgp represents a reverse discriminate function of the cycle-consistency generative adversarial network.






custom-character
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    • wherein custom-characterdis(Gimgp, Fimgrhm) represents a standard loss function of the cycle-consistency generative adversarial network, the standard loss function is expressed as:

















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In the formula (1), λ and γ represent weight indicator factors, and both λ and γ are positive numbers.


Step S402, based on the definition, an objective function of the cycle-consistency generative adversarial network is represented as:












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Step S403, for the forward generation function Gimgp and the reverse generation function Fimgrhm, a first neural network model is constructed for training. The first neural network model specifically includes m1 convolution modules, an intensive residual network composed of n1 residual modules and m1 deconvolution modules, and both m1 and n1 are positive integers.


Step S404, for the reverse discriminate functions Disimgp and the forward discriminate function Disimgrhm, a second neural network model is constructed for training. The second neural network model includes m2 convolution modules, and m2 is a positive integer.


Step S405, multiple image files after placement imgp and multiple heat map files imgrhm capable of representing the result of FPGA routing congestion are enabled to form an overall sample set.

    • a). the overall sample set is divided into two parts of a training sample set and a verification sample set.
    • b). the first neural network model and the second neural network model are trained based on the training sample set, and in response to an objective function curve converges, completing the training to obtain an initial training model.
    • c). calibrating the initial training model by using the verification sample set to obtain a final training model.


Step S406, inputting the image file after placement img, into the obtained final training model to obtain the result of routing congestion prediction.


In some embodiments, the disclosure also provides an FPGA routing congestion prediction system, which includes: an FPGA core design module, an information preprocessing module and a cycle-consistency generative adversarial network module.


The FPGA core design module is configured to model an FPGA routing congestion prediction problem as an image conversion problem and complete modeling of FPGA routing congestion prediction.


The information preprocessing module is configured to extract required feature information parameters to obtain an image file after placement imgp and an image file after routing imgr.


The cycle-consistency generative adversarial network module is configured to define a cycle-consistency generative adversarial network model to solve the image conversion problem, and obtain a result of FPGA routing congestion prediction.


In some embodiments, the system also includes a memory module, a display module and an information transfer module. The memory module is configured to store an intermediate file and a result file of routing congestion prediction, the display module is configured to display the result of routing congestion prediction, and the information transfer module is configured to transfer information among the memory module, the display module and information transfer module.


In some embodiments, the modeling the FPGA routing congestion prediction problem into the image conversion problem includes:

    • obtaining an image file after FPGA placement imgp based on a result file of FPGA placement;
    • obtaining an image file after FPGA routing imgr based on a result file after FPGA routing;


      wherein the image file after FPGA placement imgp and the image file after FPGA routing imgr are multi-channel images;
    • transforming the image file after FPGA routing img, into a heat map imgrhm, and representing the result of FPGA routing congestion by the heat map imgrhm.


There is a one-to-one mapping relationship between the image file after FPGA placement imgp and the heat map imgrhm representing the result of FPGA routing congestion, and the solution of the heat map imgrhm of the result of FPGA routing congestion is transformed into a process of generating the heat map imgrhm of the result of FPGA routing congestion by using the known image file after FPGA placement imgp, that is, completing the modeling of the FPGA routing congestion prediction problem.


In some embodiments, extracting the feature information parameters to obtain the image file after placement imgp includes:


The feature information parameters include a connection relationship between netlists, pin density after placement and a macro module.

    • generating feature images corresponding to each feature information parameter based on the feature information parameters, wherein the feature images comprise an image of the connection relationship between the netlists, an image of the pin density after placement and a macro module image.


The operation of generating the image file after placement imgp based on the feature images includes:

    • stacking the image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image to obtain the image file imgp after placement.


Wherein obtaining the image file after routing imgr based on the routing result and converting the image file after routing imgr into the image file imgrhm capable of representing the result of


FPGA routing congestion includes:

    • acquiring a result file after routing;
    • converting the result file after routing into the image file after routing imgr;
    • transforming the image file after routing imgr into the heat map file imgrhm to represent the result of FPGA routing congestion.


In some embodiments, defining the cycle-consistency generative adversarial network model to solve the image conversion problem and obtaining the result of FPGA routing congestion prediction includes:

    • step S401, a loss function of the cycle-consistency generative adversarial network is defined as:












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    • wherein custom-charactergan(Gimgp, Disimgrhm, Ximgp, Yimgrhm) represents a forward loss function of the cycle-consistency generative adversarial network, the forward loss function is expressed as:















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    • wherein Disimgrhm represents a forward discriminate function of the cycle-consistency generative adversarial network, Gimgp represents a forward generation function of the cycle-consistency generative adversarial network, ximgp ∈Ximgp represents a set of samples of the image file imgp after placement, Pdata(Ximgp) represents a distribution function of a sample Ximgp. E represents mathematical expectation, yimgrhm ∈Yimgrhm represents a set of samples of the heat map file imgrhm, and Pdata(Yimgrhm) represents a distribution function of a sample Yimgrhm.


    • custom-character
      gan(Fimgrhm, Disimgp, Yimgrhm, Ximgp) represents a reverse loss function of the cycle-consistency generative adversarial network, the reverse loss function is expressed as:















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    • wherein Fimgrhm represents a reverse generation function of the cycle-consistency generative adversarial network, and Disimgp represents a reverse discriminate function of the cycle-consistency generative adversarial network.






custom-character
cyc(Gimgp, Fimgrhm) represents consistency loss of the cycle-consistency generative adversarial network, the consistency loss is expressed as:













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    • wherein custom-characterdis(Gimgp, Fimgrhm) represents a standard loss function of the cycle-consistency generative adversarial network, the standard loss function is expressed as:
















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In the formula (1), λ and γ represent weight indicator factors, and both λ and γ are positive numbers.


Step S402, based on the definition, an objective function of the cycle-consistency generative adversarial network is represented as:










min


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img
p


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rhm





min


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Step S403, for the forward generation functions Gimgp and the reverse generation function Fimgrhm, a first neural network model is constructed for training. The first neural network model specifically includes m1 convolution modules, an intensive residual network composed of n1 residual modules and m1 deconvolution modules, and both m1 and n1 are positive integers.


Step S404, for the reverse discriminate functions Disimgp and the forward discriminate function Disimgrhm, a second neural network model is constructed for training. The second neural network model includes m2 convolution modules, and m2 is a positive integer.


Step S405, multiple image files after placement imgp and multiple heat map files imgrhm capable of representing the result of FPGA routing congestion are enabled to form an overall sample set.

    • dividing the overall sample set into two parts of a training sample set and a verification sample set
    • training the first neural network model and the second neural network model based on the training sample set, and in response to an objective function curve converges, completing the training to obtain an initial training model.
    • calibrating the initial training model by using the verification sample set to obtain a final training model.


Step S406, inputting the image file after placement imgp to the obtained final training model to obtain the result of routing congestion prediction.


Compared with the conventional art, the disclosure has the beneficial effects as follows.

    • (1) In the disclosure, the FPGA routing congestion prediction method and system are designed, so that the result of routing congestion can be accurately predicted based on the intermediate and result files produced in a placement stage, thus maintaining a great significance in reducing the time needed for routing iteration and further improving the working efficiency of an FPGA EDA tool, and strong support can be provided for a healthy and sustainable development of FPGA.
    • (2) Different from a common image conversion problem, the disclosure focuses on the change of the overall style of the image during FPGA placement and routing, can accurately reflect the change of characteristics before and after image conversion by extracting an effective feature information parameter, and can quickly solve the above problem without supervision by defining the cycle-consistency generative adversarial network model.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a schematic flowchart of an FPGA routing congestion prediction method according to the disclosure.



FIG. 2 is a schematic diagram of a manner of generating an image file after placement according to the disclosure.



FIG. 3 is a schematic structural diagram of a cycle-consistency generative adversarial network according to the disclosure.



FIG. 4 is a schematic structural diagram of an FPGA routing congestion system according to the disclosure.





DETAILED DESCRIPTION OF THE EMBODIMENTS

The methods in the embodiments of the disclosure will be clearly and completely described below in combination with the drawings in the embodiments of the disclosure. It is apparent that the described embodiments are not all embodiments but part of embodiments of the disclosure. All other embodiments obtained by those of ordinary skill in the art on the basis of the embodiments in the disclosure without creative work shall fall within the scope of protection of the disclosure.


The embodiment of the disclosure provides an FPGA routing congestion prediction method, and the flow is shown in FIG. 1. The FPGA routing congestion prediction method includes:


At step S1, modeling an FPGA routing congestion prediction problem as an image conversion problem.


At step S2, extracting feature information parameters to obtain an image file after placement imgp.


At step S3, obtaining an image file after routing imgr based on a routing result and converting the image file after routing imgr into an image file capable of representing a result of FPGA routing congestion.


At step S4, defining a cycle-consistency generative adversarial network model to solve the image conversion problem, and a result of FPGA routing congestion prediction is obtained.


In step S1, based on result files after FPGA placement and routing, the image file after placement imgp and an image file after routing imgr can be respectively obtained by the embodiment.


Both the image file after placement imgp and the image file after routing imgr are the multi-channel images.


The image file after routing imgr is transformed into a heat map imgrhm, and the result of FPGA routing congestion is represented by the heat map imgrhm.


There is a one-to-one mapping relationship between the image file after FPGA placement imgp and the heat map imgrhm representing the result of FPGA routing congestion, and the solution of the heat map imgrhm of the result of FPGA routing congestion is transformed into a process of generating the heat map imgrhm of the result of FPGA routing congestion by using the known image file after FPGA placement imgp.


Further, in order to generate the required image file after placement imgp, it is necessary to extract the required feature information parameters. That is, in step S2, the feature information parameters are extracted to obtain the image file after placement imgp. In an embodiment, a complete placement and routing process is completed by using an automatic placement and routing tool, intermediate result information of each stage is saved, and the extraction of the feature information parameter is completed according to the saved intermediate result information.


In an embodiment, the feature information parameters include a connection relationship between netlists, pin density after placement and a macro module.


When an FPGA automatic routing tool executes a routing operation, the tool may automatically avoid a congestion area according to the congestion situation of a net under the guidance of the connection relationship between the netlists, so as to avoid the problem of scarce routing resources. Therefore, the embodiment takes the connection relationship between the netlists as the feature information parameter. In addition, after an FPGA automatic placement tool executes a placement operation, the pin density in each area of an FPGA chip can be calculated. In the area with high pin density in the chip, the net may be relatively dense, and the required routing resources may increase proportionally, which makes it more prone to routing congestion. Therefore, in the embodiment, the pin density after placement is used as the feature information parameters. After the FPGA automatic routing tool executes the routing operation, according to a conclusion of analysis after routing, it is to be concluded that a boundary area of the macro module and an adjacent area between two macro modules are prone to routing congestion. According to the above conclusion, the embodiment also takes the macro module as the feature information parameter.


According to the feature information parameters, feature images corresponding to each of the feature information parameters are generated. The feature images include an image of the connection relationship between the netlists, an image of the pin density after placement and a macro module image.


The generating the image file after placement imgp based on the image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image includes:


The image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image are stacked to obtain the image file after placement imgp, which is shown in FIG. 2.


After the image file after placement is generated imgp, it is also necessary to obtain the heat map file imgrhm capable of representing the result of FPGA routing congestion, that is, step S3, obtaining the image file after routing imgr based on the routing result and converting the image file after routing imgr into the heat map file imgrhm capable of representing the result of FPGA routing congestion.


In an embodiment, a result file after routing is acquired.


The result file after routing is converted into the image file after routing imgr.


The image file after routing imgr is transformed into the heat map file imgrhm to represent the result of FPGA routing congestion.


It is to be noted that, in order to solve the image conversion problem, it is necessary to construct the cycle-consistency generative adversarial network model to complete the solution of the image conversion problem, and the schematic diagram is shown in FIG. 3. The characteristic of the cycle-consistency generative adversarial network is that positive and negative generative adversarial networks are included to perform a cycle, so as to modify an output result of the model, which can prevent the feature of an image in a domain Ximgp from being mapped to the same image in a domain Yimgrhm. From the above description, it is to be concluded that two discriminate functions and two generation functions are respectively included in the cycle-consistency generative adversarial network.


In an embodiment, the step S4 is performed according to the following steps.


At step S401, a loss function of the cycle-consistency generative adversarial network is defined as:












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g

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img
p


,

Dis

img
rhm


,

X

img
p


,

Y

img
rhm



)

+



gan

(


F

img
rhm


,

Dis

img
p


,

Y

img
rhm


,

X

img
p



)

+

λ





c

y

c


(


G

img
p


,


F

img
rhm



)


+


γℒ
dis

(


G

img
p


,

F

img
rhm



)






(
1
)









    • wherein custom-charactergan(Gimgp, Disimgrhm, Ximgp, Yimgrhm) represents a forward loss function of the cycle-consistency generative adversarial network, the forward loss function is expressed as:















gan

(


G

img
p


,

Dis

img
rhm


,

X

img
p


,

Y

img
rhm



)

=



1
2




E


y

img
rhm


~


P
data

(

Y

img
rhm


)



[


(



Dis

img
rhm


(

y

img
rhm


)

-
1

)

2

]


+


1
2




E


x

img
p


~


P
data

(

X

img
p


)



[


(


Dis

img
rhm


(


G

img
p


(

x

img
p


)

)

)

2

]







(
2
)









    • wherein Disimgrhm represents a forward discriminate function of the cycle-consistency generative adversarial network, Gimgp represents a forward generation function of the cycle-consistency generative adversarial network, ximgp ∈Ximgp represents a set of samples of the image file imgp after placement, Pdata(Ximgp) represents a distribution function of a sample Ximgp, E represents mathematical expectation, yimgrhm ∈Yimgrhm represents a set of samples of the heat map file imgrhm, and Pdata(Yimgrhm) represents the distribution function of a sample Yimgrhm.





Wherein custom-charactergan(Fimgrhm, Disimgp, Yimgrhm, Ximgp) represents a reverse loss function of the cycle-consistency generative adversarial network, the forward loss function is expressed as:












gan

(


F

img
rhm


,

Dis

img
p


,

Y

img
rhm


,

X

img
p



)

=



1
2




E


x

img
p


~


P
data

(

X

img
p


)



[


(



Dis

img
p


(

x

img
p


)

-
1

)

2

]


+


1
2




E


y

img
rhm


~


P
data

(

Y

img
rhm


)



[


(


Dis

img
p


(


F

img
rhm


(

y

img
rhm


)

)

)

2

]







(
3
)









    • wherein Fimgrhm represents a reverse generation function of the cycle-consistency generative adversarial network, and Disimgp represents a reverse discriminate function of the cycle-consistency generative adversarial network.






custom-character
cyc(Gimgp, Fimgrhm) represents consistency loss of the cycle-consistency generative adversarial network, the consistency loss is expressed as:













c

y

c


(


G

img
p


,

F

img
rhm



)

=



E


y

img
rhm





P
data

(

Y

img
rhm


)










G

img
p


(


F

img
rhm


(

y

img
rhm


)

)

-

y

img
rhm





1


+


E


x

img
p





p
data

(

X

img
p


)










F

img

r

h

m



(


G

img
p


(

x

i

m


g
p



)

)

-

x

img
p





1







(
4
)









    • where custom-characterdis(Gimgp, Fimgrhm) represents a standard loss function of the cycle-consistency generative adversarial network, the standard loss function is expressed as:
















c

y

c


(


G

img
p


,

F

img
rhm



)

=



E


x


img
rhm

,

y

img
rhm







P
data

(


X

img
p


,

Y

img
rhm



)










F

img
rhm


(

y

img
rhm


)

-

x

img
p





1


+



E


x

img
p


,


y

img
rhm





p
data

(


X

img
p


,

y

img
rhm



)












G

img
p


(

x

i

m


g
p



)

-

y

img
rhm





1

.







(
5
)







In the formula (1), λ and γ represent weight indicator factors, and both λ and γ are positive numbers.


At step S402, according to the definition, an objective function of the cycle-consistency generative adversarial network is represented as:










min


G

img
p


,

F

img
rhm





min


X

img
p


,

Y

img
rhm








(


G

img
p


,

F

img
rhm


,

Dis

img
rhm


,

Dis

img
p



)

.





(
6
)







At step S403, for the forward generation functions Gimgp and the reverse generation function Fimgrhm, a first neural network model is constructed for training. The first neural network model has a dumbbell-shaped symmetrical structure, which is as follows.


The first neural network model includes m1 convolution modules, an intensive residual network composed of n1 residual modules and m1 deconvolution modules, and both m1 and n1 are positive integers.


In an embodiment, a concrete form of the first neural network model is that five convolution modules, an intensive residual network composed of nine residual modules and five deconvolution modules are provided, that is, m1=5, and m1=9.


At step S404, for the reverse discriminate functions Disimgp and the forward discriminate function Disimgrhm, a second neural network model is constructed for training. The second neural network model includes m2 convolution modules, and m2 is a positive integer.


In an embodiment, the concrete form of the second neural network model is a convolutional neural network provided with five convolution modules, that is, m2=5.


At step S405, multiple image files after placement imgp and multiple heat map files imgrhm capable of representing the result of FPGA routing congestion are enabled to form an overall sample set.


Further, the overall sample set is divided into two parts of a training sample set and a verification sample set.


In an embodiment, the training sample set includes b1 image files after placement imgp and c1 heat map files imgrhm capable of representing the result of FPGA routing congestion.


The verification sample set includes b2 image files after placement imgp and c2 heat map files imgrhm capable of representing the result of FPGA routing congestion.


It is to be noted that parameters b1, b2, c1 and c2 need to meet the following conditions:











b
1

+

b
2


=
N




(
7
)














c
1

+

c
2


=
M




(
8
)









    • wherein N represents the number of image files after placement imgp in the overall sample set, and M represents the number of heat map files imgrhm in the overall sample set.





The first neural network model and the second neural network model are trained according to the training sample set, and the training is completed when an objective function curve converges to obtain an initial training model.


Further, the initial training model is calibrated by using the verification sample set to obtain a final training model.


At step S406, the image file after placement imgp is input to the obtained final training model to obtain the result of routing congestion prediction.


The disclosure further provides an FPGA routing congestion prediction system shown in FIG. 4, which includes: an FPGA core design module, an information preprocessing module and a cycle-consistency generative adversarial network module.


The FPGA core design module is configured to model an FPGA routing congestion prediction problem as an image conversion problem and complete modeling of FPGA routing congestion prediction.


It is to be noted that a placement and routing tool is executed in the FPGA core design module.


The information preprocessing module is configured to extract required feature information parameters to obtain an image file after placement imgp and an image file after routing imgr.


It is to be noted that S2 and S3 are executed in the information preprocessing module.


The cycle-consistency generative adversarial network module is configured to define a cycle-consistency generative adversarial network model to solve the image conversion problem, and obtain a result of FPGA routing congestion prediction.


It is to be noted that S4 is executed in the cycle-consistency generative adversarial network module.


In an embodiment of the disclosure, a memory module shall also be included, which is configured to store a series of intermediate and result files and a result file of routing congestion prediction.


In an embodiment of the disclosure, a display module shall also be included, which is configured to display the result of routing congestion prediction.


In an embodiment of the disclosure, an information transfer module shall also be included, which is configured to transfer information among the modules.


In an embodiment, the operation modeling the FPGA routing congestion prediction problem into the image conversion problem in the FPGA core design module is as follows.


According to result files after FPGA placement and routing, an image file after FPGA placement imgp and an image file after FPGA routing imgr are respectively obtained; and the image file after FPGA placement imgp and the image file after FPGA routing imgr are the multi-channel images.


The image file after FPGA routing imgr is transformed into a heat map imgrhm, and the result of FPGA routing congestion is represented by the heat map imgrhm.


There is a one-to-one mapping relationship between the image file after FPGA placement imgp and the heat map imgrhm representing the result of FPGA routing congestion, and the solution of the heat map imgrhm of the result of FPGA routing congestion is transformed into a process of generating the heat map imgrhm of the result of FPGA routing congestion by using the known image file after FPGA placement imgp, that is, completing the modeling of the FPGA routing congestion prediction problem.


In an embodiment extracting the feature information parameters to obtain the image file after placement imgp in the information preprocessing module includes the following operations.


The feature information parameters include a connection relationship between netlists, pin density after placement and a macro module.


According to the feature information parameters, feature images corresponding to each of the feature information parameters are generated. The feature images include an image of the connection relationship between the netlists, an image of the pin density after placement and a macro module image.


The operation of generating the image file after placement imgp based on the feature images includes the following operations.


The image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image are stacked to obtain the image file after placement imgp.


The operation of obtaining the image file after routing imgr based on a routing result and converting the image file after routing imgr into an image file capable of representing the result of FPGA routing congestion includes the following operations.


A result file after routing is acquired.


The result file after routing is converted into the image file after routing imgr.


The image file after routing imgr is transformed into the heat map file imgrhm to represent the result of FPGA routing congestion.


In an embodiment, the cycle-consistency generative adversarial network module is configured to define the cycle-consistency generative adversarial network model to solve the image conversion problem, and obtain the result of FPGA routing congestion prediction, which includes the following operations.


At step S401, a loss function of the cycle-consistency generative adversarial network is defined as:












(


G

img
p


,

F

img
rhm


,

Dis

img
rhm


,

Dis

img
p



)

=





g

a

n


(


G

img
p


,

Dis

img
rhm


,

X

img
p


,

Y

img
rhm



)

+



gan

(


F

img
rhm


,

Dis

img
p


,

Y

img
rhm


,

X

img
p



)

+

λ





c

y

c


(


G

img
p


,


F

img
rhm



)


+


γℒ
dis

(


G

img
p


,

F

img
rhm



)






(
1
)









    • where custom-charactergan(Gimgp, Disimgrhm, Ximgp, Yimgrhm) represents a forward loss function of the cycle-consistency generative adversarial network, the forward loss function is expressed as:















gan

(


G

img
p


,

Dis

img
rhm


,

X

img
p


,

Y

img
rhm



)

=



1
2




E


y

img
rhm


~


P
data

(

Y

img
rhm


)



[


(



Dis

img
rhm


(

y

img
rhm


)

-
1

)

2

]


+


1
2




E


x

img
p


~


P
data

(

X

img
p


)



[


(


Dis

img
rhm


(


G

img
p


(

x

img
p


)

)

)

2

]







(
2
)









    • wherein Disimgrhm represents a forward discriminate function of the cycle-consistency generative adversarial network, Gimgp represents a forward generation function of the cycle-consistency generative adversarial network, ximgp ∈Ximgp represents a set of samples of the image file imgp after placement, Pdata(Ximgp) represents a distribution function of a sample Ximgp, E represents mathematical expectation, yimgrhm ∈Yimgrhm representing a set of samples of the heat map file imgrhm, and Pdata(Yimgrhm) represents a distribution function of a sample Yimgrhm. custom-charactergan(Fimgrhm, Disimgp, Yimgrhm, Ximgp) represents a reverse loss function of the cycle-consistency generative adversarial network, the reverse loss function is expressed as:















gan

(


F

img
rhm


,

Dis

img
p


,

Y

img
rhm


,

X

img
p



)

=



1
2




E


x

img
p


~


P
data

(

X

img
p


)



[


(



Dis

img
p


(

x

img
p


)

-
1

)

2

]


+


1
2




E


y

img
rhm


~


P
data

(

Y

img
rhm


)



[


(


Dis

img
p


(


F

img
rhm


(

y

img
rhm


)

)

)

2

]







(
3
)









    • wherein Fimgrhm represents a reverse generation function of the cycle-consistency generative adversarial network, and Disimgp represents a reverse discriminate function of the cycle-consistency generative adversarial network.






custom-character
cyc(Gimgp, Fimgrhm) represents consistency loss of the cycle-consistency generative) adversarial network, the consistency loss is expressed as:)













c

y

c


(


G

img
p


,

F

img
rhm



)

=



E


y

img
rhm





P
data

(

Y

img
rhm


)










G

img
p


(


F

img
rhm


(

y

img
rhm


)

)

-

y

img
rhm





1


+


E


x

img
p





p
data

(

X

img
p


)










F

img

r

h

m



(


G

img
p


(

x

i

m


g
p



)

)

-

x

img
p





1







(
4
)









    • wherein custom-characterdis(Gimgp, Fimgrhm) represents a standard loss function of the cycle-consistency generative adversarial network, the standard loss function is expressed as:
















c

y

c


(


G

img
p


,

F

img
rhm



)

=



E


x


img
rhm

,

y

img
rhm







P
data

(


X

img
p


,

Y

img
rhm



)










F

img
rhm


(

y

img
rhm


)

-

x

img
p





1


+



E


x

img
p


,


y

img
rhm





p
data

(


X

img
p


,

y

img
rhm



)












G

img
p


(

x

i

m


g
p



)

-

y

img
rhm





1

.







(
5
)







In the formula (1), λ and γ represent weight indicator factors, and both λ and γ are positive numbers.


At step S402, representing, based on the definition, an objective function of the cycle-consistency generative adversarial network as:










min


G

img
p


,

F

img
rhm





min


X

img
p


,

Y

img
rhm








(


G

img
p


,

F

img
rhm


,

Dis

img
rhm


,

Dis

img
p



)

.





(
6
)







At step S403, for the forward generation functions Gimgp and the reverse generation function Fimgrhm, a first neural network model is constructed for training. The first neural network model has a dumbbell-shaped symmetrical structure.


In an embodiment, the first neural network model includes m1 convolution modules, an intensive residual network composed of n1 residual modules and m1 deconvolution modules, and both m1 and n1 are positive integers.


At step S404, for the reverse discriminate functions Disimgp and the forward discriminate function Disimgrhm, a second neural network model is constructed for training. The second neural network model includes m2 convolution modules, and m2 is a positive integer.


At step S405, multiple image files after placement imgp and multiple heat map files imgrhm capable of representing the result of FPGA routing congestion are enabled to form an overall sample set.


Further, the overall sample set is divided into two parts of a training sample set and a verification sample set.


Further, the first neural network model and the second neural network model are trained according to the training sample set, and the training is completed when an objective function curve converges to obtain an initial training model.


Further, the initial training model is calibrated by using the verification sample set to obtain a final training model.


At step S406, the image file after placement imgp is input to the obtained final training model to obtain the result of routing congestion prediction.


Through the above embodiment, the disclosure can accurately predict congestion information in a routing stage according to a series of parameters obtained in a placement stage, adaptively adjust the operation strategy of the FPGA placement and routing method according to the obtained routing congestion information, guide the optimization of the FPGA placement and routing process, and improve the operation efficiency of the FPGA placement and routing tool by more than 10%.


The embodiments in the specification are described in a related manner. The same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method embodiment.


The above are only the preferred embodiments of the disclosure and are not intended to limit the scope of protection of the disclosure. Any modifications, equivalent replacements, improvements and the like made within the spirit and principle of the disclosure shall fall within the scope of protection of the disclosure.

Claims
  • 1. A Field-Programmable Gate Array (FPGA) routing congestion prediction method, comprising: step S1: modeling FPGA routing congestion prediction: modeling an FPGA routing congestion prediction problem as an image conversion problem;step S2: extracting feature information parameters to obtain an image file after placement imgp;step S3: obtaining an image file after routing imgr based on a routing result, and converting the image file after routing imgr into a heat map file imgrhm capable of representing a result of FPGA routing congestion;step S4: defining a cycle-consistency generative adversarial network model to solve the image conversion problem, and obtaining a result of FPGA routing congestion prediction.
  • 2. The FPGA routing congestion prediction method as claimed in claim 1, wherein the step S1, modeling the FPGA routing congestion prediction problem into the image conversion problem comprises: obtaining an image file after FPGA placement imgp based on a result file of FPGA placement;obtaining an image file after FPGA routing imgr based on a result file after FPGA routing;wherein the image file after FPGA placement imgp and the image file after FPGA routing imgr are multi-channel images:transforming the image file after FPGA routing imgr into a heat map imgrhm, and representing a result of FPGA routing congestion by the heat map imgrhm;wherein there is a one-to-one mapping relationship between the image file after FPGA placement imgp and the heat map imgrhm representing the result of FPGA routing congestion, the solution of the heat map imgrhm being transformed into a process of generating the heat map imgrhm representing the result of FPGA routing congestion by using the known image file after FPGA placement imgp, that is, completing the modeling of the FPGA routing congestion prediction problem.
  • 3. The FPGA routing congestion prediction method as claimed in claim 1, wherein the step S2, extracting the feature information parameters to obtain the image file after placement imgp comprises: the feature information parameters comprise a connection relationship between netlists, pin density after placement and a macro module; andgenerating feature images corresponding to each feature information parameter based on the feature information parameters, wherein the feature images comprise an image of the connection relationship between the netlists, an image of the pin density after placement and a macro module image;wherein generating the image file after placement imgp based on the feature images comprises:stacking the image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image to obtain the image file after placement imgp.
  • 4. The FPGA routing congestion prediction method as claimed in claim 1, wherein the step S3, obtaining the image file after routing imgr based on the routing result, and converting the image file after routing imgr into the heat map file imgrhm capable of representing the result of FPGA routing congestion comprises: acquiring a result file after routing;converting the result file after routing into an image file after routing imgr;transforming the image file after routing imgr into the heat map file imgrhm to represent the result of FPGA routing congestion.
  • 5. The FPGA routing congestion prediction method as claimed in claim 1, wherein the step S4, defining the cycle-consistency generative adversarial network model to solve the image conversion problem, and obtaining the result of FPGA routing congestion prediction comprises: step S401: defining a loss function of the cycle-consistency generative adversarial network as:
  • 6. A Field-Programmable Gate Array (FPGA) routing congestion prediction system, comprising: an FPGA core design module, configured to model an FPGA routing congestion prediction problem as an image conversion problem and complete modeling of FPGA routing congestion prediction;an information preprocessing module, configured to extract required feature information parameters to obtain an image file after placement imgp and an image file after routing imgr;a cycle-consistency generative adversarial network module, configured to define a cycle-consistency generative adversarial network model to solve the image conversion problem, and obtain a result of FPGA routing congestion prediction.
  • 7. The FPGA routing congestion prediction system as claimed in claim 6. further comprising a memory module, a display module and an information transfer module, the memory module is configured to store an intermediate file and a result file of routing congestion prediction, the display module is configured to display the result of routing congestion prediction, and the information transfer module is configured to transfer information among the memory module, the display module and information transfer module.
  • 8. The FPGA routing congestion prediction system as claimed in claim 6, wherein transforming the FPGA routing congestion prediction problem into the image conversion problem comprises: obtaining an image file after FPGA placement imgp based on a result file of FPGA placement;obtaining an image file after FPGA routing imgr based on a result file after FPGA routing;wherein the image file after FPGA placement imgp and the image file after FPGA routing imgr are multi-channel images;transforming the image file after FPGA routing imgr into a heat map imgrhm, and representing a result of FPGA routing congestion by the heat map imgrhm;wherein there is a one-to-one mapping relationship between the image file after FPGA placement imgp and the heat map imgrhm representing the result of FPGA routing congestion, the solution of the heat map imgrhm of the result of FPGA routing congestion being transformed into a process of generating the heat map imgrhm of the result of FPGA routing congestion by using the known image file after FPGA placement imgp, that is, completing the modeling of the FPGA routing congestion prediction problem.
  • 9. The FPGA routing congestion prediction system as claimed in claim 6, wherein extracting the feature information parameters to obtain the image file after placement imgp comprises: the feature information parameters comprise a connection relationship between netlists, pin density after placement and a macro module; andgenerating feature images corresponding to each feature information parameter based on the feature information parameters, wherein the feature images comprise an image of the connection relationship between the netlists, an image of the pin density after placement and a macro module image;wherein generating the image file after placement imgp based on the feature images comprises:stacking the image of the connection relationship between the netlists, the image of the pin density after placement and the macro module image to obtain the image file after placement imgp;wherein obtaining the image file after routing imgr based on the routing result, and converting the image file after routing imgr into the heat map file imgrhm capable of representing the result of FPGA routing congestion comprises:acquiring a result file after routing;converting the result file after routing into the image file imgr after routing; andtransforming the image file after routing imgr into a heat map file imgrhm to represent the result of FPGA routing congestion.
  • 10. The FPGA routing congestion prediction system as claimed in claim 6, wherein defining the cycle-consistency generative adversarial network model to solve the image conversion problem and obtaining the result of FPGA routing congestion prediction comprises:step S401: defining a loss function of the cycle-consistency generative adversarial network as:
  • 11. The FPGA routing congestion prediction method as claimed in claim 1, wherein the step S2, extracting the feature information parameters to obtain the image file after placement imgp comprises: completing a placement and routing process by using an automatic placement and routing tool;saving intermediate result information;extracting the feature information parameters based on the intermediate result information.
  • 12. The FPGA routing congestion prediction method as claimed in claim 1, wherein the cycle-consistency generative adversarial network model comprises a positive generative adversarial network and a negative generative adversarial network.
  • 13. The FPGA routing congestion prediction method as claimed in claim 5, wherein the first neural network model comprises a dumbbell-shaped symmetrical structure.
Priority Claims (1)
Number Date Country Kind
202110691125.3 Jun 2021 CN national
PCT Information
Filing Document Filing Date Country Kind
PCT/CN2021/112384 8/13/2021 WO