An aspect of the invention relates to a method of film cadence detection for detecting a particular pull-down pattern that may be present in a video signal. Other aspects of the invention relate to a film cadence detector, a video system, and a computer program product for a programmable processor.
A video signal typically has a format that provides for 50 or 60 images per second. An image may be a field or a frame depending on whether the format provides for interlaced scanning or progressive scanning, respectively. In contrast, a motion picture, which is another word for a movie, typically has a format that provides for 24 or 25 images per second. Moreover, the images are typically recorded on a film by means of a photographic process.
A process known as telecine is generally used to transform a motion picture into a video signal. The telecine process involves an image rate conversion. In many cases, an image of an original motion picture is repeated one or more times in order to achieve a higher image rate. A video signal that has been obtained by applying a telecine process to a motion picture therefore comprises original images and repeat images. Such a video signal will be referred to as telecine video signal hereinafter.
An image repetition in a telecine video signal follows a given pattern, which is in conformity with the image rate conversion that is required. For example, let it be assumed that the motion picture has a rate of 24 images per second. Let it further be assumed that the video signal has a rate of 60 images per second. In that case, a 24-to-60 image rate conversion is required. This can be achieved by repeating odd-numbered images in the motion picture twice and by repeating even-numbered images once, or vice versa. There is a 3:2 pattern, which provides an image rate increase by a factor of 2.5. Such a repeat pattern is often referred to as pull-down pattern or film cadence.
A video signal that comprises a slow-motion sequence may also exhibit a pull-down pattern. For example, a broadcast of a sports event typically comprises one or more slow-motion sequences. So-called slow motion controllers typically generate a slow-motion sequence by repeating originally captured images one or more times. A pull-down pattern in a slow-motion sequence may be relatively exotic. For example, a pull-down pattern of 2:3:2:2:2:3:2:1:3 was found in a video signal from a sports channel. It should further be noted that there are video effects other than slow-motion, which may introduce a particular pull-down pattern.
There are various types of video signal processing in which it is advantageous to distinguish between original images and repeat images. A suboptimal result would be obtained if such a type of video signal processing was to process a telecine video signal in a fashion that is based on an assumption that each image is unique, which is not the case in the telecine video signal. Examples of types of video signal processing, which should preferably distinguish between original images and repeat images, include: image rate conversion, which is often called frame rate conversion, de-interlacing and pull-down optimization.
A film cadence detector can provide a pattern indication that allows a video signal processor to distinguish between original images and repeat images. A film cadence detector detects that a given video input signal, or a portion thereof, results from a telecine process. That is, a film cadence detector detects that the video input signal is a telecine video signal. In addition, the film cadence detector typically detects a particular pull-down pattern, which is also called film cadence, in the telecine video signal. The pull-down pattern indicates whether a particular image in the telecine video signal is an original image or a repeat image.
A film cadence detector typically comprises a state machine whose states are associated with a number of fixed pull-down patterns. Transitions between states are determined by detected differences between successive images. The greater the number of different pull-down patterns that the state machine can handle, the more complex the state machine is. Moreover, such a film cadence detector is not very flexible in the sense that the film cadence detector can only detect a limited repertoire of pull-down patterns. The film cadence detector fails to give a proper indication in case an input video signal comprises a pull-down pattern that is not included in this limited repertoire.
The international patent application published under number WO 01/013647 discloses an apparatus for detecting telecine mode in a sequence of video fields. A first video field and a second video field are compared to determine if one of the first and second fields is a repeat field. A telecine mode is declared if a sequence of repeat fields corresponds to a telecine pattern. The apparatus comprises various state machines whose respective state diagrams are illustrated in
It is an object of the invention to provide a film cadence detector that can handle a relatively great variety of pull-down patterns at moderate cost. The independent claims define various aspects of the invention. The dependent claims define additional features for implementing the invention to advantage.
In accordance with the invention, a film cadence in a video signal is detected in the following manner. Successive classification indications are generated for successive images within the video signal. A classification indication belongs to a particular image and indicates whether that particular image has been classified as an original image or a repeat image. A condition is checked for at least X successive classification indications, X representing a natural number in a given range. The condition is that each one of the at least X successive classification indications is equal to the X-th previous classification indication. If the condition is true, a pattern indication is provided, which corresponds with the natural number that X represents. If the condition is false, the condition is checked anew with X representing another natural number in the given range.
Film cadence detection in accordance with the invention can be implemented with relatively simple hardware or software, or combination of both. There is no need for any complicated state machine. Moreover, the film cadence detection is universal in the sense that a relatively great variety of pull-down patterns can be detected.
An implementation of the invention advantageously comprises one or more of following additional features, which are described in separate paragraphs that correspond with individual dependent claims.
The aforementioned condition is preferably first checked with X representing the highest natural number in the range and whereby, if the condition is false, the condition is checked anew with X representing a next highest natural number.
Film cadence detection in accordance with the invention preferably involves a counter register comprising respective counter values. A counter value is associated with a particular natural number that X may represent. The following steps are executed when a new classification indication is generated. For each natural number that X may represent, it is checked whether the new classification indication is equal to the X-th previous classification indication. If so, the counter value that is associated with the natural number that X represents, is incremented. If not, the counter value is reset. It is further checked whether a counter value is at least equal to the natural number with which the counter value is associated. If so, a pattern indication is provided that corresponds with this natural number.
A difference metric for an image is preferably calculated in the following manner. A local difference is determined for various pixels in the image. Each of these pixels has a particular value and a particular position within the image. The local difference for a pixel is determined as follows. A set of neighboring pixels in a neighboring image is defined. The neighboring pixels have respective positions within the neighboring image, which are similar to the position of the pixel in the image of interest. A minimum pixel value and a maximum pixel value within the set of neighboring pixels are determined. The local difference has a first given value or a second given value depending on whether the value of the pixel is within a range that depends on the minimum pixel value and the maximum pixel value or outside this range, respectively. A sum of the respective local differences for the respective pixels is calculated. The sum represents the difference metric for the image. It is decided on the basis of the difference metric, whether the current image classifies as an original image or a repeat image.
A current image is preferably classified as an original image or a repeat image on the basis of at least a difference metric for the current image and the aforementioned pattern indication.
Such a classification is preferably done in the following manner. An expected classification indication is determined for the current image on the basis of the pattern indication. A most probable sequence of classification indications is determined on the basis of several difference metrics. It is verified whether the most probable sequence of classification indications is in conformity with the expected classification indication, or not. The classification indication for the current image is made equal to the expected classification indication if the verification step is positive. Conversely, the classification indication is made unequal to the expected classification indication if the verification step is negative.
The additional features identified in the preceding paragraphs contribute to reliability and cost-efficiency.
A detailed description with reference to drawings illustrates the invention summarized hereinbefore, as well as the additional features.
The video display driver VDD basically operates as follows. The video display driver VDD receives a video input signal VA from the video source VSC. The video display driver VDD may receive other video input signals VB, VC from other video sources. A user may select one of the video input signals VA, VB, VC by means of his or her remote control device RCD. It is assumed that the user has selected the video input signal VA from the video source VSC. Consequently, the frame rate converter FRC receives this video input signal VA. It will be assumed hereinafter, by way of example, that the video input signal VA has a frame rate of 60 frames per second.
The video input signal VA may comprise film material: a sequence of frames that originate from a motion picture, which is another word for a movie. Motion pictures are generally provided in a format of 24 frames per second. The video input signal VA has a different format of 60 frames per second. A process known as “telecine” has been used to convert the motion picture from the format of 24 frames per second to the format of 60 frames per second. This 24-to-60 frame rate conversion typically involves a so-called 3:2 pull-down pattern: odd-numbered frames are repeated twice and even-numbered frames are repeated once, or vice versa. Telecine may involve other pull-down patterns depending on the frame rate conversion of interest. Some examples of other telecine pull-down patterns are: 2:2, 2:3:3:2, and 2:2:2:4.
The video signal VA may equally comprise a slow-motion sequence, which exhibits a particular a pull-down pattern. For example, a broadcast of a sports event typically comprises one or more slow-motion sequences, which may have been generated by repeating originally captured images one or more times. A slow-motion pull-down pattern may be relatively exotic, such as, for example: 2:3:2:2:2:3:2:1:3. There are video effects other than slow-motion, which may introduce a particular pull-down pattern. Some examples of other pull-down patterns are: 3:2:3:2:2, 5:5, 6:4, and 8:7.
Let it be assumed that the video input signal VA comprises film material. This means that the video input signal VA has a particular pull-down pattern, which results from a telecine operation. The film cadence detector FCD detects the pull-down pattern. The film cadence detector FCD provides a pattern indication PI, which is a description of the pull-down pattern that has been detected. The film cadence detector FCD will be described in greater detail hereinafter.
The frame rate converter FRC subjects the video input signal VA to a frame rate conversion. For example, the frame rate converter FRC may double the frame rate in order to enhance perceived image quality. Since it was assumed that the frame rate of the video input signal VA is 60 frames per second, the frame rate converter FRC will then provide a video display signal VD with a frame rate of 120 frames per second. The video display signal VD corresponds with the video input signal VA in terms of content, but has a different frame rate.
The output circuit OUT illustrated in
The frame rate converter FRC carries out the frame rate conversion on the basis of the pattern indication PI, which the film cadence detector FCD provides. The pattern indication PI tells the frame rate converter FRC, as it were, which frames in the video input signal VA are repeat frames and which frames are original frames, with a relatively high degree of reliability. The frame rate converter FRC can use this information to advantage for optimizing the frame rate conversion in terms of perceived image quality. For example, let it be assumed that the frame rate conversion involves making interpolations between successive images. An interpolation between an original frame and a repeat of that original frame should preferably be avoided. The pattern indication PI can avoid such an interpolation so as to ensure each interpolation concerns two original frames or their respective copies.
The video input signal VA has a 3:2 pull-down pattern. In the upper layer, a parallelogram with no filling represents original frames. A parallelogram with a grayish filling represents a repeat frame. The pattern indication PI comprises a sequence of bits, which are represented as circles. There is a specific bit for each frame in the video input signal VA. In case the frame classifies as an original frame, the bit is equal to 1. Conversely, in case the frame classifies as a repeat frame, the bit is equal to 0.
The pattern indication PI allows the frame rate converter FRC to reconstruct the original motion picture VO. To that end, the frame rate converter FRC ignores the repeat frames and retains the original frames only. In
The frame rate converter FRC generates a set of intermediate frames between two successive original frames. In the lower layer, parallelograms with a cross-hatched filling represent intermediate frames. The intermediate frames, which are included in the video display signal VD, provide a relatively high frame rate. The frame rate converter FRC may generate the intermediate frames by means of interpolations between two successive original frames. Different interpolations may be used for different intermediate frames within a set. For example, an interpolation that is used for generating a particular intermediate frame, which has a particular temporal position between two successive original frames, may depend on this particular temporal position. The interpolation may involve, for example, motion compensation. Alternatively, the interpolation may be a linear blending between the two successive original frames, wherein the one and the other original frame have respective weights that depend on the particular temporal position of the intermediate frame of interest.
The film cadence detector FCD basically operates as follows. The difference metric calculator DMC calculates a difference metric DM for each frame in the video input signal VA. The difference metric DM is a value that indicates an amount of difference between the frame of interest and a previous frame. Accordingly, the difference metric DM expresses a degree of likelihood that the frame of interest is an original frame or, conversely, a degree of likelihood that the frame of interest is a repeat frame.
The classification bit generator CBG receives successive difference metrics that belong to successive frames in the video input signal VA. The classification bit generator CBG classifies each frame in the video input signal VA as an original frame or a repeat frame on the basis of the difference metric DM for that frame and, if needed, further difference metrics. Moreover, the classification bit generator CBG utilizes the pattern indication PI in carrying out this classification. The pattern indication PI provides a basis that allows the classification bit generator CBG to predict whether a current frame should classify as an original frame or a repeat frame. This utilization of the pattern indication PI effectively constitutes a feedback in a classification process, in which previous classifications play a role in making new classifications. It should further be noted that the classification bit generator CBG may issue a request RQ to the difference metric calculator DMC for calculating further difference metrics.
The classification bit generator CBG provides a classification bit Bc for each frame in the video input signal VA in a corresponding order. The classification bit Bc has a value that is equal to 1 if the frame of interest classifies as an original frame. Conversely, the value of the classification bit Bc is equal to 0 if the frame of interest classifies as a repeat frame. Accordingly, the classification bit generator CBG provides successive classification bits BCN, BCN−1, BCN−2, . . . , BCN−L, . . . that belong to successive frames in the video input signal VA. The successive classification bits BCN, BCN−1, BCN−2, . . . , BCN−L, . . . illustrated in
The input value register RGI receives the successive classification bits BCN, BCN−1, BCN−2, . . . , BCN−L, . . . that the classification bit generator CBG has provided. The input value register RGI operates on a first-in first-out basis. Accordingly, the input value register RGI stores the L most recent classification bits that the classification bit generator CBG has provided. The most recent classification bit BcN is present in cell Ci0 and therefore constitutes input value I0. The one-but-most recent classification bit BCN−1 is present in cell Ci1 and therefore constitutes input value II, and so on.
The respective classification bits that are stored in the input value register RGI shift one cell position when the classification bit generator CBG produces a new classification bit Bc. Initially, the input value register RGI will be empty. A first classification bit is stored into cell Ci0 and constitutes input value I0. This first classification bit moves to cell Ci1 and constitutes input value I1, when a second classification bit arrives. This process continues so that each cell comprises a classification bit once the classification bit generator CBG has produced more than L classification bits. A steady state situation is achieved.
The cadence pattern detector CPD updates respective counter values C0, C1, C2, . . . , CM in the counter value register RGC each time a new classification bit Bc has been stored in the input value register RGI. That is, the counter value register RGC is updated on a frame by frame basis. Each counter value is associated with a possible periodicity that may be present within the classification bits that have been stored in the input value register RGI. Counter value C1 is associated with a period of 1 frame. Counter value C2 is associated with a period of 2 frames, and so on. Counter value CM is associated with a period of M frames, which is a maximum period that can be detected. Initially, each counter value is set to 0.
The cadence pattern detector CPD updates the counter value register RGC on the basis of the input values that are stored in the input value register RGI. In doing so, the cadence pattern detector CPD may detect a periodicity within the input values that are stored in the input value register RGI. The cadence pattern detector CPD provides a detected period Pd when there is such a periodicity. The detected period Pd is a natural number greater than 0 and smaller than M, which is the maximum period that can be detected.
The cadence pattern detector CPD writes the detected period Pd into cell Cp0 of the detected period register RGP, which operates on a first-in first-out basis. Accordingly, each previously detected period Pd, if any, that is present in this register moves one cell position. The detected period register RGP thus comprises a history of detected periods. The cadence pattern detector CPD establishes the pattern indication PI on the basis of the detected periods that are stored in the detected period register RGP and the input values that are stored in the input value register RGI.
In step SCPD1, the new classification bit BCN is written into the input value register RGI (BcN→RGI). Accordingly, the new classification bit BcN constitutes input value I0, which is stored in cell Ci0 of the input value register RGI (I0=BcN). As explained hereinbefore, assuming that a classification bit was previously stored in cell, this classification bit moves to cell Ci1. Similarly, any further classification bits that were already present in the input value register RGI each move each one cell position. At the end of step SCPD1, a given number of input values will be present in the input value register RGI. In the steady state situation, L+1 input values are present in the input value register RGI. There may be a smaller number of input values during an initial phase.
In step SCPD2, the cadence pattern detector CPD checks whether the following condition is true or not: the number of input values that are present in the input value register RGI is smaller than M or equal thereto (#I≦M?). In case the aforementioned condition is true, the maximum period M cannot be detected yet because there is insufficient number of input values. This will typically be the case during the initial phase. In case the aforementioned condition is not true, there are sufficient input values to detect the maximum period M. This will typically be the case in the steady state condition. The cadence pattern detector CPD carries out step SCPD3 or step SCPD4 depending on whether the aforementioned condition is true or not, respectively.
In step SCPD3, or step SCPD4, the cadence pattern detector CPD assigns an initial value to a cell index parameter x. The cell index parameter x is a natural number that designates a particular cell Cix in the input value register RGI, as well as the input value Ix that is stored in that particular cell. In addition, the cell index parameter x designates a particular cell Ccx in the counter value register RGC, as well as the counter value Cx that is stored in that particular cell. For example, let it be assumed that the cell index parameter x has a value that is equal to 2. In that case, the cell index parameter x designates the input value I2 and the counter value C2, which are present in cell Ci2 and cell Cc2, respectively. The cell index parameter x can also be regarded as a pointer that points to a particular cell and the value comprised in that cell.
In step SCPD3, the cadence pattern detector CPD sets the initial value of the cell index parameter x so that this value is equal to the number of input values #I that are present in the input value register RGI minus one (x=#I−1). Accordingly, the cell index parameter x initially points to the oldest input value that is present in the input value register RGI. In the initial phase, this oldest input value is the first classification bit that the classification bit generator CBG has provided following a startup.
In step SCPD4, the cadence pattern detector CPD sets the initial value of the cell index parameter x so that this value is equal to the maximum period M that can be detected (x=M). Accordingly, the cell index parameter x initially points to the input value IM.
In step SCPD5, the cadence pattern detector CPD sets the detected period Pd to 0 (Pd=0). The detected period Pd being equal to 0, signifies that no period has been detected yet. Any other value signifies that a period has been detected.
In step SCPD6, the cadence pattern detector CPD verifies whether the following condition is true or not: the cell index parameter x is greater than 0 (x>0 ?). In case the aforementioned condition is true, the cadence pattern detector CPD carries out steps SCPD7 and subsequent steps, which will be discussed in greater detail hereinafter. In case the aforementioned condition is not true, the cadence pattern detector CPD stops carrying out the steps illustrated in
In step SCPD7, the cadence pattern detector CPD verifies whether the following condition is true or not: the input value Ix to which the cell index parameter x points is equal to the input value I0, which is the most recent classification bit BCN (Ix=I0?). In case the aforementioned condition is true, the input values, which are present in the input value register RGI, may potentially have a periodicity that is equal to the cell index parameter x, which is a natural number. In that case, the cadence pattern detector CPD carries out steps SCPD9 and SCPD10, which will be discussed in greater detail hereinafter. In case the aforementioned condition is not true, the input values, which are present in the input value register RGI, do not potentially have a periodicity that is equal to the cell index parameter x. In that case, the cadence pattern detector CPD carries out step SCPD8.
In step SCPD8, the cadence pattern detector CPD resets the counter value Cx to which the cell index parameter x points (Cx=0). That is, this counter value Cx is made equal to 0. As explained hereinbefore, the counter value Cx to which the cell index parameter x points is associated with a possible periodicity that corresponds with the cell index parameter x in terms of number of frames. Resetting this counter value Cx can be regarded as an assessment that the successive classification bits from the classification bit generator CBG do probably not have a periodicity that is equal to the cell index parameter x. There has been a negative test, as it were, for the periodicity concerned. The cadence pattern detector CPD will then subsequently carry out step SCPD9, which will be discussed hereinafter.
Conversely, in step SCPD9, the cadence pattern detector CPD increments by one unit the counter value Cx to which the cell index parameter x points (Cx:+1). That is, one unit is added to this counter value Cx, which becomes the new counter value for the cell Ccx to which the cell index parameter x points. Incrementing this counter value Cx can be regarded as an assessment that the successive classification bits are likely to have a periodicity that is equal to the cell index parameter x. There has been a positive test, as it were, for the periodicity concerned.
In step SCPD10, which succeeds step SCPD9, the cadence pattern detector CPD verifies whether the following two conditions are true or not. Firstly, is the detected period equal to 0 (Pd=0)? Secondly, is the counter value Cx to which the cell index parameter x points, equal to or larger than the cell index parameter x, which is a natural number (Cx≧x)? In case the first condition is true, no period has been detected yet. In case the second condition is true, there have been a number of successive positive tests greater than the periodicity “x” to which the counter value of interest Cx is associated. In case both conditions are true, the cadence pattern detector CPD carries out step SCPD11 subsequent to step SCPD10. In case the first condition is not true, a period of a relatively great length has already been detected. In case the second condition is not true, there has been an insufficient number of positive tests thus far. In case any of the aforementioned two conditions is not true, the cadence pattern detector CPD carries out step SCPD12 subsequent to step SCPD10.
In step SCPD11, which succeeds step SCPD10 if the aforementioned condition is true, the cadence pattern detector CPD determines that the detected period Pd is equal to the cell index parameter x (Pd=x). This is because there has been a sufficient number of positive tests for the periodicity concerned. The detected period Pd will not be altered when the cadence pattern detector CPD continues carrying out the steps illustrated in
In step SCPD12, which may succeed steps SCPD8 or SCPD10, the cadence pattern detector CPD decrements the cell index parameter x by one unit (x:−1). Referring to
Each of the
In
In each table, the cell index parameter x, which occurs in steps illustrated in
In
In
In more detail,
In
In
In
In
In
In
The detected period Pd will remain 5 for any subsequently received detection bit from the sequence of detection bits, assuming that the periodicity remains 5.
In step SDMC1, the difference metric calculator DMC starts a scan of the current image IMc in accordance with a given pattern (ST_SCN). The difference metric calculator DMC successively designates pixels while scanning the current image IMc. Each designated pixel has a particular spatial position within the current image IMc. The difference metric calculator DMC repetitively carries out steps SDMC2-SDMC7 for each designated pixel until the scan is completed. In doing so, the difference metric calculator DMC successively updates a sum of local differences SMDF, which will be explained in greater detail hereinafter. The sum of local differences SMDF is given the value 0 before the difference metric calculator DMC starts the scan, which involves successively carrying out steps SDMC2-SDMC7.
In step SDMC2, the difference metric calculator DMC defines a set of neighboring pixels SPn in the previous image Imp (DEF_SPn). The pixels of this set have respective positions in the previous image IMp that are relatively similar to the position of the designated pixel in the current image IMc. For example, the difference metric calculator DMC may define a particular area that comprises the position of the designated pixel. This area can be projected on the previous image IMp. Pixels in the previous image IMp that fall into this projected area constitute the set of neighboring pixels SPn.
In step SDMC3, the difference metric calculator DMC determines a maximum value MAX and a minimum value MIN within the set of neighboring pixels SPn in the previous image IMp (DEF_MAX&MIN). In the set of neighboring pixels SPn, there will be two extremes in terms of pixel values: a pixel with a highest value and a pixel with a lowest value. The maximum value MAX corresponds with the highest pixel value within the set of neighboring pixels SPn. The minimum value MIN corresponds with the lowest pixel value.
In step SDMC4, the difference metric calculator DMC determines whether the following condition is true or not: the designated pixel has a value that is comprised between the minimum value MIN minus a threshold TH and the maximum value MAX plus the threshold TH (MIN−TH<Pi<MAX+TH ?). In case the aforementioned condition is true, it can be said that there is relatively little difference between the current image IMc and the previous image IMp at the position of interest. In that case, the difference metric calculator DMC carries out step SDMC5. In case the aforementioned condition is false, it can be said that there is a significant difference between the current image IMc and the previous image IMp at the position of interest. In that case, the difference metric calculator DMC carries out step SDMC6.
It should be noted that the threshold TH, which is applied in step SDMC5, may be fixed or variable. In the latter case, the threshold TH may depend on, for example, local spatial activity in the vicinity of the position concerned. The threshold TH may be relatively low if the current image IMc and the previous image IMp are relatively smooth in the vicinity of the position concerned. Conversely, the threshold TH may be relatively high if there are relatively many details in the vicinity of the position concerned. It should also be noted that the threshold TH may be asymmetric in the sense that different thresholds are associated with the minimum value MIN and the maximum value MAX.
In step SDMC5, the difference metric calculator DMC determines that the local difference for the designated pixel is equal to 0 (DF@Pi=0). The sum of local differences SMDF has a given value, which is maintained in step SDMC5 (SMDF: =). That is, the sum of local differences SMDF has the same value before and after step SDMC5.
In step SDMC6, the difference metric calculator DMC determines that the local difference for the designated pixel is equal to 1 (DF@Pi=1). The sum of local differences SMDF is incremented by one unit (SMDF: +1). That is, a sum of local differences SMDF will be one unit higher after step SDMC6.
In step SDMC7, the difference metric calculator DMC verifies whether the scan is complete or not (SCN=CMPL?). In case the scan is not complete, the difference metric calculator DMC designates a subsequent pixel by moving one position in the pattern of the scan. This is done in step SDMC8 (NXT_Pi), which is followed by steps SDMC2-SDMC7 that are carried out for the subsequent designated pixel. In case the scan is complete, the difference metric calculator DMC determines that the difference metric DM for the current image IMc is equal to the sum of local differences SMDF and the end of the scan. This is done in step SDMC9 (DM=SMDF). The difference metric calculator DMC applies the difference metric DM, which has been established by carrying out the series of steps illustrated in
In step SCBG1, the classification bit generator CBG determines an expected classification bit Pr[BCN+1] for the frame of interest on the basis of the pattern indication PI (PIPr[BcN+1]). That is, the classification bit generator CBG effectively predicts on the basis of the pattern indication PI whether the frame of interest will be classified as an original frame or a repeat frame.
In step SCBG2, the classification bit generator CBG determines whether the difference metric DMN+L for the frame of interest is in conformity with the expected classification bit Pr[BCN+1], or not (DMN+1˜Pr[BcN+1]?). For example, the difference metric DMN+1 should have a relatively low value if the expected classification bit Pr[BCN+1] classifies as the frame of interest as a repeat frame. Conversely, the difference metric DMN+1 should have a relatively high value if the expected classification bit Pr[BCN+1] classifies as the frame of interest as an original frame. In case the difference metric DMN+1 is in conformity with the expected classification bit Pr[BCN+1], the classification bit BCN+1 is equal to the expected classification bit Pr[BCN+1]. Step SCBG10 symbolizes this conclusion (BCN+1=Pr[BcN+1]). Conversely, in case the difference metric DMN+L is not in conformity with the expected classification bit Pr[BCN+1], the classification bit generator CBG continues and carries out steps SCBG3 and SCBG4.
In step SCBG3, the classification bit generator CBG calculates a measure of probability M1 for a sequence of classification bits to correspond with a sequence of difference metrics that the difference metric calculator DMC has produced (M1[DMN+1, DMN, DMN−1, . . . ]). The measure of probability M1 can be seen as a degree of match between the sequence of classification bits concerned and the sequence of difference metrics. The classification bit generator CBG calculates several of such measures M1 for various sequences of classification bits. A particular sequence of classification bits will have the highest measure of probability M1H. This particular sequence provides a prediction of the classification bit BCN+1 for the frame of interest.
In step SCBG4, the classification bit generator CBG determines whether the sequence of classification bits that has the highest measure of probability M1H is in conformity with expected classification bit Pr[BCN+1], or not (M1H ˜Pr[BcN+1]?). That is, the classification bit generator CBG determines whether the prediction on the basis of the sequence of difference metrics corresponds with the expected classification bit Pr[BCN+1] on the basis of the pattern indication PI, or not. In case the sequence of classification bits that has the highest measure of probability M1H in conformity with the expected classification bit Pr[BCN+1], the classification bit is equal to the expected classification bit Pr[BCN+1]. Step SCBG10 symbolizes this conclusion (BCN+1=Pr[BcN+1]). In the opposite case, which means there is no conformity, the classification bit generator CBG continues and carries out steps SCBG5-SCBG8.
In step SCBG5, the classification bit generator CBG requests the difference metric calculator DMC to calculate additional difference metrics (RQ→DMC). An additional difference metric DMN+1 may be calculated as illustrated in
In step SCBG6, the difference metric calculator DMC provides a set of additional difference metrics S_DMa in response to the request that the classification bit generator CBG has made (DMC: S_DMa→CBG).
In step SCBG7, the classification bit generator CBG calculates a new measure of probability M2 for a sequence of classification bits on the basis of the additional difference metrics, which have become available (M2[S_Dma]). The classification bit generator CBG calculates several of such new measures M2 for various sequences of classification bits. A particular sequence of classification bits will have the highest new measure of probability M2H. This particular sequence provides a new prediction of the classification bit for the frame of interest.
In step SCBG8, the classification bit generator CBG determines whether the sequence of classification bits that has the highest new measure of probability M2H is in conformity with expected classification bit Pr[BCN+1], or not (M2H˜Pr[BcN+1]?). That is, the classification bit generator CBG determines whether the new prediction, which takes into account the additional difference metrics, corresponds with the expected classification bit Pr[BCN+1] on the basis of the pattern indication PI, or not. In case the sequence of classification bits that has the highest new measure of probability M2H in conformity with the expected classification bit Pr[BCN+1], the classification bit is equal to the expected classification bit Pr[BCN+1] Step SCBG10 symbolizes this conclusion (BCN+1=Pr[BcN+1]). In the opposite case, which means there is no conformity, the classification bit generator CBG finally concludes that the classification bit is unequal to the expected classification bit Pr[BCN+1]. Step SCBG9 symbolizes this conclusion (BCN+L ≠Pr[BcN+1]), which implies the pattern indication PI will no longer apply. The pattern has been broken, which may be due to, for example, a scene change.
It should be noted that any of the functional entities illustrated in
The volatile memory RAM comprises the input value register RGI, the counter value register RGC, and the detected period Pd register illustrated in
The processor PRC illustrated in
The detailed description hereinbefore with reference to the drawings is merely an illustration of the invention and the additional features, which are defined in the claims. The invention can be implemented in numerous different manners. In order to illustrate this, some alternatives are briefly indicated.
The invention may be applied to advantage in any type of product or method that can be arranged to process a video signal, which has a pull-down pattern. The video system VSY illustrated in
Film cadence detection in accordance with the invention may be used for numerous different applications. For example, the film cadence detection may be used for a so-called pull-down optimization.
A film cadence detector in accordance with the invention may comprise further functional entities, which are not illustrated in
There are numerous different manners to implement a film cadence detector in accordance with the invention.
There numerous different manners to calculate a difference metric for an image, which represents a degree of similarity between that image and another image.
The terms “image” and “frame” should be understood in a broad sense. These terms includes a frame, a field, and any other entity that may wholly or partially constitute an image or a picture.
There are numerous ways of implementing functions by means of items of hardware or software, or both. In this respect, the drawings are very diagrammatic, each representing only one possible embodiment of the invention. Thus, although a drawing shows different functions as different blocks, this by no means excludes that a single item of hardware or software carries out several functions. Nor does it exclude that an assembly of items of hardware or software or both carry out a function.
The remarks made herein before demonstrate that the detailed description with reference to the drawings, illustrate rather than limit the invention. There are numerous alternatives, which fall within the scope of the appended claims. Any reference sign in a claim should not be construed as limiting the claim. The word “comprising” does not exclude the presence of other elements or steps than those listed in a claim. The word “a” or “an” preceding an element or step does not exclude the presence of a plurality of such elements or steps.
Number | Date | Country | Kind |
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07300699.1 | Jan 2007 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB2007/055278 | 12/21/2007 | WO | 00 | 6/30/2009 |