Patent Application
20090189645
This application claims the benefit of Taiwan application Serial No. 97103168, filed Jan. 28, 2008, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a filter, and more particularly to a filter enabling the pulse width of the input signal to be the same with that of the output signal without using an additional set of high frequency pulse.
2. Description of the Related Art
Many digital signal interfaces and universal serial buses (USB) have a specification regarding minimum pulse width and noise suppression to avoid the noise of an electronic system affecting the quality of digital signal and incurring erroneous actions. In prior art, such problem is resolved by using a first conventional filter or a second conventional filter.
First Conventional Filter:
Referring to
However, the conventional filter 10 makes the overall signals decayed. As a result, the pulse width of the output signal Sout1 cannot maintain the same with that of the input signal Sin1.
Second Conventional Filter:
Currently, the electronic system is directed towards low power consumption, and most of the time, an electronic system would work on a stand-by mode or a sleep mode. An electronic system working on a stand-by mode or a sleep mode cannot provide high frequency pulse to the conventional filter to filter the noise.
The invention is directed to a filter, which enables the pulse width of the input signal to be the same with that of the output signal without using high frequency pulse.
According to a first aspect of the present invention, a filter is provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal.
According to a second aspect of the present invention, a filtering method. The filtering method includes the following steps. (a) A first compare voltage is generated according to an input signal. (b) A second compare voltage is generated, wherein the second compare voltage equals the first reference voltage when the first compare voltage is not over the first reference voltage, the second compare voltage equals the second reference voltage when the first compare voltage is over the first reference voltage, and the first reference voltage and the second reference voltage depend on a minimum pulse width. (c) A filtered signal is outputted according to the first compare voltage and the second compare voltage outputs. (d) A filtered signal is inverted to a filtered signal to an output signal.
The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Circuit of Filter:
Referring to
When the first compare voltage V1 is not over the first reference voltage Vref1, the second compare voltage V2 equals the first reference voltage Vref1. When the first compare voltage V1 is over the first reference voltage Vref1, the second compare voltage V2 equals the second reference voltage Vref2. The first reference voltage Vref1 and the second reference voltage Vref2 depend on a minimum pulse width determined according to a digital signal interface or a universal serial bus (USB) such as an I2C.
The first compare voltage V1 and the second compare voltage V2 are respectively inputted to a non-inverse input end and an inverse input end of the comparator 40. The comparator 40 outputs a filtered signal Voutb according to the first compare voltage V1 and the second compare voltage V2. The inverter 50 receives the filtered signal Voutb and then inverts the filtered signal Voutb to an output signal Sout2.
Referring to
The charging circuit 220 charges the capacitor C according to the inverse input signal Sin2′. When the inverse input signal Sin2′ equals a high logic level, the first compare voltage V1 boosts as the capacitor C is charged. The high logic level is logic “1” for example.
The first discharging circuit 230 discharges the capacitor C according to an input signal Sin2. When the input signal Sin2 equals the high logic level, the first compare voltage V1 steps down as the capacitor C is discharged.
The second discharging circuit 240 further includes a switch SW1 and a logic gate 244. The switch SW1 and the capacitor C are connected in parallel. The logic gate 244 is an AND gate for example. The second discharging circuit 240 discharges the capacitor C according to an input signal Sin2 and the output signal Sout2. When the input signal Sin2 and output signal Sout2 equals the high logic level, the logic gate 244 turns on the switch SW1, such that the voltage stored in the capacitor C is discharged via the switch SW1, and the first compare voltage V1 plummets as the capacitor C is discharged.
The second compare voltage generation unit 30 further includes a current source 310, a resistor R1, a resistor R2, a switch SW2, a switch SW3, a switch SW4, an inverter 330 and a logic gate 320. The current source 310 is connected in serial with the switch SW3, the resistor R1 and the resistor R2, but is connected in parallel with the switch SW2 and the resistor R1. The switch SW3 is controlled by the filtered signal Voutb and the inverse input signal Sin2′, so as to selectively and electrically connect the current source 310 to the resistor R1.
The logic gate 320 is an NOR gate for example. When the filtered signal Voutb and the inverse input signal Sin2′ are both at a low logic level, the logic gate 320 outputs a high logic level. The inverter 330 inverts the high logic level to the low logic level to turn off the switch SW3. As the switch SW3 is turned off, the electrical connection between the current source 310 and the resistor R1 is cut off. Thus, under such a stable status, the filter 60 does not consume power, and power consumption can be thus saved.
To the contrary, if the filtered signal Voutb and the inverse input signal Sin2′ are not both at a low logic level, the switch SW3 is turned on, such that the current source 310 and the resistor R1 are electrically connected. The current I provided by the current source 310 flows to the resistor R1 and the resistor R2 from the switch SW3 to generate a first reference voltage Vref1 used as the second compare voltage V2 (as indicated in
The switch SW4 is also controlled by the filtered signal Voutb and the inverse input signal Sin2′ to selectively and electrically connects the output end of the comparator 40 to a ground end. When the filtered signal Voutb and the inverse input signal Sin2′ are both at a low logic level, the logic gate 320 turns on the switch SW4, such that the output end and the ground end of the comparator 40 are electrically connected. As the filtered signal Voutb equals the low logic level, the output signal Sout2 is set as the high logic level.
The switch SW2 controlled by the filtered signal Voutb is selectively turned on. When the first compare voltage V1 is larger than the first reference voltage Vref1, the filtered signal Voutb boosts to the high logic level from the low logic level, such that the switch SW2 is turned on. The current I provided by the current source 310 flows to the resistor R2 via the switch SW2 to generate a second reference voltage Vref2 used as the second compare voltage V2.
The filter 60 selectively works on a noise filtering mode or a signal passing mode according to an input signal Sin2. If the input signal Sin2 is interfered with by a noise, the filter 60 works on a noise filtering mode to filter the noise. If the input signal Sin2 is not interfered with by the noise, the filter 60 works on a signal passing mode such that the input signal Sin2 is unchanged, the input signal Sin2 passes through the filter 60 without distortion and then is outputted. The status of the filter 60 working on a noise filtering mode or a signal passing mode is further elaborated below.
Timing of Noise Filtering Mode:
Referring to
When the filter 60 works on a time period T1, the input signal Sin2 and the first compare voltage V1 are respectively equal to the high logic level and the low logic level, and the inverse input signal Sin2′ equals the low logic level. During the time period, the logic gate 320 and the switch SW4 are controlled by the filtered signal Voutb and the inverse input signal Sin2′, such that the filtered signal Voutb is forced to equal the low logic level and the output signal Sout2 is forced to equal the high logic level. Besides, the switch SW3 is controlled by the filtered signal Voutb and the inverse input signal Sin2′ to be turned off, such that the power consumption of the filter 60 during the time period T1 is almost 0.
Afterwards, when the filter 60 works on a time period T2, the input signal Sin2 forms a noise pulse due to the interference of the noise, such that the input signal Sin2 steps down to the low logic level from the high logic level and the inverse input signal Sin2′ equals the high logic level. The charging circuit 220 is controlled by the inverse input signal Sin2′ and starts to charge the capacitor C, such that the first compare voltage V1 gradually boosts. As most of the noise pulse widths are within 50 n second, the first compare voltage V1 is not larger than the first reference voltage Vref1 during the time period T2. Thus, the filtered signal Voutb still equals the low logic level, such that the output signal Sout2 equals the high logic level.
Lastly, when the filter 60 works on a time period T3, the input signal Sin2 boosts to the high logic level from the low logic level. The first discharging circuit 230 is controlled by the input signal Sin2 to discharge the capacitor C, such that the first compare voltage V1 steps down to the low logic level. Besides, the second discharging circuit 240 is controlled by the input signal Sin2 and the output signal Sout2 to discharge the capacitor C to make the first compare voltage V1 step down faster. As the first compare voltage V1 is at a low logic level, the filtered signal Voutb still equals low logic level, such that the output signal Sout2 equals the high logic level.
Timing of Signal Passing Mode:
Referring to
When the filter 60 works on a time period T4, the input signal Sin2 and the first compare voltage V1 are respectively equal to the high logic level and the low logic level, and the inverse input signal Sin2′ equals the low logic level. During the time period, the logic gate 320 and the switch SW4 are controlled by the filtered signal Voutb and the inverse input signal Sin2′, such that the filtered signal Voutb is forced to equal the low logic level and the output signal Sout2 is forced to equal the high logic level. Besides, the switch SW3 is controlled by the filtered signal Voutb and the inverse input signal Sin2′ to be turned off, such that the power consumption of the filter 60 during the time period T4 is almost 0.
Afterwards, when the filter 60 works on a time period T5, the input signal Sin2 steps down to the low logic level from the high logic level and the inverse input signal Sin2′ equals the high logic level. The charging circuit 220 is controlled by the inverse input signal Sin2′ and starts to charge the capacitor C, such that the first compare voltage V1 gradually boosts. As the first compare voltage V1 is not larger than the first reference voltage Vref1 during the time period T5, the filtered signal Voutb still equals the low logic level, such that the output signal Sout2 equals the high logic level.
Next, when the filter 60 works on a time period T6, the input signal Sin2 still equals the low logic level, and the first compare voltage V1 is larger than the first reference voltage Vref1 because the charging circuit 220 continuously charges the capacitor C. As the first compare voltage V1 is larger than the first reference voltage Vref1, the filtered signal Voutb boosts to the high logic level from the low logic level, such that output signal Sout2 steps down to the low logic level from the high logic level. After the filtered signal Voutb boosts to the high logic level from the low logic level, the above second compare voltage V2 (as indicated in
After that, when the filter 60 works at a time period T7, the input signal Sin2 boosts to the high logic level from the low logic level, and the first discharging circuit 230 is controlled by the input signal Sin2 and starts to discharge the capacitor C, such that the first compare voltage V1 gradually steps down. As the first compare voltage V1 is not smaller than the second reference voltage Vref2 during the time period T7, the filtered signal Voutb still equals the high logic level, such that the output signal Sout2 equals the low logic level.
Lastly, when the filter 60 works at a time period T8, the input signal Sin2 still equals the high logic level and the first compare voltage V1 is smaller than the second reference voltage Vref2 because the first discharging circuit 230 continuously discharges the capacitor C. As the first compare voltage V1 is smaller than the second reference voltage Vref2, the filtered signal Voutb steps down to the low logic level from the high logic level, such that output signal Sout2 boosts to the high logic level from the low logic level. During this time period, both the input signal Sin2 and the output signal Sout2 are at a high logic level, so the logic gate 244 turns on the switch SW1 to make the first compare voltage V1 step down faster.
The filter 60 can make the time period T5 equal the time period T7 by appropriately adjusting the charging circuit 220, the first discharging circuit 230, the first reference voltage Vref1 and the second reference voltage Vref2. Thus, the pulse width of the output signal Sout2 equals the pulse width of the input signal Sin2, such that the output signal Sout2 will not be distorted due to signal decay.
Filtering Method:
Referring to
According to the filter and the filtering method disclosed in the above embodiments of the invention, the pulse width of the output signal is the same with that of the input signal without receiving a set of high frequency pulse. Regardless the electronic system works on a stand-by mode or a sleep mode, the filter and the filtering method disclosed in the above embodiments still filter noise and function normally.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 97103168 | Jan 2008 | TW | national |
