Filter circuit for communication

Abstract

The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

Description

FIELD OF THE INVENTION

The present invention relates to a filter circuit for communication, especially to a matched filter effective for a spread spectrum communication system for the mobile cellular radio and wireless LAN.

BACKGROUND OF THE INVENTION

A matched filter is a filter for judging the identification between two signals. In the spread spectrum communication, each user who receives a signal processes a received signal by a matched filter using spreading code allocated for the user to as to find a correlation peak for acquisition and holding.

Here, assuming that a spreading code is d(i), sampling interval is Δt, a length of spreading code is N, a received signal before a time t is x(T-iΔt), a correlation output y(t) of matched filter is as in formula (1). In formula (1), d(i) is a data string of 1 bit data. $$ y ⁡ ( t ) = ∑ i = 0 N - 1 ⁢ d ⁡ ( i ) ⁢ x ⁡ ( t - i ⁢   ⁢ Δ ⁢   ⁢ t ) ( 1 )

A conventional matched filter circuit is described here. In an accumulation circuit of a digital matched filter in FIG. 16 , digitized input signal X is held in a shift register SFT-REG and shifted, then, a multiplier registered in a register REG is multiplied to the input signal on the predetermined sample timing by a plurality of digital multiplying portions DM. The outputs of multiplying portions are added by the digital adder DAD. These operations correspond to the formula (1). For the acquisition, double or higher order of sampling is necessary. In such a case, the circuit in FIG. 16 is plurally structured. Consequently, the size of the whole circuit was large and consumed much electric power. It is a serious defect. Though a circuit of SAW device was used, the total circuits cannot be incorporated within one LSI and S/N ratio was low.

The applicant of the present invention proposes a matched filter circuit by an analog circuit in FIG. 17 . The electric power consumption was reduced by a circuit with a multiplier and an adder of voltage driven type using a capacitive coupling. However, a digital output is also necessary as an output of a matched filter because conventional digital communication will be also used for the present.

SUMMARY OF THE INVENTION

The present invention solves the above conventional problems and has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption.

In a matched filter circuit according to the present invention, the function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

It is possible to use a circuit of rather low speed as an A/D converting circuit by the matched filter circuit according to the present invention. Therefore, it is profitable considering the cost, yield and electric power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a matched filter circuit according to the present invention.

FIG. 2 shows a sampling and holding circuit in the first embodiment of the present invention.

FIG. 3 shows a shows one sampling and holding circuit in a sampling and holding circuit.

FIG. 4 shows a circuit of the first type switch in the embodiment.

FIG. 5 shows a circuit of the second type switch in the embodiment.

FIG. 6 shows a circuit of the third type switch in the embodiment.

FIG. 7 shows a circuit of an A/D converter in the embodiment.

FIG. 8 shows a circuit of the A/D converter in FIG. 7 .

FIG. 9 shows a shows an accumulation circuit in the embodiment.

FIG. 10 shows a sampling and holding circuit in the accumulation circuit in FIG. 9 .

FIG. 11 shows a circuit of an inverted amplifying portion included in the embodiment.

FIG. 12 shows a circuit of a multiplexer in the sampling and holding circuit if FIGS. 8 and 10 .

FIG. 13 shows a circuit of the first addition circuit in the accumulation circuit in FIG. 9 .

FIG. 14 shows a circuit of the second addition circuit in the accumulation circuit in FIG. 9 .

FIG. 15 shows a circuit of the third addition circuit in the accumulation circuit in FIG. 9 .

FIG. 16 shows a block diagram of conventional digital matched filter.

FIG. 17 shows a block diagram of proposed analog matched filter.

FIG. 18 shows a timing chart of the timing of action of the sampling and holding circuit.

FIG. 19 shows a timing chart of the timing of another action of the sampling and holding circuit.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter, the first embodiment of a matched filter according to the present invention is described with reference to the attached drawings.

In FIG. 1 , a matched filter includes a sampling and holding circuit “S/H 3 ” for holding an analog output signal of the circuit “MF” for addition and multiplication and A/D converting portion “A/D” for digitizing an analog output signal Aout from the sampling and holding circuit at the next stage to the circuit “MF” in FIG. 17 . The sampling and holding circuit is controlled by a peak detector “PD”. Accumulating portion outputs a clock signal C 1 for deciding the time of holding data of an inside sampling and holding circuit and a reset signal RST for showing the timing of holding data of the first sampling and holding circuit to the peak detector PD. The peak detector controls S/H 3 according to the signals.

The peak detector outputs a clock C 2 corresponding to C 1 and a signal N indicating a number of a datum to be held (i in the formula (1)) by the sampling and holding circuit S/H 3 . A plurality of Ns can be output up to a predetermined number, for example three. Each number is once registered in a register in the sampling and holding circuit (not shown in FIG. 1 ), a register selecting signal RSEL for the registration is input from PD to S/H 3 .

In FIG. 2 , the sampling and holding circuit S/H 3 includes a plurality of sampling and holding circuits SH 21 , SH 22 and SH 23 for holding Aout of an output of accumulating portion by an appropriate timing. The outputs of the sampling and holding circuits are connected to switches SB 2 , SB 3 and SB 4 , respectively. When a supply voltage is Vdd, the reference voltage Vr of Vdd/ 2 is input to each sampling and holding circuit, and Vr is input to a switch SB 1 arranged in parallel with the switches above. Outputs of SB 1 to SB 4 are input to a capacitance S 21 in parallel, and an output of a capacitance C 21 is input to an inverted amplifier INV 2 . An output of the inverted amplifier INV 2 is fed back to the input through a capacitance C 22 . The outputs of SB 1 to SB 4 are output as analog output signal Ao 2 with a good linearity.

SH 21 to SH 23 and SB 1 to SB 4 are controlled by controlling signal STRL 2 CTRL 2 from a controller (shown by “CONTROLLER” in FIG. 2 ). In the controller, a plurality of registers corresponding to a plurality of peaks of multipass are set, and the timing to input data, that is, the number showing the location of a peak in the data (“a peak number”, hereinafter) can be registered by it. A register selecting signal RSEL, a peak number signal N and a register writing clock C 2 are input to the controller from the peak detector PD, and the peak number of each register is written.

In an inverted amplifying portion INV 2 , a switch SA 1 is settled for connecting the input and output. An offset voltage of the input of the inverted amplifying portion INV 2 can be refreshed by closing SA 1 . High accuracy of outputs of sampling and holding circuit can be surely obtained by the refresh.

Switches SB 2 to SB 4 are closed at the timing when Aout held in SH 21 to SH 23 are to be output to the next stage, and SB 1 is closed when INV 2 , C 21 and C 22 are refreshed.

The sampling and holding circuit SH 21 includes switches SWH 1 and SWH 2 connected Aout and Vr, respectively. Outputs of the switches are input to inverter INV 3 through capacitance C 31 , similar to the case of S/H 3 . An input and an output of the inverter INV 3 are connected with each other parallelly by a capacitance C 32 and a switch SA 2 . The sampling and holding circuit SH 21 is controlled by a control signal CTRL 3 to take and hold Aout for an electrical charge of C 31 and C 32 at the timing SWH 2 is opened. Good linearity of the output of the sampling and holding circuit is guaranteed by a high gain of INV 3 and the feedback of C 32 , SH 22 and SH 23 are structured similarly to SH 21 .

In FIG. 4 , the switch SA 1 is structured by connecting in serial a MOS transistor T 4 and a dummy transistor DT 4 (about half size of T 4 ) with inverse polarity of that of T 4 . To the gate, a controlling signal CTRL 4 and a signal inverted by an in letter I 4 are input and an input Tin 4 is conducted to an output To 4 when CTRLCTRL 4 is high level. DT 4 is connected to the input of INV 2 , that is to a capacitance C 21 in the state of floating, so as to cancel out the influence of residual electric charge of C 21 on refreshing by inverse polarity of DT 4 . Therefore, it is prevented that the output becomes inaccurate because of the influence of switch SA 1 . As SA 2 is the same structure as SA 1 , it is omitted to be shown in a figure. Switches SA . . . described below also have the same structure.

In FIG. 5 , a switch SB 1 has MOS transistor T 5 to which a control signal CTRL 5 and a signal inverted by an inverter I 5 are input at its gate. When CTRLCTRL 5 is high level, an input Tin 5 is conducted to an output To 5 . As SB 2 to SB 4 are same as SB 1 , they are not shown in a figure. Switches SB . . . described below also have the same structure.

In FIG. 6 , in the switch SWH 1 , CMOST 6 MOS transistor T 6 and dummy transistor DT 6 (about half size of T 6 ) with inverse polarity are connected in serial. A control signal CTRL 6 and a signal inverted by an inverter 16 are input to the gate of the switch SWHISWH 1 ; an input Tin 6 is conductive toward an output of To 6 when CTRL 6 is high level. DT 6 is connected to the output, that is to a capacitance C 31 in the state of floating, so as to cancel out the influence of residual electric charge of C 31 on refreshing by inverse polarity of DT 6 . Therefore, it is prevented that the output becomes inaccurate because of the influence of switch SWH 1 . As SWH 2 is the same structure as SA 1 , it is omitted to be shown in a figure.

The timing of sampling and holding by the sampling and holding circuit S/H 3 is shown in FIG. 18 . After a predetermined time Th from when the signal is input to SH 21 , data of SH 21 is output from SB 2 . Before completion of data output, SH 22 starts to take in data, and data of SB 3 is output after it. After holding data in SH 23 , data is output from SB 4 . Cyclic period TcTo of the sampling and holding is given from a starting point of the beginning of taking data by SH 21 as in FIG. 18 . Assuming the time distance from beginning of output by SB 2 to the completion of it by SB 4 to be T 1 , the time (Th+T 1 ) is settled shorter than TcTo. The circuit is refreshed by switches SA 1 and SB 1 within the time {TcTo-(Th+T 1 )}.

The embodiment above is the case that three peaks are detected and all the circuits in a sampling and holing circuit is used. In the case of fewer peaks, for example two peaks are detected, the timing is as in FIG. 19 .

In FIG. 19 , the time distance Td from taking data by SH 21 to that by Sh 22 and the time distance Th from taking data by SH 21 to the output by SB 2 are settled similarly to that in FIG. 18 . Also, an output period T 1 is settled similarly to that of FIG. 18 .

In FIG. 7 , an A/D converter includes the first quantizing circuit Q 1 to which an output of S/H 3 (Ai 7 in FIG. 7 ) is input and the second quantizing circuit Q 2 in which an output of Q 1 and inverse output of Ai 7 are input. Upper bits and lower bits are generated in Q 1 and Q 2 , respectively.

Quantizing circuit Q 1 includes four stages of thresholding, circuits Th 1 , Th 2 , Th 3 and Th 4 as in FIG. 8 , b 0 ′,b 1 ′ and b 2 ′ of inverse outputs of b 0 to b 2 of each thresholding circuit of upper three stages are generated as inside intermediate data.

Th 4 of the lowest thresholding circuit includes a capacitive coupling CP 84 to which input signals Ai 8 , b 0 ′, b 1 ′ and b 2 ′ are input, and four stages of MOS inverters I 841 , I 842 , I 843 and I 844 . An output of CP 84 is connected to I 841 . The signal b 3 is generated as an output of I 844 . In CP 84 , capacitances C 841 , C 842 , C 843 , C 844 , C 845 and C 846 are connected in parallel, to which input signals Ai 8 , b 0 ′, b 1 ′, b 2 ′, supply voltage Vcc (=Vdd) and the ground are connected, respectively. Ai 8 is input to C 841 through multiplexer MUX which input Ai 8 or the reference voltage Vr to C 841 , alternatively.

Th 3 of the second digit from the lowest thresholding circuit includes a capacitive coupling CP 83 to which the input signals Ai 8 , b 0 ′, and b 1 ′ are input, and four stages of MOS inverters I 831 , I 832 , I 833 and I 834 . An output of CP 83 is connected to I 831 . The signal b 3 is generated as an output of I 834 . In CP 83 , capacitances C 831 , C 832 , C 833 , C 834 and C 835 are connected in parallel, to which input signals Ai 8 , b 0 ′, b 1 ′, supply voltage Vcc and the ground are connected, respectively. Ai 8 is input to C 831 through multiplexer MUX which input Ai 8 or the reference voltage Vr to C 831 , alternatively.

Th 2 of the third digit from the lowest thresholding circuit includes a capacitive coupling CP 82 to which the signals Ai 8 and b 0 ′ are input, and four stages of MOS inverters I 821 , I 822 , I 823 and I 824 . An output of CP 82 is connected to I 821 . The signal b 1 is generated as an output of I 824 . In CP 82 , capacitances C 821 , C 822 , C 823 and C 824 are connected in parallel, to which input signals Ai 8 , b 0 ′, supply voltage Vcc and the ground are connected, respectively. Ai 8 is input to C 821 through multiplexer MUX which input Ai 8 or the reference voltage Vr to C 821 , alternatively.

Th 1 of the upper thresholding circuit includes a capacitive coupling CP 81 to which the signal Ai 8 is input and four stages of MOS inverters I 811 , I 812 , I 813 and I 814 . An output of CP 81 is connected to I 811 . The signal b 0 is generated as an output of I 814 . In CP 81 , capacitances C 811 , C 812 , and C 813 are connected in parallel, to which input signal Ai 8 , supply voltage Vcc and the ground are connected respectively. Ai 8 is input to C 811 through multiplexer MUX which input Ai 8 or the reference voltage Vr to C 811 , alternatively.

The capacities of CP 81 to CP 84 are shown in TABLE 1, and outputs b 0 , b 1 , b 2 and b 3 in response to input signal Ai 8 are shown in TABLE 2.

TABLE 1
CAPACITIVE
COUPLING	CAPACITANCE	CAPACITY
CP84	C841	16Cu
	C842	8Cu
	C843	4Cu
	C844	2Cu
	C845	Cu
	C846	Cu
CP83	C831	16Cu
	C832	8Cu
	C833	4Cu
	C834	2Cu
	C835	2Cu
CP82	C821	16Cu
	C822	8Cu
	C823	4Cu
	C824	4Cu
CP81	C811	16Cu
	C812	8Cu
	C813	8Cu

TABLE 2
INPUT	INNER INTERMEDIATE
VOLTAGE	OUTPUT	OUTPUT
Vi8	b3′	b2′	b1′	b0′	b3	b2	b1	b0
0 ≦ Vi8 < Va	Vdd	Vdd	Vdd	Vdd	0	0	0	0
Va ≦ Vi8 <	0	Vdd	Vdd	Vdd	Vdd	0	0	0
2Va
2Va ≦ Vi8 <	Vdd	0	Vdd	Vdd	0	Vdd	0	0
3Va
3Va ≦ Vi8 <	0	0	Vdd	Vdd	Vdd	Vdd	0	0
4Va
4Va ≦ Vi8 <	Vdd	Vdd	0	Vdd	0	0	Vdd	0
5Va
5Va ≦ Vi8 <	0	Vdd	0	Vdd	Vdd	0	Vdd	0
6Va
6Va ≦ Vi8 <	Vdd	0	0	Vdd	0	Vdd	Vdd	0
7Va
7Va ≦ Vi8 <	0	0	0	Vdd	Vdd	Vdd	Vdd	0
8Va
8Va ≦ Vi8 <	Vdd	Vdd	Vdd	0	0	0	0	Vdd
9Va
9Va ≦ Vi8 <	0	Vdd	Vdd	0	Vdd	0	0	Vdd
10Va
10Va ≦ Vi8 <	Vdd	0	Vdd	0	0	Vdd	0	Vdd
11Va
11Va ≦ Vi8 <	0	0	Vdd	0	Vdd	Vdd	0	Vdd
12Va
12Va ≦ Vi8 <	Vdd	Vdd	0	0	0	0	Vdd	Vdd
13Va
13Va ≦ Vi8 <	0	Vdd	0	0	Vdd	0	Vdd	Vdd
14Va
14Va ≦ Vi8 <	Vdd	0	0	0	0	Vdd	Vdd	Vdd
15Va
15Va ≦ Vi8 <	0	0	0	0	Vdd	Vdd	Vdd	Vdd
16Va

Cu in TABLE 1 is not necessary to be the minimum capacity, it is all right if it is common to each capacitive coupling. In TABLE 2 , the voltage (Vdd/ 16 ) is indicated as Va.

The outputs from b 0 to b 3 are generated by the quantizing circuit Q 1 above. Signals b 0 to b 3 are binary weighted by the capacitive coupling CP 7 in FIG. 7 and added to an inverse output of the Ai 7 . Ai 7 is input to C 73 through inverted amplifying portion INV 71 whose output is fed back to its input through the capacitance C 72 . The output of the inverted amplifier is −Ai 7 (C 71 /C 72 ), where it is settled that C 71 =C 72 . An output of capacitive coupling CP 7 is input to Q 2 through inverted amplifying portion INV 72 whose output is fed back to its input through the capacitance C 74 . In the capacitive coupling CP 7 , capacitances C 73 , C 75 , C 76 C 77 , C 78 are connected in parallel, and −Ai 7 , b 0 , b 1 , b 2 and b 3 are connected to the capacitances. The ratio of the capacities in C 74 and CP 7 is; C 73 :C 74 :C 75 :C 76 :C 77 :C 78 = 16 : 1 : 8 : 4 : 2 : 1 . The quantizing circuit Q 2 is structured similar to that of Q 1 , the description of Q 2 is omitted.

In FIG. 9 , in accumulation circuit MF, an input voltage Vin (a voltage referencing the reference voltage Vr) is connected in parallel to a plurality of sampling and holding circuits S/H 91 to S/H 96 . Two types outputs of H (high) and L (low) are output from each sampling and holding circuit. A control circuit CTRL 9 is connected to the sampling and holding circuits, which controls the connection of Vin in order that Vin is successively input to one of sampling and holding circuits.

In the sampling and holding circuits, input voltage Vin is introduced to one of H and L, and the reference voltage Vr is connected to the other according to the control circuit. This selection of route is performed corresponding to 1 bit code to be multiplied to an input signal. Then, the multiplication is completed.

Sampling and holding circuits from S/H 91 to S/H 96 (They are represented by S/H 91 in the FIG. 10. ) are structured as in FIG. 10 , in which input voltage Vin is connected to a switch SB 15 similar to SB 1 . An output of switch SB 15 is connected to the capacitance C 91 whose output is connected to inverted amplifying portion INV 9 . An output of INV 9 is input to two multipliers MUX 91 and MUX 92 . The common reference voltage Vr is connected to the multiplexers. When SB 15 is closed, C 91 is charged by the electrical charge corresponding to Ai 9 and the linearity of the output is guaranteed by INV 9 . When the switch SB 15 is opened after it, the sampling and holding circuit S/H 91 holds Ai 9 .

The structure of the inverted amplifying portion INV 2 is as in FIG. 11 . An input voltage Ai 10 is input to three serial MOS inverters I 101 , I 102 and I 103 , Vo 10 of an output of the last stage MOS inverter I 103 is connected to an input of the first stage capacitance I 101 through the feedback capacitance C 22 (in FIG. 2 ), consequently, closed loop gain is formed. The capacity of the feedback capacitance C 22 is settled equal to that of C 21 (in FIG. 2 ), and the closed loop gain is settled as −1.

In the inverted amplifying portion INV 2 , I 103 is connected at its output to the ground through a grounded capacitance C 102 and I 102 is connected at its output to the supply voltage and the ground through a pair of balancing resistances RE 101 and RE 102 , respectively. Unstable oscillations of the inverted amplifying circuit including feedback circuit is prevented by such a structure.

As INV 3 , INV 71 , INV 72 and INV 9 are structured same as that of the INV 2 , they are omitted to be shown in figures.

As shown in FIG. 12 , in the multiplexer MUX in FIG. 8 , each of transistor circuits T 121 and T 122 is structured by connecting an nMOS transistor at its source and drain with pMOS transistor at its drain and source, respectively. Terminals of the source of the nMOS transistor in both transistor circuits are connected to the common output terminal TO 12 , and the input voltage Ai 8 shown in FIG. 8 (Ai 12 in FIG. 12 ) is connected to a terminal of the drain of nMOS transistor of T 121 . The reference voltage Vr is connected to a terminal of the drain of nMOS transistor of T 122 . A control signal CTRL 12 is input to a gate of nMOS transistor of the transistor circuit T 121 and a gate of pMOS transistor of the transistor circuit T 122 . A signal of inverted CTRL 12 by an inverter I 12 is input to gate of pMOS of T 121 and nMOS of T 122 . Consequently, when CTRL 12 is high level, T 121 is conductive and T 122 is cut off, and when low level, T 122 is conductive and T 121 is cut off. That is, MUX can alternatively output Ai 12 or Vr by the control of CTRL 12 . As multiplexers MUX 91 and MUX 92 in FIG. 10 are structured in the same way as that of MUX, the description is omitted.

As in FIG. 13 , an addition portion AD 91 p (AD 91 m has the same structure) includes a capacitive coupling CP 13 comprehending capacitances of the number corresponding to the number of sampling and holding circuits in a group, C 131 , C 132 and C 133 . An output of CP 13 is connected to INV 13 which is the same as INV 2 , and is output as an output voltage Ao 13 with good linearity.

Assuming input voltages of capacitances C 131 to C 133 to be Ai 131 , Ai 132 and Ai 133 , and a feedback capacitance of INV 13 to be CF 1 CF 13 , Ao 13 of an output of INV 13 is expressed as in the formula (2) $$ Ao 13 = - C 131 ⁢ Ai 131 + C 132 ⁢ Ai 132 + C 133 ⁢ Ai 133 CF 13 ( 2 )

Here, Ai 131 to Ai 133 and Ao 133 Ao 13 are the voltage referencing the reference voltage Vr, and it is settled that C 131 =C 132 =C 133 =CF 13 / 3 . A normalized output of inverse value of addition can be obtained as in formula (3). It is prevented that the maximum voltage exceeds the supply voltage by the normalization. $$ Ao 13 = - Ai 131 + Ai 132 + Ai 133 3 ( 3 )

As in FIG. 14 , an addition portion AD 92 includes a capacitive coupling CP 14 comprehending capacitances of the number corresponding to the number of connected sampling and holding circuits, C 141 and C 142 . An output of CP 14 is connected to INV 14 which is the same as INV 2 , and is output to an output of INV 14 with good linearity.

Assuming input voltages of capacitances C 141 and C 142 to be Ai 141 and Ai 142 , and a feedback capacitance of INV 14 to be CF 14 , an output Ao 14 of INV 14 is expressed as in the formula (4) $$ Ao 14 = - C 141 ⁢ Ai 141 + C 142 ⁢ Ai 142 CF 14 ( 4 )

Here, Ai 141 , Ai 142 and Ao 14 are the voltage referencing the reference voltage Vr, and it is settled that C 141 =C 142 =CF 14 / 2 . A normalized output of inverse value of addition can be obtained by it as in formula (5). It is prevented that the maximum voltage exceeds the supply voltage by the normalization. $$ Ao 14 = - Ai 141 + Ai 142 2 ( 5 )

As in FIG. 15 , an addition portion AD 93 includes a capacitive coupling CP 15 comprehending capacitances of the number corresponding to the number of circuits connected to AD 93 , two AD 91 p, two AD 91 m and AD 92 , C 151 , C 152 and C 153 . An output of CP 15 is connected to INV 15 which is the same as INV 2 , and is output to an output of INV 1 with good linearity.

Assuming input voltages (referencing Vr) of capacitances C 151 to C 153 to be Ai 151 , Ai 152 and Ai 153 , and a feedback capacitance of INV 15 to be CF 15 , Ao 13 Ao 15 of an output of INV 15 is expressed as in the formula (6) $$ Ao 15 = - C 15 ⁢ Ai 151 + C 152 ⁢ Ai 152 + C 153 ⁢ Ai 153 CF 15 ( 6 )

It is settled that C 151 =C 152 =C 153 / 2 +C 15 / 2 . A normalized output of inverse value of addition can be obtained by it as in formula (7). It is prevented that the maximum voltage exceeds the supply voltage by the normalization. The weight of C 153 is twice as weights of C 151 and C 152 in order to reduce the influence of the normalization of AD 92 . The output of C 153 is adjusted to be balanced with unnormalized Ao 13 and Ao 14 . $$ Ao 15 = - Ai 151 + Ai 152 + 2 ⁢ Ai 153 2 ( 7 )

Generalizing the calculation of AD 91 p, AD 91 m, AD 92 and AD 93 , Ao 14 of the output of AD 92 and Ao 15 (t) of the output of AD 93 are expressed in formulas (8) and (9), respectively, in which assuming a signal CTRL 9 for i-th S/H 9 i to be CTRL 9 (i) and its inversion to be ICTRL 9 (i). $$ Ao14 = 1 N ⁢ ∑ i = 0 N - 1 ⁢ ICTRL9 ⁡ ( i ) + 1 2 ⁢ V ⁡ ( t - i ⁢   ⁢ Δ ⁢   ⁢ t ) ( 8 ) Ao15 ⁡ ( t ) = - 1 N ⁢ { NA 0 ⁢ 14 - ∑ i = 0 N - 1 ⁢ ICTRL9 ⁡ ( i ) + 1 2 ⁢ V ⁡ ( t - i ⁢   ⁢ Δ ⁢   ⁢ t ) } ( 9 )

That is, it is the same that formula (10) is executed. $$ Ao15 ⁡ ( t ) = 1 N ⁢ ∑ i = 0 N - 1 ⁢ CTRL9 ⁡ ( i ) ⁢ V ⁡ ( t - i ⁢   ⁢ Δ ⁢   ⁢ t ) - ICTRL ⁡ ( i ) ⁢ V ⁡ ( t - i ⁢   ⁢ Δ ⁢   ⁢ t ) 2 ( 10 )

Here,

CTRL 9 (i)=1 or CTRL 9 (i)=−1,

when CTRL 9 (i)=−1, ICTRL 9 (i)=−1,

when CTRL 9 (i)=−1, ICTRL 9 (i)=1.

Switches SA 1 to SA 12 , SB 1 , SB 7 to SB 14 are for refreshing the circuit, and can cancel an offset voltage caused by a leak of electric charge or others. The switch of supply voltage SWS is for stopping supply voltage of the sampling and holding circuit etc. when possible for reducing electrical consumption. Even when the switch for refreshing is omitted, the output is usually enough accurate.

In a matched filter circuit according to the present invention, the function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition. Therefore, it is possible to use a circuit of rather low speed as an A/D converting circuit by the matched filter circuit according to the present invention. Therefore, it is profitable considering the cost, yield and electric power consumption.

Claims

1. A filter circuit for communication comprising:i) a means for addition and multiplication for a) sequentially holding an analog input signal by a plurality of a first sampling and holding circuits at a plurality of holding points, b) performing a weighted addition by PN code of said analog input signal onat each of said holding pointpoints, and c) outputting an addition result as an analog output signal, iii) a peak detecting portion for deciding a timing to take said signal according to a peak of said analog output signal; andiii) a second sampling and holding circuit for holding the analog input signal only on said timing to take said signal; andiiiv) an A/D converter for converting said analog output signal into a digital signal, comprising: a) a second sampling and holding circuit for holding a signal only on said timing to take said signal, and b) a quantizing portion for digitizing an output of said second sampling and holding circuit.

2. A filter circuit for communication as claimed in claim 1, wherein said second sampling and holding circuit comprises:i) a plurality of third sampling and holding circuits corresponding to a plurality of peaks ; ii) a plurality of switches for alternatively outputting one of outputs of said third sampling aand holding circuits or a reference voltage; and iii) a controller for controlling a holding timing of said third sampling and holding circuits and a timing of opening and closing of said switches.