Patent Application
20100277231
In many applications, rechargeable batteries are placed in series or in parallel in order to generate a desired output voltage. One such application is the use of batteries in hybrid- or fully-electric vehicles. Within these vehicles, a plurality of individual battery “cells” are arranged in order to build a battery stack having a desired output voltage. A large number of cells may be arranged in series such that, for example, the total potential difference developed across the battery stack is in the order of several hundred volts. Each cell typically only has a potential difference of a few, for example 2 to 4 volts, developed across it. Although the cells are similar, they are not identical, so repeated charging and discharging cycles may cause the voltage developed across some cells to be different than voltages developed across other cells. Ideally, the voltage across each individual cell, or at least small groups of cells, would be monitored such that the cells could be temporarily removed from a charging process if their terminal voltage gets too high or alternatively, if the cell temperature becomes unduly elevated. It is also possible to preferentially discharge cells to reduce their voltage. While it is feasible to build a single battery monitoring apparatus that can operate across the entire voltage range, for example 0 to 400 volts developed across a stack, this tends to be an expensive option.
Accordingly, there is a need for a battery monitoring system where each battery monitor can monitor the operating parameters of a single cell or a group of cells in a battery stack. Furthermore, there is a need for a method and system for communicating between each of the battery monitors and a method and system for reducing the effects of electro-magnetic corruption (EMC) on the system.
Embodiments of the present invention may include a data receiver having an input for a current signal. The data receiver may further include a current generator to generate a reference current for comparison against an input current signal. The data receiver may also include a data converter having an input coupled to an intermediate node of the data receiver, the data converter comprising a plurality of cascaded stages with intermediate nodes among the stages and a capacitive device coupled to at least one intermediate node among the stages. The data receiver may provide improved responses because it may drive a generated current into a received current before the received current enters the data conversion stages. The data receiver may limit responses of the data converter to current glitches because a capacitive device may be coupled on the current path at the output of at least one of the data conversion stages. The data receiver can further provide improved glitch response through tuning the capacitive device time response. The data receiver may also provide improved responses through conversion between the current and the voltage domains. Data conversion stages can also be current limited to provide output current responses within a prescribed current range. Moreover, data conversion stages can be voltage limited to provide voltage responses within a prescribed voltage range.
Each group of battery cells may be associated with a respective battery monitoring device, 130, 132, 134, 136, 138 or 140. Each battery monitor 130-140 may determine the voltage of its respective battery cell group, and may report the voltage value to a system controller 170. The battery monitors 130-140 may be provided in a so-called ‘daisy chain’ of groups in which data to be read from any given battery monitor (say, monitor 134) may be passed serially from each battery monitor to the next (134→136→138, etc.) until it reaches a battery monitor 140 at the end of the chain. Battery monitor 140 may pass the communicated data to a system controller 170.
Since the battery stack 100 may use multiple battery monitors rather than a single monitoring apparatus to monitor the entirety of the battery stack, the potential difference spanning across each battery monitor is reduced and as a result relatively inexpensive semiconductor fabrication processes can be used to fabricate integrated circuits capable of operating with the limited potential difference existing across the subunit within the battery stack.
Each battery monitoring device 130-140 can measure a plurality of parameters, including voltage potential across each individual cell or any combination of cells of its associated cell group. Further, the devices may also measure temperature. The voltage and/or temperature may be sent as a digital word to the system controller 170. As seen, for example, in
Data can be read from battery monitors 130-140 from any position of the daisy chain and communicated to the system controller 170. Moreover, data may be transmitted from the system controller 170 to a battery monitor 130-140 at any position of the daisy chain. Thus, the system controller 170 can read or write data to any position of the daisy chain, and battery monitors at intermediate positions of the daisy chain may relay the communicated data from the source of the data to its destination.
Each battery monitoring device may have a pair of transceivers, for example transceivers 190 and 192, within battery monitoring device 138. Reliable communication between integrated circuits may be compromised by spurious electro-magnetic corruption (EMC), commonly, called “glitches” introduced between the integrated circuit. Glitches can cause a receiver to detect multiple spurious edges on data or clock inputs which causes data corruption. The data errors caused by glitches could be digitized by one of the transceivers and, if so, could be propagated throughout the remainder of a communication path as digital data. Accordingly, each transceiver may have an EMC reduction circuit to reduce or eliminate the influence of glitches in the system. Each of the transceivers 190 and 192 may include data receivers for receiving data.
The output of the comparator 220 may be transmitted to a multi-stage data converter 230. The multi-stage data converter 230 illustrated in
Since glitches typically have a shorter duration than data present on the input signal, the glitches will generally not propagate through every stage of the multi-stage data converter 230. Accordingly, even if a glitch temporarily alters the output from the comparator 220 or even a stage of the multi-stage data converter 230, the data integrity of the input signal is maintained since the glitches will not generally propagate through every stage of the multi-stage data converter 230.
Each stage may have a corresponding capacitive device (e.g., capacitor 240.i) capacitively shorting the output of each stage to a ground potential. The capacitive device (e.g., capacitor 240.i) may provide further protection against glitches. The capacitive device may be a capacitor or a plurality of transistors providing a capacitive effect. Since capacitors resist a change in voltage, even if a glitch temporarily changes the output of a stage, the glitch in the output of the stage may not propagate to a next stage since the capacitive device will resist the change. Furthermore, the capacitors can be used to lengthen the propagation delay for certain types of logic gates. Optionally, a fuse (not shown) may be placed between the capacitive device and an intermediate node to provide for protection against large current spikes.
The data receiver 300 may further include a first stage 320 as part of a multi-stage data converter. Stage 320 may include an inverter 322. Optionally, the stage 320 may also include capacitor C1 connected from the output of the inverter 322 to ground or a reference potential VSS. The input of the inverter may be connected to the output of a comparator, for example, node N1.
The data receiver 300 may include a second stage 330 as a stage of the multi-stage data converter. Second stage 330 may include a first pair of transistors 332 and 334 arranged as an inverter. Transistor 332 may be a p-channel MOSFET and transistor 334 may be an n-channel MOSFET. Transistors 332 and 334 may be biased transistors. A drain of transistor 332 may be connected to a source of transistor 334. The gates of transistors 332 and 334 may be connected to the output of first stage 320. The second stage 330 may include a second pair of transistors 336 and 338 formed to limit current through transistors 332 and 334, respectively. The source terminal of transistor 336 may be connected to a drain of transistor 332. A drain terminal of transistor 336 may be connected to the reference voltage VDD. The drain terminal of transistor 338 may be connected to a source terminal of transistor 334, while a source terminal of transistor 338 may be connected to ground or a reference voltage VSS. Optionally, the stage 330 may also include capacitor C2 connected from the output of the inverter (transistors 332 and 334) to ground.
The data receiver 300 may include a third stage 340 as a stage of the multi-stage data converter. The stage 340 may include a Schmitt triggered buffer 342. Optionally, the stage 340 may also include capacitor C3 connected from the output of the Schmitt triggered buffer 342 to ground at a node N3.
Operationally, the data receiver 300 may receive an input signal IIN corresponding to a data signal, which may have been subject to EMC. The input signal IIN may be received by the comparator 310 via input 305 at a source terminal of transistor 314. The comparator 310 may compare the input current IIN to a reference current IREF. As discussed above, when the information signal represented by IIN is in a first state, a resultant current (IREF) may flow in a first direction (e.g., from input 305 to reference voltage VDD), and when the information signal is in a second state IREF may flow in an opposite direction (e.g., reference voltage VDD to the input pin). This resultant current may induce a corresponding voltage at node N1, which may be the input to stage 320 of the data receiver 300.
The voltage output by the comparator 310 is received at the input to inverter 322. The inverter 322 may inherently have a propagation delay at its output, so while transition occurs at the input to the inverter (either high to low or low to high) the change may be delayed at the output. The inverter 310 can be designed to have a longer or shorter propagation delay depending upon the amount of EMC the circuit may be expected to experience. The propagation delay may be increased by adding a capacitor, for example capacitor C1, between the output of the inverter 322 and ground or a reference potential VSS. The propagation delay can be lengthened by increasing the size of the capacitor C1. The propagation delay can also be lengthened by decreasing a power supply voltage VDD supplied to the inverter 322 by adding a resistor in the power supply path, a lower process transconductance parameter can be used, and/or a width/length ratio of the transistors can be decreased.
The output of first stage 320 may be transmitted to the input of transistors 332 and 334 in second stage 330, which are arranged as an inverter. Transistors 336 and 338 may be used to limit current of transistors 332 and 334, respectively. The bias potentials PBIAS2 and NBIAS2 may be individually, or in tandem, set to control the amount of current that may respectively passed by each of transistors 336 and 338, respectively. By limiting the current, a resultant potential across the inverter of second stage 330 may also be limited, and so discussed above, the propagation delay may be increased (i.e., by lowering a power supply voltage and/or raising the lower potential VSS to a non-zero value). Accordingly, the inverter represented in second stage 330 may be designed to have a longer propagation delay than the inverter 322 in second stage 330. Thus, a glitch which may have persisted long enough to change the output of first stage 320 may not persist long enough to change the output of the inverter in second stage 330. While only two inverters are illustrated in the data receiver 300 illustrated in
The output of the inverter arranged in second stage 330 may be output to a Schmitt triggered buffer 342 in third stage 340. If an odd number of inverter stages are used previously in the chain, an inverting Schmitt trigger could be used. Schmitt triggers are designed to have a persistent output. When the input to the Schmitt trigger is higher than a certain chosen threshold, the output is transitioned high. When the input is below another (lower) chosen threshold, the output is transitioned low. However, when the input is between the two, the output retains its current value. So, even if a glitch that obscures a signal transition persisted long enough to pass through the inverters in first stage 320 and second stage 330, the input to the Schmitt trigger would have to rise above the upper threshold or fall below the lower threshold before the output to the Schmitt trigger will change its output value. Accordingly, the EMC of the input signal is effectively removed from the input signal prior to further signal processing.
Exemplary input signal B illustrates an input signal with a small glitch GS. As seen in
Exemplary input signal C illustrates an input signal with a larger glitch GM. As seen in
Exemplary input signal D illustrates an input signal with an even larger glitch GL. As seen in
The reference current IREF output from the reference current generator 420 and the output current IOUT may both be fed into the input terminal of inverter 430. The bias current IBIAS may be selected such that when the data represented by the input signal IIN is in a first state a positive voltage is present at the input to the inverter and when the data represented by the input signal IIN is in a second state a negative voltage is present at the input to the inverter.
The output of inverter 430 may be fed into an input terminal of an inverter 450. The inverter 450 may include transistors 454 and 456. The transistor 454 and 456 may be arranged as an inverter. The inverter 450 may further include biasing transistors 452 and 458 which can bias a potential across the inverter to either lengthen or reduce the propagation delay of the inverter. The gate terminals of transistors 452 and 456 may be controlled by the output of a voltage bias generator 440.
The voltage bias generator 440 may include transistors 442, 444, 446, 448 arranged to form a current mirror. The source terminal of transistors 442 and 444 may be connected to reference voltage VDD. The gate terminal of transistor 442 may be connected to the gate terminal and the drain of transistor 424 in the reference current generator 420. The drain of the 442 transistor may be connected to the drain and gate of the transistor 446, which is arranged as a current mirror with transistor 448. The drain and the gate of transistor 444 may be connected to the gate of biasing transistor 452 in the inverter 450. In addition, the drain and gate of transistor 444 is connected to the drain of transistor 448. The gates of both transistor 446 and transistor 448 are connected to the gate of biasing transistor 458 of the inverter 458.
In operation, transistor 442 of the voltage bias generator 440 is enabled by a reference signal from the reference current generator 420 that is applied to the gate of transistor 442. A current may flow through transistor 442. This current is mirrored through transistor 444 because of the current mirror arrangement of transistors 446 and 448. The current through transistor 444 results in a gate voltage of the transistor 444 being applied to the gate of biasing transistor 452, and similarly, the current through the transistor 448 results in a gate voltage of the transistor 448 being applied to the gate of biasing transistor 458. The voltages supplied by the voltage bias generator 440 may be proportional to the bias current IBIAS that is mirrored from the reference current IREF.
The output of inverter 450 may be connected to a capacitor network 460. The capacitor network 460 may include a capacitor 462 connecting the output of the inverter 450 to an upper potential VDD. The capacitor network 460 may further include a capacitor 464 connecting the output of the inverter 450 to a lower potential VSS. The capacitors network 460 may be tuned to control the length of propagation delay of inverter 450.
The output of inverter 450 may further be connected to the input terminal of a Schmitt triggered buffer 470. As discussed above, an upper and lower threshold may be selected for the Schmitt triggered buffer 470 which will prevent the output of the Schmitt triggered buffer 470 from changing until the output of the inverter 450 rises above or falls below the respective thresholds.
Based on the bias voltage VBIAS applied to the transistor 505, the input current signal IIN provided to the current mirroring circuit 510 may be limited, which may also limit the effect of any glitches in the input current signal IIN. The amplifying current mirroring circuit 510 may include two pairs of transistors 512, 514 and 516 and 518 arranged as current mirrors. Transistors 512 and 514 may be arranged as a first current mirror, and transistors 516 and 518 may be arranged as a second current mirror. The current mirroring circuit 510 provides an amplified current signal IAMP that is input into the current mirror 520. The operation of the current mirror 520 is similar to the current mirror 410 of
The capacitance module 570 may provide yet another stage for introducing a propagation delay into the input circuit to further mitigate any errors that may be caused by glitches present on the input signal passed by the previous stages 510-560.
Similar as those described in conjunction with
Several embodiments of the invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.
This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 61/174,710, filed May 1, 2009 and entitled “Improved Filtering On Current Mode Daisy Chain Inputs,” which is herein incorporated by reference in its entirety. This disclosure is related to U.S. patent application Ser. No. 12/011,615, filed Jan. 28, 2008 and published Jul. 31, 2008 as U.S. publication No. 2008/0180106 (the '615 application), which is assigned to Analog Devices, Inc., the assignee of the present disclosure. The '615 application is incorporated into the present disclosure in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61174710 | May 2009 | US |
