The present disclosure relates to the technical field of fingerprint identification, and particularly relates to a fingerprint identification driving circuit, a fingerprint identification circuit, and a driving method for the fingerprint identification circuit.
In the related art, a photosensitive device may be used to converse light of different intensities to a photocurrent of different magnitudes. In this case, due to the difference between a fingerprint valley and a fingerprint ridge, reflected light of different intensities may be generated when light from a light source is irradiated on a finger, such that different photocurrents may be generated and then a fingerprint pattern may be acquired. Specifically, as shown in
However, in the related art, the method for acquiring a fingerprint pattern under strong light has the problems of long fingerprint detection time, slow response, and the like.
Some embodiments of the present disclosure provide a fingerprint identification driving circuit, a fingerprint identification circuit, and a driving method for the fingerprint identification circuit.
In a first aspect, the embodiments of the present disclosure provide a fingerprint identification driving circuit including a shift register sub-circuit and an output sub-circuit, wherein the output sub-circuit is configured to transmit a signal input from a first clock signal terminal to a scan signal output terminal of the output sub-circuit for outputting, in response to a signal input from a driving signal output terminal of the shift register sub-circuit: and the output sub-circuit is further configured to transmit a signal input from a first voltage signal terminal to the scan signal output terminal of the output sub-circuit for outputting, in response to a signal of a first node inside the shift register sub-circuit.
Optionally, the shift register sub-circuit includes an input sub-circuit, a reset sub-circuit, and an output control sub-circuit: the input sub-circuit is configured to transmit a signal input from an input signal terminal to a second node in response to a signal input from a second clock signal terminal: the reset sub-circuit is configured to transmit a signal input from a second voltage signal terminal to the first node in response to the signal input from the second clock signal terminal: the output control sub-circuit is configured to transmit a signal input from a third clock signal terminal to the driving signal output terminal in response to a signal of the second node, and is configured to transmit the signal input from the first voltage signal terminal to the driving signal output terminal in response to a signal of the first node: the second node is a connection node between the input sub-circuit and the output control sub-circuit: and the first node is a connection node between the reset sub-circuit and the output control sub-circuit.
Optionally, the input sub-circuit includes: a first transistor having a first electrode connected to the input signal terminal, a second electrode connected to the second node, and a control electrode connected to the second clock signal terminal.
Optionally, the reset sub-circuit includes: a second transistor having a first electrode connected to the second voltage signal terminal, a second electrode connected to the first node, and a control electrode connected to the second clock signal terminal.
Optionally, the output control sub-circuit includes a third transistor, a fourth transistor, a first capacitor, and a second capacitor: a first electrode of the third transistor is connected to the third clock signal terminal, a second electrode of the third transistor is connected to the driving signal output terminal, and a control electrode of the third transistor is connected to the second node: one terminal of the first capacitor is electrically connected to the control electrode of the third transistor, and the other terminal of the first capacitor is connected to the second electrode of the third transistor: a first electrode of the fourth transistor is connected to the driving signal output terminal, a second electrode of the fourth transistor is connected to the first voltage signal terminal, and a control electrode of the fourth transistor is connected to the first node: and one terminal of the second capacitor is electrically connected to the control electrode of the fourth transistor, and the other terminal of the second capacitor is connected to the second electrode of the fourth transistor.
Optionally, the output sub-circuit includes a fifth transistor and a sixth transistor: a first electrode of the fifth transistor is connected to the first clock signal terminal, a second electrode of the fifth transistor is connected to the scan signal output terminal, and a control electrode of the fifth transistor is connected to the driving signal output terminal: and a first electrode of the sixth transistor is connected to the first voltage signal terminal, a second electrode of the sixth transistor is connected to the scan signal output terminal, and a control electrode of the sixth transistor is connected to the first node.
Optionally, the fingerprinting identification driving circuit further includes a first control sub-circuit configured to transmit a signal of a second clock signal terminal to the first node in response to a signal of a second node.
Optionally, the first control sub-circuit includes: a seventh transistor having a first electrode connected to the first node, a second electrode connected to the second clock signal terminal, and a control electrode connected to the second node.
Optionally, the fingerprinting identification driving circuit further includes a second control sub-circuit configured to transmit a signal output from the first voltage signal terminal to a second node in response to a signal transmitted from a third clock signal terminal and a signal transmitted from the first node.
Optionally, the second control sub-circuit includes an eighth transistor and a ninth transistor: a first electrode of the eighth transistor is connected to a second electrode of the ninth transistor, and a second electrode of the eighth transistor is connected to the second node: a control electrode of the eighth transistor is connected to the third clock signal terminal: a first electrode of the ninth transistor is connected to the first voltage signal terminal, and a control electrode of the ninth transistor is connected to the first node.
In a second aspect, the embodiments of the present disclosure provide a fingerprint identification circuit including: the above fingerprint identification driving circuits, m driving signal lines and n reading signal lines crossing over the m driving signal lines, and photosensitive units arranged in an array of m×n, wherein the photosensitive units in a same row are connected to a same driving signal line, and the photosensitive units in a same column are connected to a same reading signal line: the driving signal output terminal of an N-th stage fingerprint identification driving circuit is connected to an input sub-circuit of an (N+1)-th stage fingerprint identification driving circuit: and the scan signal output terminal of the N-th stage fingerprint identification driving circuit is connected to an m-th driving signal line, where N=m, and N, n and m are positive integers.
In a third aspect, the embodiments of the present disclosure provide a driving method for driving the above fingerprint recognition circuit, including: outputting, from the driving signal output terminal of an N-th stage shift register sub-circuit, a turn-on level signal to control starting of the output sub-circuit, wherein a signal of the first clock signal terminal is transmitted to the m-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, such that a reset operation and a reading operation are performed on the photosensitive units based on a signal input from the m-th driving signal line: after completion of the reset operation and the reading operation on the photosensitive units connected to the m-th driving signal line, outputting, from the driving signal output terminal of the N-th stage shift register sub-circuit, a turn-on level signal to the input sub-circuit of an (N+1)-th stage shift register sub-circuit for starting the (N+1)-th stage fingerprint identification driving circuit: and then, outputting, at the driving signal output terminal of the (N+1)-th stage shift register sub-circuit, a turn-on level signal to control the starting of the output sub-circuit in a same stage, wherein the signal of the first clock signal terminal is output to an (m+1)-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, such that a reset operation and a reading operation are performed on the photosensitive units based on a signal input from the (m+1)-th driving signal line.
In a fourth third aspect, the embodiments of the present disclosure provide a driving method for driving the above fingerprint recognition circuit, including: outputting, from the driving signal output terminal of an N-th stage shift register sub-circuit, a turn-on level signal to control starting of the output sub-circuit, wherein a signal of the first clock signal terminal is transmitted to the m-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, such that a reset operation and a reading operation are performed on the photosensitive units based on a signal input from the m-th driving signal line: after completion of the reset operation on the photosensitive units connected to the m-th driving signal line, outputting, from the driving signal output terminal of the N-th stage shift register sub-circuit, a turn-on level signal to the input sub-circuit of an (N+1)-th stage shift register sub-circuit for starting the (N+1)-th stage fingerprint identification driving circuit: and then, outputting, from the driving signal output terminal of the (N+1)-th stage shift register sub-circuit, a turn-on level signal to control the starting of the output sub-circuit in a same stage, wherein the signal of the first clock signal terminal is output to an (m+1)-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, such that a reset operation is performed on the photosensitive units based on a signal input from the (m+1)-th driving signal line: after completion of the reset operation on all the rows of photosensitive units, outputting, from the driving signal output terminal of the N-th stage shift register sub-circuit, a turn-on level signal to control the starting of the output sub-circuit, wherein the signal of the first clock signal terminal is transmitted to the m-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, such that a reading operation is performed on the photosensitive units based on a signal input from the (m)-th driving signal line:
and after completion of the reading operation on the photosensitive units connected to the m-th driving signal line, outputting, from the driving signal output terminal of the N-th stage shift register sub-circuit, a turn-on level signal to the input sub-circuit of the (N+1)-th stage shift register sub-circuit for starting the (N+1)-th stage fingerprint identification driving circuit: and then, outputting, from the driving signal output terminal of the (N+1)-th stage shift register sub-circuit, a turn-on level signal to control the starting of the output sub-circuit in a same stage, wherein the signal of the first clock signal terminal is output to the (m+1)-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, such that a reading operation is performed on the photosensitive units based on a signal input from the (m+1)-th driving signal line until completion of the reading operation on all the rows of photosensitive units.
In order to make one of ordinary skill in the art better understand the technical solutions of the present disclosure, the following detailed description is given with reference to the drawings and the specific embodiments.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The words “first,” “second,” and the like in present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. Similarly, the word “a,” “an,” “the,” or the like does not denote a limitation of quantity, but rather denotes the presence of at least one element. The word “comprising,” “including,” or the like, means that the element or item preceding the word contains the element or item listed after the word and its equivalent, but does not exclude other elements or items. The word “connected,” “coupled,” or the like is not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect connections. The words “upper,” “lower,” “left,” “right,” and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It should be noted that, the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source electrode and the drain electrode of each transistor used are symmetrical, the source electrode and the drain electrode are not different from each other. In the embodiments of the present disclosure, to distinguish the source electrode and the drain electrode of each transistor from each other, one of the source electrode and the drain electrode is referred to as a first electrode, the other of the source electrode and the drain electrode is referred to as a second electrode, and the gate electrode thereof is referred to as a control electrode. In addition, the transistors may be classified as N-type transistors and P-type transistors based on the characteristics of the transistors, and in the following embodiments, a P-type transistor is taken as an example for description. When a P-type transistor is used, the first electrode is a source electrode of the P-type transistor, and the second electrode is a drain electrode of the P-type transistor. When a low level is input to the gate electrode of the P-type transistor, the source electrode and the drain electrode of the P-type transistor are electrically connected with each other, and the N-type transistor is turned-on by a high level at the gate electrode thereof opposite to the low level at the gate electrode of the P-type transistor. It is conceivable that the implementation of the present inventive concept by using N-type transistors can be easily carried out by one of ordinary skill in the art without creative work, and therefore also falls within the protection scope of the embodiments of the present disclosure.
In the embodiment of the present disclosure, since each transistor used is a P-type transistor, the turn-on level signal in the embodiment of the present disclosure refers to a low level signal, and the turn-off level signal refers to a high level signal: and correspondingly the turn-on level terminal is a low level signal terminal, and the turn-off level terminal is a high level signal terminal. The first power supply voltage supplied to the first power supply voltage terminal is higher than the second power supply voltage supplied to the second power supply voltage terminal. In the embodiments of the present disclosure, the case where the first power supply voltage is a high power supply voltage and the second power supply voltage is a low power supply voltage is taken as an example.
Continuing to refer to
In order to solve at least one of the above technical problems, a fingerprint identification driving circuit, a fingerprint identification circuit, and a driving method for a fingerprint identification circuit are provided in the embodiments of the present disclosure. The fingerprint identification driving circuit, the fingerprint identification circuit, and the driving method for the fingerprint identification circuit in the embodiments of the present disclosure will be described in further detail below with reference to the drawings and specific embodiments.
In a first aspect,
Specifically, the output sub-circuit 2 is configured to transmit a signal input from a first clock signal terminal CLK1 to a scan signal output terminal Sensor out of the output sub-circuit 2 for outputting, in response to a signal input from a driving signal output terminal Gout of the shift register sub-circuit 1. The output sub-circuit 2 is further configured to transmit a signal input from a first voltage signal terminal VGH to the scan signal output terminal Sensor out of the output sub-circuit 2 for outputting, in response to a signal of a first node N1 inside the shift register sub-circuit 1.
In the present embodiment, a scan line switching signal is provided at the driving signal output terminal Gout of the shift register sub-circuit 1, and a driving signal for one row of photosensitive units 01 is provided by the output sub-circuit 2, so that the timing sequence of respective driving signals may be adjusted based on different application scenarios. That is, an adjustable integration time can be realized, such that the photosensitive units 01 are not saturated under strong light, and the speed of fingerprint identification is increased.
In some embodiments,
The input sub-circuit 11 is configured to transmit a signal input from an input signal terminal Vin to a second node N2 in response to a signal input from a second clock signal terminal CLK2. The reset sub-circuit 12 is configured to transmit a signal input from a second voltage signal terminal VGL to the first node N1 in response to the signal input from the second clock signal terminal CLK2. The output control sub-circuit 13 is configured to transmit a signal input from a third clock signal terminal CLK3 to the driving signal output terminal Gout in response to a signal of the second node N2, and the output control sub-circuit 13 is configured to transmit a signal input from the first voltage signal terminal VGH to the driving signal output terminal Gout in response to the signal of the first node N1. The second node N2 is a connection node between the input sub-circuit 11 and the output control sub-circuit 13, and the first node N1 is a connection node between the reset sub-circuit 12 and the output control sub-circuit 13.
In the present embodiment, a scan line switching signal is provided at the driving signal output terminal Gout of the shift register sub-circuit 1, and a driving signal for one row of photosensitive units 01 is provided by the output sub-circuit 2, so that the timing sequence of respective driving signals can be adjusted according to different application scenarios, that is, the adjustable integration time can be realized. As such, the photosensitive units 01 are not saturated under strong light, and the speed of fingerprint identification is increased.
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In the present embodiment, the stability of the output signal of the fingerprint identification driving circuit can be enhanced by providing the first control sub-circuit 14 and the second control sub-circuit 15.
In order to make the structure of the fingerprint identification driving circuit in the embodiment of the present invention clearer, the structure and the operation process of the embodiment of the present invention are described in connection with the following specific examples.
As shown in
Specifically, the first electrode of the first transistor M1 is connected to the input signal terminal Vin, the second electrode of the first transistor M1 is connected to the second node N2, and the control electrode of the first transistor M1 is connected to the second clock signal terminal CLK2. The first electrode of the second transistor M2 is connected to the second voltage signal terminal VGL, the second electrode of the second transistor M2 is connected to the first node N1, and the control electrode of the second transistor M2 is connected to the second clock signal terminal CLK2. The first electrode of the third transistor M3 is connected to the third clock signal terminal CLK3, the second electrode of the third transistor M3 is connected to the driving signal output terminal Gout, and the control electrode of the third transistor M3 is connected to the second node N2. One terminal of the first capacitor C1 is electrically connected to the control electrode of the third transistor M3, and the other terminal of the first capacitor C1 is connected to the second electrode of the third transistor M3. The first electrode of the fourth transistor M4 is connected to the driving signal output terminal Gout, the second electrode of the fourth transistor M4 is connected to the first voltage signal terminal VGH, and the control electrode of the fourth transistor M4 is connected to the first node N1. One terminal of the second capacitor C2 is electrically connected to the control electrode of the fourth transistor M4, and the other terminal of the second capacitor C2 is connected to the second electrode of the fourth transistor M4. The first electrode of the fifth transistor M5 is connected to the first clock signal terminal CLK1, the second electrode of the fifth transistor M5 is connected to the scan signal output terminal Sensor out, and the control electrode of the fifth transistor M5 is connected to the driving signal output terminal Gout. The first electrode of the sixth transistor M6 is connected to the first voltage signal terminal VGH, the second electrode of the sixth transistor M6 is connected to the scan signal output terminal Sensor out, and the control electrode of the sixth transistor M6 is connected to the first node N1. The first electrode of the seventh transistor M7 is connected to the first node N1, the second electrode of the seventh transistor M7 is connected to the second clock signal terminal CLK2, and the control electrode of the seventh transistor M7 is connected to the second node N2. The first electrode of the eighth transistor M8 is connected to the second electrode of the ninth transistor M9, and the second electrode of the eighth transistor M8 is connected to the second node N2. The control electrode of the eighth transistor M8 is connected to the third clock signal terminal CLK3. The first electrode of the ninth transistor M9 is connected to the first voltage signal terminal VGH, and the control electrode of the ninth transistor M9 is connected to the first node N1.
In a first stage (t1), a low level signal is input from the input signal terminal Vin, a low level signal is input from the second clock signal terminal CLK2, a high level signal is input from the third clock signal terminal CLK3, and a high level signal is input from the first clock signal terminal CLK1. As shown in
In the second stage (t2), a high level signal is input from the input signal terminal Vin, a high level signal is input from the second clock signal terminal CLK2, a high level signal is input from the third clock signal terminal CLK3, and a high level signal is input from the first clock signal terminal CLK1. As shown in
In a third stage (t3), a high level signal is input from the input signal terminal Vin, a high level signal is input from the second clock signal terminal CLK2, a low level signal is input from the third clock signal terminal CLK3, and a fingerprint scan signal is input from the first clock signal terminal CLK1. As shown in
In a fourth stage (t4), a high level signal is input from the input signal terminal Vin, a high level signal is input from the second clock signal terminal CLK2, a high level signal is input from the third clock signal terminal CLK3, and a high level signal is input from the first clock signal terminal CLK1. As shown in
In the present embodiment, the signal output from the scan signal output terminal Sensor out is controlled by the signal input from the third clock signal terminal CLK3, and thus the timing sequence of the fingerprint scan signal input from the third clock signal terminal CLK3 can be adjusted according to different application scenarios, that is, the integration (or integral) time can be adjusted, so that each photoreceptive unit is not saturated under strong light, and the speed of fingerprint identification is increased.
It should be noted that, in the present embodiment, the shift register sub-circuit 1 is described by taking the circuit of 7T2C (i.e., 7 transistors and 2 capacitors) as an example, but the present disclosure is not limited thereto. It is to be understood that, other types of shift register sub-circuits 1 may be selected by one of ordinary skill in the art, for example, each shift register sub-circuit 1 may alternatively have a structure of 9T2C, and therefore, embodiments using different types of shift register sub-circuits are within the scope of the present disclosure.
In a second aspect,
With continued reference to
In the present embodiment, referring to
In a third aspect,
At step S101, a turn-on level signal is output from the driving signal output terminal of the N-th stage shift register sub-circuit to control the starting (i.e., turning on or turning-on) of the output sub-circuit, and the signal of the first clock signal terminal is transmitted to the m-th driving signal line connected to the scan signal output terminal through the started (i.e., turned-on) output sub-circuit, so that a reset operation and a reading operation are performed on the photosensitive units based on a signal input from the m-th driving signal line.
At step S102, after the completion of the reset operation and the reading operation on the photosensitive units connected to the m-th driving signal line, a turn-on level signal for starting the (N+1)-th stage fingerprint identification driving circuit is output from the driving signal output terminal of the N-th stage shift register sub-circuit to the input sub-circuit of the (N+1)-th stage shift register sub-circuit.
At step S103, a turn-on level signal for starting the output sub-circuit in the same stage is output from the driving signal output terminal of the (N+1)-th stage shift register sub-circuit, and the signal of the first clock signal terminal is output to the (m+1)-th driving signal line connected to the scan signal output terminal, so that a reset operation and a reading operation are performed on the photosensitive units based on a signal input from the (m+1)-th driving signal line.
Illustratively, as shown in
Then, after the completion of the reset (Reset) operation and the reading (Read) operation on the photosensitive units 01 connected to the first driving signal line G1, a turn-on level signal is output from the driving signal output terminal Gout1 of the first stage shift register sub-circuit to the input sub-circuit 11 of the second stage shift register sub-circuit, to start (i.e., to turn on) the second stage fingerprint identification driving circuit. Then, a turn-on level signal for controlling the starting of the output sub-circuit 2 in the same stage is output from the driving signal output terminal Gout2 of the second stage shift register sub-circuit, and then the signal of the first clock signal terminal CLK1 is output to the second driving signal line G2 connected to the scan signal output terminal Sensor out2, so that a reset (Reset) operation and a reading (Read) operation are performed on the photoreceptive units 01 based on the signal input from the second driving signal line G2.
The time duration of the integration (i.e., Integral) stage can be determined by any one of the following two methods.
In the first method, during the scanning operation of the sensors, N integration time durations, such as T1, T2, T3, . . . , and TN, have been preset inside the system, and represent different integration times from small to large. Each of the integration times is in a one-to-one correspondence with an ambient light intensity. There are N grades for the ambient light from the minimum Dark state to the maximum 10 W luxes (i.e., the maximum intensity of the ambient light is assumed to be 10 W 1×), and then the N grades of the integration times are T1 to TN.
A second method is shown in
In the present embodiment, it is assumed that the time for completing the reset scanning of N rows of sensors is TO, which is a value between the preset integration time durations T1 and TN of the system. In the fingerprint scanning process, after a required integration time duration is determined as T, which is a value between the preset integration time durations T1 and TN of the system. If the determined integration time T is less than the time TO for completing the reset scanning of the N rows of sensors, in the fingerprint identification circuit according to the embodiment of the present disclosure, the operations of the reset scanning, the sensor integration, and the sensor reading scanning, on the first row of sensors, on the second row of sensors, and so on, are sequentially implemented until completing the fingerprint scanning of the N rows of sensors.
In the present embodiment, since the signal output from the scan signal output terminal Sensor out is controlled by the signal output from the third clock signal terminal CLK3, the timing sequence of the fingerprint identification signal output from the third clock signal terminal CLK3 can be adjusted based on different application scenarios, i.e., the integration time can be adjusted, so that each sensor is not saturated under strong light, and the speed of fingerprint identification is increased.
In a fourth aspect,
At step S401, a turn-on level signal for controlling the starting of the output sub-circuit is output from the driving signal output terminal of the N-th stage shift register sub-circuit, and the signal of the first clock signal terminal is transmitted to the m-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reset operation is performed on the photosensitive units based on the signal input from the m-th driving signal line.
At step S402, after the completion of the reset operation on the photosensitive units connected to the m-th driving signal line, a turn-on level signal is output from the driving signal output terminal of the N-th stage shift register sub-circuit (which may also me referred to as an N-th stage driving signal output terminal) to the input sub-circuit of the (N+1)-th stage shift register sub-circuit for starting the (N+1)-th stage fingerprint identification driving circuit.
At step S403, a turn-on level signal for controlling the starting of the output sub-circuit in the same stage is output from the driving signal output terminal of the (N+1)-th stage shift register sub-circuit, and the signal of the first clock signal terminal is transmitted to (or output to) the (m+1)-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reset operation is performed on the photosensitive units based on the signal input from the (m+1)-th driving signal line.
At step S404, after the completion of the reset operation on all the rows of photosensitive units, a turn-on level signal is output from the driving signal output terminal of the N-th stage shift register sub-circuit to control the starting of the output sub-circuit, and the signal of the first clock signal terminal is transmitted to the m-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reading operation is performed on the photosensitive units based on the signal input from the m-th driving signal line.
At step S405, after the completion of the reading operation on the photosensitive units connected to the m-th driving signal line, a turn-on level signal is output from the driving signal output terminal of the N-th stage shift register sub-circuit to the input sub-circuit of the (N+1)-th stage shift register sub-circuit for starting the (N+1)-th stage fingerprint identification driving circuit.
At step S406, a turn-on level signal is output from the driving signal output terminal of the (N+1)-th stage shift register sub-circuit to control the starting of the output sub-circuit in the same stage, and the signal of the first clock signal terminal is output to the (m+1)-th driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reading operation is performed on the photosensitive units based on the signal input from the (m+1)-th driving signal line until the reading operation is completed on all the rows of photosensitive units.
Illustratively, as shown in
After the completion of the reset operation on the photosensitive units connected to the first driving signal line, a turn-on level signal is output from the driving signal output terminal of the first stage shift register sub-circuit (which may also be referred to as the first stage driving signal output terminal) to the input sub-circuit of the second stage shift register sub-circuit to start the second stage fingerprint identification driving circuit. And then, a turn-on level signal is output from the driving signal output terminal of the second stage shift register sub-circuit to control the starting of the output sub-circuit in the same stage, and the signal of the first clock signal terminal is output to the second driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reset operation is performed on the photosensitive units based on the signal input from the second driving signal line.
After the completion of the reset operation on all the rows of photosensitive units, a turn-on level signal is output from the driving signal output terminal of the first stage shift register sub-circuit to control the starting of the output sub-circuit, and the signal of the first clock signal terminal is transmitted to the first driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reading operation is performed on the photosensitive units based on the signal input from the first driving signal line.
After the completion of the reset operation on the photosensitive units connected to the first driving signal line, a turn-on level signal is output from the first stage driving signal output terminal to the input sub-circuit of the second stage shift register sub-circuit to start the second stage fingerprint identification driving circuit. And then, a turn-on level signal is output from the driving signal output terminal of the second stage shift register sub-circuit to control the starting of the output sub-circuit in the same stage, and the signal of the first clock signal terminal is output to the second driving signal line connected to the scan signal output terminal through the started output sub-circuit, so that the reading operation is performed on the photosensitive units based on the signal input from the second driving signal line until the completion of the reading operation on all the rows of photosensitive units.
In the present embodiment, it is assumed that the time for completing the reset scanning of the N rows of sensors is TO, which is a value between the preset integration time durations T1 and TN of the system. In the fingerprint scanning process, after the integration time duration is determined based on the above integration time determination method as T, which is a certain value between the preset integration time durations T1 and TN of the system. If the determined integration time T is greater than or equal to the time TO for completing the reset scanning of the N rows of sensors, the following is performed sequentially for completing the fingerprint scanning of the N rows of sensors: the reset scanning of the sensors row-by-row, and then the reading scanning of the sensors row-by-row after a certain time duration has passed since the reset scanning.
In the present embodiment, since the signal output from the scan signal output terminal Sensor out is controlled by the signal output from the third clock signal terminal CLK3, the timing sequence of the fingerprint identification signal output from the third clock signal terminal CLK3 can be adjusted based on different application scenarios, that is, the integration time can be adjusted, so that each sensor is not saturated under strong light, and the speed of fingerprint identification is increased.
It will be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and essence of the present disclosure, and these changes and modifications are to be considered within the scope of the present disclosure.
This is a National Phase Application filed under 35 U.S.C. 371 as a national stage of PCT/CN2021/114790 filed on Aug. 26, 2021, the content of which is incorporated herein by reference in its entirety.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2021/114790 | 8/26/2021 | WO |