Claims
- 1. FIRDAC (20) comprising at least one current output (23; 24) and a plurality of FIRDAC cells (40), each cell (40) comprising:a shift register cell (60); at least one current source (50; 70) controlled by the corresponding shift register cell (60) for coupling a FIRDAC cell current contribution (IPi; INi)to said at least one current output (23; 24); the FIRDAC (20) further comprising a compensation current source (Ncomp; Pcomp) coupled to said current output (23; 24).
- 2. FIRDAC according to claim 1, wherein said at least one current source (50) is arranged for generating a positive current contribution (IPi) to said at least one current output (23), and wherein said compensation current source (Ncomp) is arranged for generating a predetermined, fixed amount of negative current.
- 3. FIRDAC according to claim 1, wherein said at least one current source (70) is arranged for generating a negative current contribution (INi) to said at least one current output (24), and wherein said compensation current source (Pcomp) is arranged for generating a predetermined, fixed amount of positive current.
- 4. FIRDAC according to claim 2 or 3, wherein said at least one current source (50; 70) comprises a transistor of a first conductivity type (PMOS; NMOS) coupled between said at least one current output (23; 24) and a first supply line (VDD; VSS), and wherein said compensation current source (Ncomp; Pcomp) comprises a transistor of a second conductivity type (NMOS; PMOS) coupled between said at least one current output (23; 24) and a second supply line (VSS; VDD).
- 5. FIRDAC according to claim 1, wherein said at least one current source (50) is arranged for generating a positive current contribution (IPi) to said at least one current output (23), and wherein said compensation current source is arranged for generating a pre-determined, fixed amount of positive current.
- 6. FIRDAC according to claim 1, wherein said at least one current source (70) is arranged for generating a negative current contribution (INi) to said at least one current output (24), and wherein said compensation current source is arranged for generating a pre-determined, fixed amount of negative current.
- 7. FIRDAC according to claim 5 or 6, wherein said at least one current source (50; 70) comprises a transistor of a first conductivity type (PMOS; NMOS) coupled between said at least one current output (23; 24) and a supply line (VDD; VSS), and wherein said compensation current source comprises a transistor of the same conductivity type coupled between said at least one current output (23; 24) and said supply line (VSS; VDD).
- 8. FIRDAC according to any of claims 1-7, wherein said compensation current source (Ncomp; Pcomp) is implemented as a parallel combination of a plurality of transistors (90; 80).
Priority Claims (1)
Number |
Date |
Country |
Kind |
99203989 |
Nov 1999 |
EP |
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CROSS REFERENCE TO RELATED APPLICATION
This is a continuation Ser. No. 09/722,832 filed Nov. 27, 2000 now U.S. Pat. No. 6,424,278.
US Referenced Citations (6)
Continuations (1)
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09/722832 |
Nov 2000 |
US |
Child |
10/156411 |
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