This application claims priority from Korean Patent Application No. 10-2008-0061566, filed on Jun. 27, 2008, the disclosure of which is incorporated herein in its entirety by reference.
The present invention relates to a finite impulse response (FIR) filter, and more particularly, to a finite impulse response (FIR) filter without decimation.
A finite impulse response (FIR) filter performs filtering using only input signal values. An impulse response which is the characteristic function of such a FIR filter has a finite length. FIR filters have been widely utilized in various digital devices, particularly, for the purpose of varying the phase of an input signal without changing the waveform of the input signal.
A conventional FIR filter filters an input signal using a moving average characteristic. Upon filtering, the conventional FIR filter operates based on a moving average formula, with a difference between an input sampling rate and an output sampling rate, and accordingly decimation occurs inevitably.
For example, when an input sampling rate of a FIR filter is 1 sample every 1 period, if during 4 periods, that is, while 4 samples are received, a single output is generated, a decimation value of the FIR filter will become 4. In other words, decimation is the characteristic of a filter occurring when an input sampling rate is different from an output sampling rate. The magnitude of decimation is determined by a system specification considering a sampling frequency which can be processed by a sampler, a sampling frequency which can be processed by an analog-to-digital converter (ADC), etc.
Meanwhile, in regard to a discrete-time receiver system, recently, demands for a FIR filter which can be applied to a broadband system and for techniques for improving attenuation of a FIR filter are increasing.
A simplest method for satisfying the demands is to connect a plurality of FIR filters in a cascade structure. However, in the case of connecting conventional FIR filters in series, there is a problem that additional decimation is generated due to different sample rates between input and output signals.
The present invention provides a finite impulse response (FIR) filter without decimation.
According to an aspect of the present disclosure, there is provided a finite impulse response (FIR) filter that may include: a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample, wherein each sub block has a state among N charging states for storing the received sample, a transfer state for outputting the stored sample, and a reset state for operation initialization, and the N charging states, the transfer state, and the reset state are changed sequentially in response to the clock signals.
Each clock signal may be used to control a charging state of a first sub block among the N+2 sub blocks, a reset state of a second sub block among the N+2 sub blocks, and a transfer state of a third sub block among the N+2 sub blocks.
Each clock signal may be a signal in which a unit pulse is repeated periodically, and a (n+1)-th clock signal among the plurality of clock signals is a signal delayed by a length of the unit pulse from a n-th clock signal among the plurality of clock signals.
Each sub block may include a first switch unit and a second switch unit. The first switch unit may control a charging state of the sub block in response to a clock signal generated by the clock generator. The second switch unit may control a transfer state or a reset state of the sub block in response to the clock signal.
The second switch unit may include a transfer switch and a reset switch. The transfer switch may be connected to an output terminal of the FIR filter. The reset switch may be connected to a reset terminal of the FIR filter.
According to another aspect, there is provided a finite impulse response (FIR) filter, which may include a clock generator and a plurality of sub blocks. The clock generator may generate a plurality of clock signals that are different from each other. The plurality of sub blocks may each have a state among N charging states for storing a received sample, a transfer state for outputting the stored sample, or a reset state for operation initialization. The N charging states, the transfer state and the reset state may be changed in response to a clock signal generated by the clock generator. At least one sub block among the plurality of sub blocks may be in the transfer state.
The clock signal generated by the clock generator may be used to control a charging state of a first sub block among the plurality of sub blocks, and may simultaneously control a transfer state or a reset state of a second sub block among the plurality of sub blocks.
Each sub block may include N sample storage units, a first switch unit and a second switch unit. The N sample storage units may store a received sample. The first switch unit may be connected to the N sample storage units, and may control a charging state of the sub block in response to a clock signal received from the clock generator. The second switch unit may be connected to the N sample storage units, and may control a transfer state or a reset state of the sub block in response to the clock signal.
According to yet another aspect, there is provided a finite impulse response (FIR) filter, in which a plurality of FIR filter units may be connected in a cascade structure, and which may include a plurality of sub blocks, each having a state among N charging states for storing a received sample, a transfer state for outputting the stored sample, and a reset state for operation initialization. The N charging states, the transfer state, and the reset state may be changed sequentially in response to an external clock signal. At least one sub block of the plurality of sub blocks may be in the transfer state. The FIR filter units of the above configuration can also be connected in a cascade structure to a conventional FIR filter exhibiting decimation.
The FIR filter may further include a clock generator generating a plurality of clock signals for controlling states of the plurality of FIR filter units.
Additional aspects of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice thereof.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, intended to provide further explanation, but not as limiting, of the subject matter claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the embodiments of the invention, and together with the description serve to explain various aspects of the invention, of which drawings:
Several embodiments are described more fully hereinafter with reference to the accompanying drawings. Aspects of the present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope thereof to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.
Referring to
A FIR filter is used to change the characteristics of a signal. A FIR filter filters an input signal using a moving average method or a running average method.
For example, each of the sub blocks 102-1 through 102-m temporarily stores an input signal, calculates a moving average or running average of the stored signal and outputs the result of the calculation, under the control of the clock generator 101.
In the current embodiment, the FIR filter has N+2 sub blocks 102-1 through 102-m, and each sub block, for example, the sub block 102-1, has N sample storage units 103-1 through 103-n, wherein N is a decimation factor selected considering the specification of a system. The decimation factor may be a value related to the frequency characteristics of the FIR filter. For example, if a decimation value 3 is obtained as the result of analysis on a transfer function of a conventional down-sampling FIR filter, the N value is set to “3” when the FIR filter according to the current example is configured. In this example, 5 sub blocks are constructed and each sub block includes 3 sample storage units. Of course, even in this example, the N value can be set to a value (for example, “4”) greater than “3”, and also, can be set to an arbitrary value which does not influence the overall performance of the system.
The clock generator 101 generates a plurality of clock signals to control the sub blocks 102-1 through 102-m. The clock signals are different from each other. For example, each clock signal may be a signal in which a unit pulse is repeated periodically, and a (n+1)-th clock signal may be a signal delayed by the length of a unit pulse from a n-th clock signal.
Each of the sub blocks 102-1 through 102-m can store (sample or charge) an input signal, combine and transfer the stored input signal, or discharge (reset) the input signal for initialization, in synchronization to a clock signal of the clock generator 101. For example, each of the sub blocks 102-1 through 102-m has a charging state, a transfer state, or a reset state, and the states of the sub blocks 102-1 through 102-m may be changed in response to a clock signal of the clock generator 101.
Referring to
In the transfer state 302, samples stored in the sample storage units 103-1 through 103-n are combined and transferred.
In the reset state 303, the operation of the system is initialized and the sample storage units 103-1 through 103-n are, e.g., grounded.
If a clock signal is received from the clock generator 101 when each of the sub blocks 102-1 through 102-m is in any one of the charging state, transfer state and reset state, the current states of the sub blocks 102-1 through 102-m can be changed in response to the clock signal. For example, as illustrated in
Again referring to
For example, it is assumed that in a FIR filter including three sub blocks (for example, first, second and third sub blocks 102-1, 102-2 and 102-3) each having a sample storage unit 103, a clock generator (not shown) generates three different clock signals (for example, T1, T2 and T3). In this case, the clock signal T1 is input to each of the first, second and third sub blocks 102-1, 102-2 and 102-3. For example, the clock signal T1 is applied to the first switch unit 104 of the first sub block 102-1 to control the charging state of the first sub block 102-1, simultaneously applied to the second switch unit 105 of the second sub block 102-2 to control the reset state of the second sub block 102-2, and also applied to the second switch unit 105 of the third sub block 102-3 to control the transfer state of the third sub block 102-3.
The operation of the FIR filter will be described in more detail below with reference to the circuit diagram of the FIR filter according to an embodiment shown in
In
According to the embodiment, each sample storage unit 103 may be a switched capacitor connected to the sampling switch 104. The transfer switch 301 switchably connects the sample storage unit 103 to an output terminal. The reset switch 302 switchably connects the sample storage unit 103 to, e.g., a ground.
A clock signal generated by the clock generator 101 (see
A clock signal (for example, a clock signal T1) among a plurality of clock signals, applied to the respective switches 104, 301 and 302, is a signal which is applied from the first sub block 102-1 to the sampling switch 104 to control the charging state of the first sub block 102-1. Simultaneously, the clock signal T1 is also applied to the remaining sub blocks 102-2 through 102-5. That is, the clock signal T1 is applied to the reset switch 302 of the second sub block 102-2 to control the reset state of the second sub block 102-2. Also, the clock signal T1 is applied to the transfer switch 301 of the third sub block 102-3 to control the transfer state of the third sub block 102-3. Likewise, clock signals T2 through T5 are applied to the respective sub blocks 102-1 through 102-5 in a manner similar to that in which the clock signal T1 is applied to the respective sub blocks 102-1 through 102-5.
Hereinafter, the operation of the FIR filter according to the current embodiment will be described with reference to
In a period A, the clock signal T1 is in a “high” state and the remaining clock signals T2 through T5 are in a “low” state. Accordingly, the first, fourth and fifth sub blocks 102-1, 102-4 and 102-5 to which the clock signal T1 is applied through their input switches 104 are in the charging state, and input signals are stored in the respective sample storage units 103 of the first, fourth and fifth sub blocks 102-1, 102-4 and 102-5. However, the second sub block 102-2 to which the clock signal T1 is applied through its reset switch 302 is in the reset state, and the third sub block 102-3 to which the clock signal T1 is applied through its transfer switch 301 is in the transfer state.
Thereafter, in a period B, the clock signal T2 goes “high” and the remaining clock signals T1, T3, T4 and T5 are in the “low” state. Accordingly, the first, second and fifth sub blocks 102-1, 102-2 and 102-5 to which the clock signal T2 is applied through their input switches 104 are in the charged state, the third sub block 102-3 to which the clock signal T2 is applied through its reset switch 302 are in the reset state, and the fourth sub block 102-4 to which the clock signal T2 is applied through its transfer switch 301 is in the transfer state. Here, in the first sub block 102-1, the clock signal T1 goes “low”, which holds a sample stored in the first sample storage unit 103-1.
A table showing the states of the first through fifth sub blocks 102-1 through 102-5 during the periods A through E is as follows.
Referring to Table 1, the first through fifth sub blocks 102-1 through 102-5 have different states for each period, and particularly one of the sub blocks 102-1 through 102-5 is in a transfer state for each period. Accordingly, in the case where an input signal is received for each period, since an output signal is generated whenever the input signal is received, decimation can be removed.
As described above, a FIR filter according to an embodiment of the present invention has no decimation. Accordingly, by connecting a plurality of filters each having the construction of the FIR filter illustrated in
In
Since the NDF 202 has no decimation, it is possible to improve attenuation characteristics by cascading a plurality of NDFs 202. The NDFs 202 connected in a cascade structure can be connected to the front or back stage of the conventional FIR filter 201. Also, it is possible to connect two groups of NDFs 202 connected in series respectively to the front and back stages of the conventional FIR filter 201. The number of NDFs 202 connected in series is not limited, and a frequency response can be improved so that it appears in the waveform of a sincN function.
Referring to
Comparing the frequency characteristics of the conventional FIR filter with the frequency characteristics of the filter set according to the current embodiment, more portions of the frequency-characteristics function of the filter set are below an attenuation level which is a requirement for a filter, than in the conventional FIR filter.
Accordingly, the bandwidth of a notch is widened and an anti-aliasing function is improved, and as a result the filter set according to the current embodiment can be applied to a broadband system.
In other words, in the case of a filter set constructed by cascading a plurality of NDFs to the front or back stage of a conventional FIR filter with decimation, attenuation characteristics can appear maximally in the waveform of a sincN function and bandwidth characteristics can also be improved. As a result, the filter set according to the current embodiment can be applied to a broadband system.
In the case of the filter set according to the current embodiment, at least 2N unit clock signals are needed, and a clock signal for controlling a transfer state and reset state can be generated by combining the unit clock signals.
As a result, since a FIR filter according to an embodiment of the present invention has no decimation, it is possible to connect a plurality of NDFs and a conventional FIR filter in a cascade structure and improve the attenuation characteristics and bandwidth characteristics of a filter.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Number | Date | Country | Kind |
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10-2008-0061566 | Jun 2008 | KR | national |