The present invention relates to an FIR filter allowing high-speed operation and flexible configuration.
A filter is an indispensable circuit element in signal processing and is the most frequently appearing and most important circuit in digital signal processing. There are two ways to configuring a digital filter, an FIR (Finite Impulse Response) filter and an IIR (Infinite Impulse Response) filter, but the FIR filter which enables a constantly stable characteristic is easier to use (for example, refer to Japanese Patent Application Lied-open No. 103,418/1984).
In the case of such an FIR filter, in realizing steep filter characteristics which are desirable to the system, it is necessary to provide a large scale circuit of high order (for example, refer to “Fundamentals of Digital Signal Processing” Chap. 4-4.2 edited by Shigeo Tsujii, 1988, Corona publishing co.), but in fact, it is generally difficult to provide a sufficient scaled filter because of the limitation in chip area of LSI and gate number of FPGA. Particularly when a high-bit high precision signal processing is needed, the necessary gate number and implementing area presumably increase according to square bit-number, hence above difficulty increases.
In addition, in digital signal processing, a subject signal is changed (sampled) to a digital signal before processing, but in doing so, it is necessary to sample it at the higher frequency of 10 times or more of the upper limit of its frequency range, and the succeeding digital signal processing circuits must also be operated at the same throughput. That is to say, a subject signal with a frequency range of the upper limit of 10 MHz will need to be sampled at a frequency of 100 MHz or above, and will need to be provided with a digital processing circuit which operates at a frequency of 100 MHz or above, and also, to process a signal up to 100 MHz, digital signal processing circuits operating at a frequency of 1 GHz or above is necessary. Thus a digital signal processing circuit requires a high operating frequency.
However, at present, except certain specially configured CPUs, the operating frequency of a digital circuit feasible by an LSI technique with a generally available CMOS process is approximately less than 2 GHz, and in the case of configuring a large scale digital filter, the operating frequency decreases even more, and in effect, it is impossible to develop an LSI operating at 1 GHz or above at a low cost.
Thus the purpose of the present invention is to manufacture a high-order and high-precision FIR filter, i.e. a large-scale digital filter capable of high-speed operation of 2 GHz or above at a low cost.
The present invention which has advantageously solved the above-mentioned problem is characterized by its configuration of a high-speed, high-order and high-precision FIR filter, i.e. a large-scale digital filter by combining a variety of FIR filter element circuits capable of high-speed operation to operate synchronously, and this variety of element circuits may be substituted by a single kind of element circuit.
That is to say, the FIR filter of the present invention comprises a plurality of input delay circuits which are mutually connected in cascade and each of which delays the input data and outputs it, and a plurality of multiplier circuits each of which multiplies respective input data of said plurality of input delay circuit and the output data of the input delay circuit of the final stage by respective coefficients to make partial output data, and FIR filter which sums up partial output data of said plurality of multipliers to make filter output data is characterized in that said FIR filter comprises a plurality of element circuits which have one or more input delay circuits each of which is configured by dividing said plurality of input delay circuits mutually connected in cascade in the direction of the cascade, and one or more multiplier circuits connected to said one or more input delay circuits, and which obtain partial sum data from partial output data of said one or more multiplier circuits, and among said plurality of element circuits, the initial stage element circuit outputs said partial sum data directly, and each of the succeeding element circuits from the second stage outputs the partial sum data obtained by adding delayed said partial sum data obtained inside that element circuit to partial sum data output by the element circuit of the prior stage, and the element circuit of the final stage outputs the partial sum data as the filter output data.
In addition, the element circuit of the present invention is characterized by having one or more of said input delay circuits mutually connected in cascade, and one or more of said multiplier which multiply to each one of the input data from one or more of said input delay circuits by a coefficient to make partial output data, and a partial output adder which adds the partial output data from one or more of said multiplier mutually to make partial sum data, or in addition by having a partial sum delay circuit which delays partial sum data of said partial output adder, and a partial sum adder which adds the partial sum data delayed by said partial sum delay circuit and partial sum data of said initial stage element circuit or said intermediate stage element circuit of the prior stage to make partial sum data, or, by having a partial sum delay circuit which delays partial sum data from said partial output adder, and a partial sum adder which adds partial sum data delayed by said partial sum delay circuit and the partial sum data from said intermediate stage element circuit of the prior stage to make the filter output data.
According to the FIR filter of the present invention, it has one or more input delay circuit configured by dividing(slicing) a number of input delay circuits mutually connected in cascade of the FIR filter in the middle of the taps into a plurality, and a plurality of element circuits which has one or more multiplier connected to said one or more input delay circuits and obtains the partial sum data from the partial output data of said multiplier, and in those element circuits, the initial stage element circuits output said partial sum data without modification, and from the second stage element circuits onward, partial sum data obtained by adding delayed said partial sum data obtained in the element circuits to the partial sum data output by the prior element circuit, is output, especially the element circuit of the last stage amongst the stages succeeding the second stage, modifies the partial sum data to make a filter output data by synchronizing and adding the partial sum data from said plurality of element circuits together, hence it is possible to manufacture a tap-slice type FIR filter having an arbitrary order and accuracy(number of bits), and capable of high-speed operation of 2 GHz or above.
However, the FIR filter of the present invention may be comprised of one initial stage element circuit comprised of one or more of said input delay circuit mutually connected in cascade into which filter input data is input, and one or more of said multiplier circuits each of which multiplies one or more input data of the input delay circuit by respective coefficients to make partial output data, and a partial output adder which adds said one or more partial output data mutually to make partial sum data of said one or more multiplier circuits, and one or more intermediate stage element circuits comprised of a plurality of said input delay circuits mutually connected in cascade, into which said initial stage element circuit or the output data from the final stage input delay circuit of said intermediate stage element circuit of the prior stage is input, and one or more of said multiplier circuits which multiply the input data from one or more of said input delay circuits by respective coefficients to make partial output data, and a partial output adder which adds the partial output data from one or more of said multiplier circuits mutually to make partial sum data, and a partial sum delay circuit which delays partial output data of said partial output adder, and a partial sum delay circuit which delays the partial sum data from said partial output adder, and a partial sum adder which adds partial sum data delayed by said partial sum delay circuit and partial sum data of said initial stage element circuit or said intermediate stage element circuit of the prior stage to make partial sum data, and a final stage element circuit comprised of one or more of said input delay circuits mutually connected in cascade, into which the output data from the final stage input delay circuit of said intermediate stage element circuit of the prior stage is input, and a plurality of said multiplier circuits which the input data from one or more of said input delay circuits and the output data from the last stage input delay circuit by respective coefficients to make partial output data, and a partial output adder which adds partial output data of said plurality of multiplier circuits mutually to make partial sum data, and a partial sum delay circuit which delays partial sum data of said partial output adder, and a partial sum adder which adds partial sum data delayed by said partial sum delay circuit and partial sum data of said intermediate stage element circuit of the prior stage to make filter output data, and in this way, in the partial sum delay circuit incorporated in the intermediate stage element circuit and the final stage element circuit, partial sum output data of the element stages from initial stage element circuit to final stage element circuit and inner partial sum data of the element circuit can be synchronized with and added, thus it is possible to realize a tap-slice type FIR filter having an arbitrary order and accuracy (bit number) and capable of high-speed operation of 2 GHz or above, and moreover, owing to the mass-production effect of the element circuits being assembled in 3 parts; the initial stage element circuit, the intermediate stage element circuit, and the final stage element circuit, the cost of the high-end digital filter is easily reducible.
In addition, the FIR filter of the present invention may be comprised of a plurality of element circuit sets which correspond respectively to a plurality of divided input data divided from the original filter input data, each element circuit set configured by said initial stage element circuit, said intermediate stage element circuit, and said final stage element circuit, and a plurality of element circuit sets in which said coefficients of said multiplier circuits of the element circuits corresponding to the stage of each of the element circuit sets are made equal, and a filter output adder which aligns the decimal point and sums up the partial output data as a filter output data output by said final stage element circuit of said plurality of element circuit sets, and outputs the filter output data having a bit length corresponding to that of the original input data, and in this way, a bit-slice type FIR filter is also realizable by the FIR filter of the present invention, and a larger-scale digital filter may be configured.
Moreover, in the FIR filter of the present invention, said coefficient of said multiplier circuit may be made variable, and in this way, the filter characteristics can be changed arbitrarily, and a large-scale adaptive digital filter may be configured.
Meanwhile, an element circuit of the FIR filter of the present invention having one or more of said input delay circuit mutually connected in cascade, and one or more of said multiplier circuits which multiply the input data from one or more of said input delay circuits by respective coefficients to make partial output data, and a partial output adder which adds the partial output data from one or more of said multiplier circuits mutually to make partial sum data, may be used for the initial stage element circuits of said FIR filter of the present invention, and in addition an element circuit of the FIR filter of the present invention having a partial sum delay circuit which delays partial output data of said partial output adder, and a partial sum adder which adds partial sum data delayed by said partial sum delay circuit and partial sum data of said initial stage element circuit or said intermediate stage element circuit of the prior stage to make partial sum data, may be used for the intermediate stage element circuits of said FIR filter of the present invention, and in addition to the first element circuit, an element circuit of said FIR filter of the present invention having a partial sum delay circuit which delays partial sum data from said partial output adder, and a partial sum adder which adds partial sum data delayed by said partial sum delay circuit and the partial sum data from said intermediate stage element circuit of the prior stage to make filter output data may be used for the final stage element circuit of said FIR filter of the present invention.
In addition, the element circuits of the FIR filter which may be used in said intermediate stage element circuits sorts, by not using part of the components or data, may function as a substitute for at least either said initial stage element circuit or said final stage element circuit, and in this way, the number of the element circuits may be decreased to increase the mass-production effect and the cost of the high-end digital filter can be reduced even more.
Furthermore, in the element circuits of said FIR filter, said coefficient of said multiplier circuit may be made variable, and in this way, the filter characteristics can be changed arbitrarily, and a large-scale adaptive digital filter may be configured easily.
According to the present invention, an FIR filter is configured by 4 sorts of element circuits including the post-processing circuit 4. The input signal (filter input data) is generally input as a multiple-bit digital signal, but in this embodiment, the input signal is divided into two bit groups of the upper and lower, and bit-slice configuration is employed so as to enable bit- slice processing on both groups separately. For example, if the input signal is 24 bits wide, the upper 12 bits are assigned to the upper bit group 5, and the lower 12 bits are assigned to the lower bit group 6. The FIR filter of the present invention is configured by 3 sorts of element circuits 1 to 3 with the exclusion of the post-processing circuit 4, and the reason these 3 sorts of circuits are necessary is because the input and output data of each of the element circuits differ slightly. As illustrated, the 3 sorts of element circuits 1 to 3 are connected in cascade and arranged in sets, and the number of the sets is equal to the number of bit-slices; in this embodiment 2 sets, in the diagram disposed one above the other, to obtain the final output data 10 by processing each of the output signals 11 and 12 from these two element circuit sets with the post-processing circuit 4 as a filter output adder. In addition, the inner multiplier coefficient and the delay degree of the partial sum delay circuit of the element circuits 1 to 3 is designed to be variable, and are made externally settable by the setting signal 9. Meanwhile, the multiplier coefficient of the multiplier in the corresponding tap position of the multipliers of the 2 above mentioned element circuit sets which respectively processes the 2 bit groups must be made aligned (equal) to each other.
The intermediate stage element circuit 116 calculates the inner partial sum data of the element circuits at the partial output adder 118, then delays properly that partial sum data at the partial sum delay circuit 120, and calculates the sum of the delayed partial sum data and partial sum data 113 (in the case of having a plurality of intermediate stage element circuits 116, after the second intermediate stage element circuit 116, partial sum data 114 from the intermediate stage element circuit 116 of the prior stage is employed) from the initial stage element circuit 115 of the prior stage at the partial sum adder 119, and outputs the value of the calculation result as the partial sum data 114 of the intermediate stage element circuit 116.
The final stage element circuit 117 is the same as the intermediate stage element circuit 116, and after calculating the inner partial sum data of the element circuits at the partial sum adder 118, it properly delays the partial sum data at the partial sum delay circuit 120 and calculates the sum of the delayed sum data and the partial sum data 114 from the intermediate stage element circuit 116 of the prior stage at the partial sum adder 119, and outputs the value of the calculation result as the output signal 105.
Next, we explain the element circuits which an adaptive digital filter may configure, as shown in
According to the initial stage element circuit, intermediate stage element circuit, and final stage element circuit of these embodiments, it is possible to synchronize and to add the partial sum output data of the element circuits and the inner partial sum data of the element circuits by the partial sum delay circuit 211 implemented in the intermediate stage element circuit and the final stage element circuit, thus a tap-slice type FIR filter having an arbitrary order and accuracy(number of bits), and capable of high-speed operation of 2 GHz or above is realizable, and moreover, owing to the mass-production effect of the element circuits being assembled in 3 parts; the initial stage element circuit, the intermediate stage element circuit, and the final stage element circuit, the cost of the high-end digital filter is easily reducible, and furthermore, the value of the multiplier coefficient, which is stored by the multiplier coefficient memory 208 of the multiplier 201, is settable/valuable by multiplier coefficient/partial sum delay setting signal 207, therefore, it is possible to change the filter characteristics arbitrarily and configure a large scale adaptive digital filter. Also, according to the initial stage element circuit, intermediate stage element circuit, final stage element circuit, and the post-processing circuit of this embodiment, a bit-slice type FIR filter capable of having the same effect, as mentioned-above, for data with a wider bit width is realizable.
In the above explanations, the FIR filter was configured by 4 sorts of element circuits, but according to the present invention, it is possible to configure the FIR filter by less sorts of element circuits. First, the final stage element circuit of
Moreover, the post-processing circuit in
In this way, according to the present invention, it is possible to configure a large-scale FIR filter having many taps, and an arbitrary characteristic for a wide range of width in bits of the data by using only intermediate stage element circuit.
Thus, the delay setting value of the partial sum delay circuit 211 in the second stage should be set so as to satisfy the following equation (1).
ta1+ts1+tb1=ta2 (1)
In addition, the delay setting value of the partial sum delay circuit 211 in the third stage is likewise, and should be set so as to satisfy the following equation (2).
ta2+ts2+tb2=ta3 (2)
Thus far, the explanations were according to the illustrated examples, but the present invention is not limited to said example of the bit-slice type, and for example, it may configure a tap-slice type FIR filter as shown in
Also, said element circuits for the FIR filter of the present invention may be realized as a LSI chip, and configure a large-scale FIR filter by connecting inside a multi-chip module or a SIP (System In Package), or be realized as one chip one package, and realize a large-scale FIR filter on the printed board.
Moreover, these element circuits may be realized as a hard macro or a soft macro for a LSI, be connected in an LSI and realize a large-scale FIR filter as a part of the SOC (System On a Chip), or providing FPGAs and CPLDs with these element circuits built in, and connecting the element circuits using the variable connecting function of the FPGA and CPLD, or realize a large-scale FIR filter by using the built-in module of FPGA and CPLD together.
Furthermore, these element circuits may be realized as a hybrid IC, a circuit module, a daughter board, or a printed board having a card connecter and the like, and realizing a large-scale FIR filter which connects these circuits likewise, and in the same way, realizing a large-scale FIR filter by configuring these element circuits inside a vessel made of metal or plastic, and connecting the circuits with connecters and cables for intersystem connections.
The present invention is applicable to the implementation of all sorts of filters from high-end to low-end, and enables to facilitate the realization of an FIR filter at low cost.
Number | Date | Country | Kind |
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2003-411068 | Dec 2003 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP04/18054 | 12/3/2004 | WO | 3/29/2007 |