The present invention relates to pulse width modulation in power converters, and more specifically to Fixed Frequency Ripple Regulator modulation.
A simplified diagram of a synthetic ripple regulator pulse width modulation (PWM) converter is shown in
The positive slope of voltage VR at node 36 can be written as:
VRPOS=gm·(Vin−Vout)
and the negative slope of VR can be written as:
VRNEG=gm·Vout,
where gm is the gain of the transconductance amplifiers.
The Synthetic Ripple Regulator of
a and 3b illustrate operation of the SSR for a load step up and load step down. The ripple voltage across CR is determined between EA and EA+Vwindow, the window voltage. When the ripple voltage VR drops below EA, the flip-flop 15 is set so the PWM pulse starts. When the ripple voltage exceeds EA+VW, the flip-flop is reset and the PWM pulse terminates. The duty cycle of the PWM pulse is determined by comparing the EA output to the ripple voltage.
While Synthetic Ripple Regulator (SRR) modulation technology claims the fastest response, SRR modulation has inherent shortcomings. Such shortcomings include variable frequency operation and difficulty of implementation in multi-phase applications.
It is an object of the present invention to provide a converter modulator with a faster transient response from the SRR.
It is another object of the present invention to provide a converter operating with Fixed Frequency pulse width modulation that is easy to implement in single phase as well as multi-phase PWM controllers.
It is yet another object of the present invention to provide a converter modulator with a fixed frequency operation.
It is furthermore an object of the invention to use Fixed Frequency pulse width modulation to make LC output filters resemble a first order system in which the closed loop stability can be achieved with a type II compensation network, making internal integrated compensation possible.
Provided is a ripple regulator for providing a pulse width modulation (PWM) signal for regulating an output voltage of a power converter switching stage. The regulator including a ripple circuit for providing a ripple voltage; a comparison circuit for comparing the ripple voltage to an output of an error amplifier; and a PWM circuit producing the PWM signal and receiving an output of the comparison circuit and a clock signal input, the clock signal input determining a first edge of the PWM signal and the output of said comparison circuit determining a second edge of the PWM signal.
Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.
a and 3b are graphs showing load step-up and load step-down results simulated with the ripple regulator of
a and 4b are graphs showing load step-up and load step-down results simulated with the ripple regulator of
In
The implementation methods of the Fixed Frequency Ripple Regulator can vary. However, the basic concept shown in the FFRR circuit of
a and 4b show the operation of the invention during a load step-up and load step down. The ripple voltage is shown. The invention shows an improved, faster transient response. In
b shows a load step down. As the voltage VOUT starts to increase, the ripple voltage switches the comparator 42A sooner than the SRR circuit, thereby reducing the duty cycle faster and providing a better response.
In the FFRR circuit of
Further, in addition to providing a faster transient response and being easy to implement in either single phase or multi-phase PWM controllers, the FFRR circuit of
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.
This application is based on and claims priority to U.S. Provisional Patent Application Ser. No. 60/977,484, filed on Oct. 4, 2007 and entitled FIXED FREQUENCY RIPPLE REGULATOR, the entire contents of which are hereby incorporated by reference.
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