FIXED VALUE MULTIPLICATION USING FIELD-PROGRAMMABLE GATE ARRAY

Abstract

A method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (pi) from p using the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.

Description

BACKGROUND

The present invention relates to computing technology, and particularly to improvement to a fixed-value multiplier used by computing systems, where the improvement is achieved by using a field-programmable gate array (FPGA).

An FPGA is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Computing a multiplication of two numbers is a common operation performed by various computing systems. Several computing systems require a multiplication in which one of the values is known or fixed, and the second is a dynamic input value.

SUMMARY

According to one or more embodiments of the present invention, a method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (p_i) from p using the lookup tables based on specific combination of bits from the known binary number w and from the input binary number d, wherein a notation j_x represents the x^th bit of j from the right, with bit j₀ being the rightmost bit of j.

In one or more embodiments of the present invention, the known binary number w has a predetermined number of bits. For example, the known binary number is an 8-bit binary number. Further, in one or more embodiments of the present invention, the input binary number has a predetermined number of bits. For example, the input binary number is a 12-bit binary number.

In one or more embodiments of the present invention, the bits p₅, p₄, p₃, p₂, p₁, and p₀ of p are determined by a first circuit that includes a first layer of the lookup tables from the integrated circuit based on the bits d₅, d₄, d₃, d₂, d₁, and do of the input binary number d. Further, the bits p₈, p₇, and p₆, of p are determined by a second circuit from the integrated circuit based on the first set of auxiliary bits computed by the first circuit. The second circuit includes a second layer of the lookup tables. Further yet, the bits p₁₆, p₁₅, p₁₄, p₁₃, p₁₂, p₁₁, and p₁₀ of p are determined by a third circuit from the integrated circuit based on auxiliary bits computed by the second circuit. The third circuit includes a third layer of the lookup tables. In one or more embodiments of the present invention, determining the bit p₁₉ of p includes determining, using a subset of lookup tables, that t≤d, wherein t=┌2¹⁹/w┐ is precomputed, and in response to t≤d, p₁₉ is set to 1, and otherwise p₁₉ is set to 0.

In one or more embodiments of the present invention, determining the bit p₁₈ of p includes precomputing threshold values t₀₁, t₁₀, and t₁₁:

t ₀₁=┌2¹⁸/w┐,

t ₁₀=└(2¹⁹−1)/w┘, and

t ₁₁=┌(2¹⁹+2¹⁸)/w┐.

In response to (t₁₁≤d) or (t₀₁≤d≤t₁₀), p₁₈ is set to 1, and otherwise to 0.

Further, in one or more embodiments of the present invention, determining the bit p₁₇ of p includes precomputing threshold values:

t ₀₀₁=┌2¹⁷/w┐,

t ₀₁₀=└(2¹⁸−1)/w┘,

t ₀₁₁=┌(2¹⁸+2¹⁷)/w┐,

t ₁₀₀=└(2¹⁹−1)/w┘,

t ₁₀₁=┌(2¹⁹+2¹⁷)/w┐,

t ₁₁₀=└(2¹⁹+2¹⁸−1)/w┘, and

t ₁₁₁=┌(2¹⁹+2¹⁸+2¹⁷)/w┐.

P₁₇ is set to 1 in response to t₁₁₁≤d, t₁₀₁≤d≤t₁₁₀, t₀₁₁≤d≤t₁₀₀, and t₀₀₁≤d≤t₀₁₀, and to 0 otherwise.

The technical solutions described herein can also be achieved by implementing a system that includes a memory device that stores a known binary number (w), and a multiplication circuit that performs the method to determine the multiplication result (p) of the known binary number with an input binary number (d) that is received dynamically.

Alternatively, in one or more embodiments of the present invention, a neural network system includes a multiplication circuit for performing a method to determine a multiplication result of a weight value with an input value (d) that is received dynamically, the method including configuring several lookup tables in an integrated circuit based on the weight value (w) that is a known value. The lookup tables can be configured in three layers. The method further includes determining a multiplication result (p) of the weight value w and the input value d by determining each bit (p_i) from p using the lookup tables based on a specific combination of bits from the weight value w and from the input value d, wherein a notation j_x represents the x^th bit of j from the right, with bit j₀ being the rightmost bit of j.

In yet another embodiment of the present invention, an electronic circuit determines a multiplication result (p) of a weight value (w) and an input value (d) that is received dynamically. Determining the multiplication result includes configuring several lookup tables based on the weight value (w), and determining each respective bit (p_i) of the multiplication result (p) using the lookup tables based on specific combination of bits from the weight value w and from the input value d. The notation j_x represents the x^th bit of j from the right, with bit j₀ being the rightmost bit of j.

In another embodiment of the present invention, a field programmable gate array includes several lookup tables, wherein the field programmable gate array performs a method for determining a multiplication result (p) of a weight value (w) and an input value (d) that is received dynamically. The lookup tables can be configured in three layers.

Embodiments of the present invention can include various other implementations such as machines, devices, and apparatus.

Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 depicts a block diagram of a system that uses a multiplication circuit according to one or more embodiments of the present invention;

FIG. 2 depicts an exemplary neural network system according to one or more embodiments of the present invention;

FIG. 3 depicts a block diagram of a multiplication circuit according to one or more embodiments of the present invention;

FIG. 4 depicts a flowchart of a method for determining a multiplication result of a known value, w, with input value, d, according to one or more embodiments of the present invention;

FIG. 5 depicts a first circuit used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 6 depicts a second circuit used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 7 depicts a third circuit used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 8 depicts a lookup table used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 9 depicts several lookup tables used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 10 depicts a lookup table used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 11 depicts a lookup table used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 12 depicts a lookup table used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 13 depicts a circuit used to determine a most significant bit of a multiplication result according to one or more embodiments of the present invention;

FIG. 14 depicts a circuit used to determine a second most significant bit of a multiplication result according to one or more embodiments of the present invention;

FIG. 15 depicts several lookup tables used in a multiplication circuit according to one or more embodiments of the present invention;

FIG. 16 depicts a circuit used to determine a third most significant bit of a multiplication result according to one or more embodiments of the present invention; and

FIG. 17 depicts a computing system that can be used to implement one or more embodiments of the present invention.

The diagrams depicted herein are illustrative. There can be many variations to the diagrams or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order, or actions can be added, deleted, or modified. Also, the term “coupled” and variations thereof describe having a communications path between two elements and do not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention provide improved efficiency for computing a multiplication in computing systems, particularly in the case where one of the values to be multiplied is a fixed (known) value, and the second value to be multiplied is dynamically input. Exemplary embodiments of the present invention provide a multiplication circuit for performing such a computation efficiently. The values are represented in digital format using binary numbers. In one or more embodiments of the present invention, a field-programmable gate array (FPGA) includes a plurality of lookup tables (LUTs), the LUTs being configured in n layers to realize the multiplication circuit.

As a brief introduction, FPGAs typically contain an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together,” like several logic gates that can be coupled together in different configurations. Logic blocks can be configured to perform combinational functions, logic gates like AND and XOR, and other functions. The logic blocks also include memory elements, such as flip-flops or more complete blocks of memory. It should be noted that FPGAs can include components different from those described herein; the above is an exemplary FPGA.

A technical challenge with computing systems is improving the time required for the computing system to perform calculations such as multiplication of numbers represented as binary numbers. Technical solutions provided by embodiments of the present invention address such technical challenges by providing an n layered multiplication circuit that performs a multiplication in deterministic time for two binary numbers—one fixed-value number and one variable number that is input at runtime. One or more embodiments of the present invention use FPGAs to implement the multiplication circuit using LUTs. As used herein, a “k-to-1 Boolean function” is implemented as a k-input LUT that provides a 1-bit output given a k-bit input.

Further, the present document denotes B={0,1}, Bⁿ is the set of all n-tuples of zeros and ones, and B_n is the set of all Boolean functions Bⁿ→B. Also, the present document uses the same symbol x interchangeably to denote both a Boolean vector x=(x₀, . . . , x_k-1)∈B^k and a natural number x=Σ_i=0^k-1x_i2^k. The operation of the addition of two Boolean vectors, including two Boolean scalars, is denoted without confusion by the same ‘+’ sign. Accordingly, the technical challenge restated using the terminology just established is to compute the product of an input value d and a fixed-value weight w.

FIG. 1 depicts a block diagram of a system for computing a fixed-value binary number multiplication according to one or more embodiments of the present invention. For example, the multiplication circuit 115 that is described herein can be a part of a computing system 110 that receives an input-value (d) from an input source 120. The multiplication circuit 115 calculates an output p of a product of d with a known fixed value w.

In one or more embodiments of the present invention, the computing system 110 can be an artificial neural network system. Alternatively, the computing system 110 is a desktop computer, a server computer, a tablet computer, or any other type of computing device that uses the multiplication circuit 115 to compute a product of two binary numbers, one of which has a known value (w).

In one or more embodiments of the present invention, the input source 120 can be a memory, a storage device, from which the input-value is provided to the multiplication circuit 115. Alternatively, or in addition, the input-value can be input to the multiplication circuit 115 directly upon acquisition, for example, the input source 120 is a sensor, such as a camera, an audio input device, or any other type of sensor that captures data in a form that can be input to the multiplication circuit 115.

FIG. 2 illustrates an example, non-limiting neural network system for which efficiency can be facilitated in accordance with one or more embodiments of the invention. The neurons of a neural network 200 can be connected so that the output of one neuron can serve as an input to another neuron. Neurons within a neural network can be organized into layers, as shown in FIG. 2. The first layer of a neural network can be called the input layer (224), the last layer of a neural network can be called the output layer (228), and any intervening layers of a neural network can be called a hidden layer (226). Aspects of systems (e.g., system 200 and the like), apparatuses, or processes explained herein can constitute machine-executable component(s) embodied within machine(s), e.g., embodied in one or more computer-readable mediums (or media) associated with one or more machines. Such component(s), when executed by the one or more machines, e.g., computer(s), computing device(s), virtual machine(s), etc. can cause the machine(s) to perform the operations described. Repetitive description of like elements employed in respective embodiments is omitted for the sake of brevity.

The system 200 and/or the components of the system 200 can be employed to use hardware and/or software to solve problems that are highly technical in nature, that are not abstract and that cannot be performed as a set of mental acts by a human. For example, system 200 and/or the components of the system 200 can be employed to use hardware and/or software to perform operations, including facilitating an efficiency within a neural network. Furthermore, some of the processes performed can be performed by specialized computers for carrying out defined tasks related to facilitating efficiency within a neural network. System 200 and/or components of the system 200 can be employed to solve new problems that arise through advancements in technology, computer networks, the Internet, and the like. System 200 can further provide technical improvements to live and Internet-based learning systems by improving processing efficiency among processing components associated with facilitating efficiency within a neural network.

System 200, as depicted in FIG. 2, is a neural network that includes five neurons—neuron 202, neuron 204, neuron 206, neuron 208, and neuron 210. The input layer 224 of this neural network is comprised of neuron 202 and neuron 204. The hidden layer 226 of this neural network is comprised of neuron 206 and neuron 208. The output layer 228 of this neural network is comprised of neuron 210. Each of the neurons of input layer 224 is connected to each of the neurons of hidden layer 226. That is, a possibly-weighted output of each neuron of input layer 224 is used as an input to each neuron of hidden layer 226. Then, each of the neurons of hidden layer 226 is connected to each of the neurons (here, one neuron) of output layer 228.

The neural network of system 200 presents a simplified example so that certain features can be emphasized for clarity. It can be appreciated that the present techniques can be applied to other neural networks, including ones that are significantly more complex than the neural network of system 200.

In the context of artificial neural networks, each of the neurons performs a computation, for example, during various phases, such as forward propagation, backward propagation, and weight update. Such computations can include multiplication. In one or more embodiments of the present invention, the computations include multiplication of a weight-value assigned to the neuron (which is a known and fixed value), and an input value (which can be variable). Here, the “weight-value” represents the weight that is assigned to a neuron in the neural network 200, and the “input-value” is a value received by that neuron to calculate the output. The calculation can be performed during the training of the neural network or during inference using the neural network. In one or more embodiments of the present invention, the calculation can be performed during any phase of the training, forward propagation, backward propagation, weight update, or any other phase. The performance of the neural network 200 can be improved if the efficiency of the multiplication operation can be improved. One or more embodiments of the present invention facilitate a faster way of calculating a multiplication of an input-value (d) with the weight-value (w). Further, one or more embodiments of the present invention facilitate hardware components to support such calculation using LUTs.

It is noted that although FIG. 2 depicts an embodiment of the present invention with the computing system 110 as a neural network system (200), in one or more embodiments of the present invention, the computing system 110 can be other types of computing systems that include the multiplication circuit 115.

The technical solutions provided by one or more embodiments of the present invention are now described using an exemplary case where w is an 8-bit value, and d is a 12-bit value. It is understood that in other embodiments of the present invention, the values can have a different number of bits. However, for explaining the operation of the technical solutions of the present invention, the above example scenario is chosen. Accordingly, the computational problem is defined by a fixed nonzero weight-value, which is a vector of bit-values w=(w₀, . . . , w₇)∈B⁸, so w=Σ_i=0⁷w_i2ⁱ. The input-value is a vector of bit-values d=(d₀, . . . , d₁₁)∈B¹², so d=Σ_i=0¹¹d_i2ⁱ.

The input-value d can also be represented as d=g 2⁶+h, where g and h are integers such that 0≤g, h<2⁶. Accordingly,

$g=\lfloor \frac{d}{2^6}\rfloor$

and h=d−g·2⁶.

In this case, p is a vector of bit-values such that p=(p₀, . . . , p₁₉)∈B²⁰, so p=Σ_i=0¹⁹p_i2ⁱ, and hence, 0≤p≤2²⁰−1. In this document, a function is denoted P_i(d)=P_i(d;w), where the function returns p i=0, . . . , 19.

Now, if n is any natural number, and if g is an n-to-1 Boolean function, and if ƒ₁, . . . , ƒ_n are n 6-to-1 Boolean functions, the composition h(x)=g(ƒ₁, (x), . . . , ƒ_n(x)) is also a 6-to-1 Boolean function. Further, let x={0, . . . , 2⁶−1} and let y=x+1, where x and y are Boolean vectors. For i=0, . . . , 5:

$\begin{array}{cc}{J}_i\left(x\right)\{\begin{array}{cc}1\mathrm{if}{x}_j=1& \mathrm{for}j=0,1,\dots ,i\\ 0& \mathrm{otherwise}\end{array}& \left(1\right)\end{array}$

Under these conditions, for i=0, . . . , 5, y, =x, if and only if J_i(x)=0, and y₆=1 if and only if J₅(x)=1.

It can be proven that for every natural n E N, there exists a 2-level circuit of 6-to-1 Boolean functions, where the circuit decides for every d∈B¹² whether or not d<n. If n≥2¹², then because d<2¹², the problem is trivial. Hence, consider that n<2¹². In this case, the number n can be uniquely represented as n=a·2⁶+b, where a and b are integers such that 0≤a, b<2⁶. Here, d<n if and only if either (i) g<a, or (ii) g=a and h<b. Defining the following functions:

$G\left(d\right)=G\left(g\right)=\{\begin{array}{cc}1& \mathrm{if}g<a\\ 0& \mathrm{if}g\ge a\end{array}E\left(d\right)=E\left(g\right)=\{\begin{array}{cc}1& \mathrm{if}g=a\\ 0& \mathrm{if}g\ne a\end{array}\mathrm{and}H\left(d\right)=H\left(g\right)=\{\begin{array}{cc}1& \mathrm{if}h<b\\ 0& \mathrm{if}h\ge b\end{array}$

Each of these functions is a 6-to-1 Boolean function. It should be noted that although d∈B^1-2 each of these functions operates on only six bits of d. Let J: B³→B be the following:

$J\left(x_1,x_2,x_3\right)=\{\begin{array}{cc}1& \mathrm{if}{x}_1=1\\ 1& \mathrm{if}{x}_2=1\mathrm{and}{x}_3=1\\ 0& \mathrm{if}{x}_2=1\mathrm{and}{x}_3=0\\ 0& \mathrm{if}{x}_1=0\mathrm{and}{x}_2=0\end{array}.$

It follows that

d<n⇔J[G(d),E(d),H(d)]=1.

Accordingly, to improve the operation of the computing system 110, the multiplication circuit 115 has to be a circuit of FPGAs of minimum possible depth (i.e., number of layers) so that given a fixed weight-value w, the LUTs can be programmed for calculating the product w×d for any input d∈B^1-2:

$\begin{array}{cccccccccccccccccccc}& & & & & & & & d_{11}& d_{10}& d_9& d_8& d_7& d_6& d_5& d_4& d_3& d_2& d_1& d_0\\ & & & & & & & & & & \times & & w_7& w_6& w_5& w_4& w_3& w_2& w_1& w_0\\ p_{19}& p_{18}& p_{17}& p_{16}& p_{15}& p_{14}& p_{13}& p_{12}& p_{11}& p_{10}& p_9& p_8& p_7& p_6& p_5& p_4& p_3& p_2& p_1& p_0\end{array}$

Here, each of the d_i, w_i, and p_i is a bit-value.

FIG. 3 depicts a block diagram of the multiplication circuit according to one or more embodiments of the present invention. The multiplication circuit 115 can be an FPGA in one or more embodiments of the present invention. Alternatively, or in addition, the multiplication circuit 115 can be an application-specific integrated circuit (ASIC), or any other type of electronic circuit that includes transistors, flip-flops, and other such components to implement lookup tables. The multiplication circuit 115, for this particular case of 8-bit 14) and 12-bit d, includes three levels, a first circuit 310, a second circuit 320, and a third circuit 330, each level being a separate circuit. Here, each circuit can be a collection of LUTs implemented by the FPGA. In the case where the w and/or the d has/have a different number of bits, the number of levels in the multiplication circuit 115 can change. The circuits (310, 320, and 330) can communicate auxiliary bit-values among each other to facilitate calculations to be efficient. The circuits (310, 320, and 330) include several LUTs 350 to provide an output based on the input-value d. The LUTs 350 are configured based on the weight-value iv, which is a known value.

FIG. 4 depicts a flowchart of a method for computing the product p of the input-value d and the weight-value))) according to one or more embodiments of the present invention. FIG. 5, FIG. 6, and FIG. 7, each depicts a block diagram of the first circuit 310, the second circuit 320, and the third circuit 330, respectively, according to one or more embodiments of the present invention.

The method 400 includes configuring the several LUTs 350 in the multiplier circuit 115 based on the weight-value iv, at block 402. Each LUT 350 provides an output bit based on a set of input bits. The input bits to the LUT 350 can include one or more bit-values from d. In addition, the input bits to the LUT 350 can include one or more auxiliary bit-values output by another LUT 350. In one or more cases, the auxiliary bit-values from the first circuit 310 are used as input bits to one or more LUTs 350 in the other circuits (320 and 330). Similarly, auxiliary bits from the second circuit 320 can be used as input bits to LUTs 350 of the third circuit 330.

The method 400 includes determining an output of the first circuit 310, at block 410. Part of the output from the first circuit 310 includes a predetermined number of LSBs 510 of p, at block 412. As shown in FIG. 5, in the case with the 12-bit d and 8-bit w, the first circuit 310 computes the first 6-bits of p (p₀ to p₅). The first circuit 310 further determines a first set of auxiliary bit-values (r₆ to r₁₃) 520 that is used as input bit-values to other LUTs 350 from the multiplication circuit 115, at block 414. The LSBs 510 and the first set of auxiliary bit-values 520 are both determined based on the six LSBs of d (d₀ to d₅). The computation of the LSBs 510 and the first set of auxiliary bit-values 520 can be expressed as:

$\begin{array}{cc}\begin{array}{ccccccccccccccc}& & & & & & & & & d_5& d_4& d_3& d_2& d_1& d_0\\ & & & & & \times & & w_7& w_6& w_5& w_4& w_3& w_2& w_1& w_0\\ =& r_{13}& r_{12}& r_{11}& r_{10}& r_9& r_8& r_7& r_6& p_5& p_4& p_3& p_2& p_1& p_0\end{array}& \left(2\right)\end{array}$

Further, the first circuit 310 determines a second set of auxiliary bit-values (q₀ to q₁₃) 530 that is used as input bit-values to other LUTs 350 from the multiplication circuit 115, at block 416. The second set of auxiliary bit-values 520 is determined based on the six most significant bits (MSBs) of d (d₆ to d₁₁). The computation of the second set of auxiliary bit-values 530 can be expressed as:

$\begin{array}{cc}\begin{array}{ccccccccccccccc}& & & & & & & & & d_{11}& d_{10}& d_9& d_8& d_7& d_6\\ & & & & & \times & & w_7& w_6& w_5& w_4& w_3& w_2& w_1& w_0\\ =& q_{13}& q_{12}& q_{11}& q_{10}& q_9& q_8& q_7& q_6& q_5& q_4& q_3& q_2& q_1& q_0\end{array}& \left(3\right)\end{array}$

In addition, the first circuit 310 determines a first ancillary bit-value (q_9.8) 540, at block 418. The first ancillary bit-value is communicated to the second circuit 320 and represents:

q _9.8 =q ₉ ∧q ₈.

the output bit-values of the second circuit 320, at block 420. Part of the output of the second circuit 320 includes a predetermined number of bits 610 of p, at block 422. As shown in FIG. 6, in the case with the 12-bit d and 8-bit w, the second circuit 320 computes p₆ to p₈ (610). The second circuit 320 further determines a second ancillary bit-value (x₉) 620 that is used as input bit-values to other LUTs 350 from the multiplication circuit 115, at block 424. The bit-values 610 and the second ancillary bit-value 620 are both determined based on subsets of the first set of auxiliary bit-values 520 and the second set of auxiliary bit-values 530 (r₈, r₇, r₆, and q₂, q₁, q₀). The computation can be expressed as:

$\begin{array}{cc}\begin{array}{ccccc}& & r_8& r_7& r_6\\ +& & q_2& q_1& q_0\\ =& x_9& p_8& p_7& p_6\end{array}.& \left(4\right)\end{array}$

Further, the second circuit 320 determines a third set of auxiliary bit-values (y₉ to y₁₂) 630, at block 426. The third set of auxiliary bit-values is determined using subsets of the first set of auxiliary bit-values 520 and the second set of auxiliary bit-values 530 (r₁₁, r₁₀, r₉, and q₅, q₄, q₃). The computation can be expressed as:

$\begin{array}{cc}\begin{array}{ccccc}& & r_{11}& r_{10}& r_9\\ +& & q_5& q_4& q_3\\ =& y_{12}& y_{11}& y_{10}& y_9\end{array}& \left(5\right)\end{array}$

The second circuit 320 further determines a third ancillary bit-value (y_10.8) 640 and a fourth ancillary value (y_11.9) 650, at block 427. The ancillary bit-values are used by the third circuit 330. In one or more embodiments of the present invention, the third ancillary bit-value (y_10.8) 640 and the fourth ancillary value (y_11.9) 650 are part of the third set of auxiliary values 630. The ancillary bit-values represent a combination of one or more bit-values from the third set of auxiliary bit-values, and the computation can be expressed as:

y _10.9 =y ₁₀ ∧y ₉

y _11.9 =y ₁₁ ∧y ₁₀ ∧y ₉  (6)

Further, the second circuit 320, using (r₁₃, r₁₂, and q₁₀, q₉, q₈, q₇, q₆), determines a fourth set of auxiliary bit-values (z₁₆ to z₁₂) 660, at block 428. The computation can be expressed as:

$\begin{array}{cc}\begin{array}{cccccc}& 0& 0& 0& r_{13}& r_{12}\\ +& q_{10}& q_9& q_8& q_7& q_6\\ =& z_{16}& z_{15}& z_{14}& z_{13}& z_{12}\end{array}.& \left(7\right)\end{array}$

Further yet, the second circuit 320 further determines a fifth ancillary bit-value (z_14.13) 670 and a sixth ancillary value (z_15.13) 680, at block 429. The computation of the ancillary bit-values can be expressed as:

z _14.13 =z ₁₄ ∧z ₁₃  (8)

z _15.13 =z ₁₅ ∧z ₁₄ ∧z ₁₃.  (9)

Additionally, the bit-value z₁₆ 662 represents the combination:

z ₁₆ =q ₁₀⊗((q₉∧q₈)∧((r₁₃∧q₇)∨(r₁₃∧r₁₂∧q₅)∨(q₇∧r₁₂∧q₆)),  (16)

Here, a⊗b=(a∧¬b)∨(¬a∧b). This implies that q₉ can be replaced by q_9.8=q₉ ∧q₈ for the computation of z₁₆. Accordingly, z₁₆ 662 can be obtained as a function of six input bit-values (r₁₃, r₁₂, and q₁₀, q_9.8, q₇, q₆) to a LUT 350. FIG. 8 depicts the LUT 350 for obtaining z₁₆ 662.

Referring back to FIG. 4, the method 400 further includes determining the remaining bit-values (MSBs) 710 of the product p using the third circuit 330, at block 430. Determining the MSBs 710 includes using several combinations of the input bit-values of d, the sets of auxiliary bit-values, and the several ancillary bit-values computed by the first circuit 310 and the second circuit 320.

The bit p₉ is determined using bits (y₉, x₉) based on:

p ₉ ≡p ₉(y₉,x₉)=(y₉+x₉)(mod 2)

The corresponding LUT 350 is depicted in view 910 of FIG. 9 to determine p₉ based on the input bit-values.

The bit p₁₀ is determined using bits (y₁₀, y₉, x₉) based on:

$p_{10}\equiv p_{10}\left(y_{10},y_9,x_9\right)=\{\begin{array}{cc}{y}_{10}& \mathrm{if}\left(y_9,x_9\right)\ne \left(1,1\right)\\ 1-y_{10}& \mathrm{if}\left(y_9,x_9\right)=\left(1,1\right)\end{array}$

The corresponding LUT 350 is depicted in view 920 of FIG. 9 to determine p₁₀ based on the input bit-values.

The bit p₁₁ is determined using bits (y₁₁, y₁₀, y₉, x₉) based on:

$p_{11}\equiv p_{11}\left(y_{11},y_{10},y_9,x_9\right)=\{\begin{array}{cc}{y}_{11}& \mathrm{if}\left(y_{10},y_9,x_9\right)\ne \left(1,1,1\right)\\ 1-y_{11}& \mathrm{if}\left(y_{10},y_9,x_9\right)=\left(1,1,1\right)\end{array}.$

The dependence of p₁₁ on y₁₀ and y₉ is only to check whether or not (y₁₀, y₉)=(1, 1). Hence, y₁₀ and y₉ can be replaced by the third ancillary bit 640 (y_10.9). The corresponding LUT 350 is depicted in view 930 of FIG. 9 to determine pH based on such input bit-values.

Calculating p₁₂ requires computing the addition:

$\begin{array}{cccccc}& 0& y_{12}& 0& 0& x_9\\ +& 0& z_{12}& y_{11}& y_{10}& y_9\\ =& c_{13}& p_{12}& p_{11}& p_{10}& p_9,\end{array}$

where c₁₃ is not used, and p₉, p₁₀, and p₁₁, are determined as described earlier. Here, the dependence of p₁₂ on y₁₁, y₁₀, and y₉ is only to check whether or not (y₁₁, y₁₀, y₉)=(1, 1, 1). Hence, y₁₁, y₁₀, and y₉ can be replaced by the fourth ancillary bit 650 (y_11.9). The corresponding LUT 350 is depicted in view 940 of FIG. 9 to determine p₁₂ based on such input bit-values.

Calculating p₁₃ requires computing the addition:

$\begin{array}{ccccccc}& 0& 0& y_{12}& 0& 0& x_9\\ +& 0& z_{13}& z_{12}& y_{11}& y_{10}& y_9\\ =& c_{14}& p_{13}& p_{12}& p_{11}& p_{10}& p_9\end{array},$

where c₁₄ is not used, and p₉, p₁₀, p₁₁, and p₁₂, are determined as described earlier. Here, the dependence of p₁₃ on y₁₁, y₁₀, and y₉ is only to check whether or not (y₁₁, y₁₀, y₉)=(1, 1, 1). Hence, y₁₁, y₁₀, and y₉ can be replaced by a single bit—the fourth ancillary bit 650 (y_11.9). Accordingly, p₁₃ can be determined as a function of five variables (z₁₃, z₁₂, y₁₂, y_11.9, x₉). The corresponding LUT 350 is depicted in view 950 of FIG. 9 to determine p₁₃ based on such input bit-values. In view 950, the calculation of c₁₄ is depicted for denotational purposes. However, c₁₄ is not used.

Calculating p₁₄ requires computing the addition:

$\begin{array}{cccccccc}& 0& 0& 0& y_{12}& 0& 0& x_9\\ +& 0& z_{14}& z_{13}& z_{12}& y_{11}& y_{10}& y_9\\ =& c_{15}& p_{14}& p_{13}& p_{12}& p_{11}& p_{10}& p_9\end{array},$

where c₁₅ is not used, and p₉, p₁₀, p₁₁, p₁₂, and p₁₃ are determined as described earlier.

Here, the addition is a function of eight variables. As noted earlier, the technical solutions herein overcome the technical challenge of handling such cases with more than six input bit-values. In this particular case, y₁₁, y₁₀, and y₉ can be replaced by a single bit—the fourth ancillary bit 650 (y_11.9) so that p₁₄ can be determined using the LUT 350 shown in view 1010 of FIG. 10.

Calculating p₁₅ requires computing the addition:

$\begin{array}{ccccccccc}& 0& 0& 0& 0& y_{12}& 0& 0& x_9\\ +& 0& z_{15}& z_{14}& z_{13}& z_{12}& y_{11}& y_{10}& y_9\\ =& c_{16}& p_{15}& p_{14}& p_{13}& p_{12}& p_{11}& p_{10}& p_9\end{array},$

where c₁₆ is not used, and p₉, p₁₀, p₁₁, p₁₂, p₁₃, and p₁₄ are determined as described earlier.

Here, the addition is a function of nine variables. Again, y₁₁, y₁₀, and y₉ can be replaced by a single bit—the fourth ancillary bit 650 (y_11.9). Furthermore, the dependence of p₁₅ on z₁₄ and z₁₃ is only to check whether or not (z₁₄, z₁₃) by the fifth ancillary bit-value 670 (z_14.13) can be determined using the LUT 350 shown in view 1110 of FIG. 11 as a function of six variables.

Calculating p₁₆ requires computing the addition:

$\begin{array}{cccccccccc}& 0& 0& 0& 0& r_{13}& r_{12}& 0& 0& 0\\ +& 0& q_{10}& q_9& q_8& q_7& q_6& 0& 0& x_9\\ & 0& 0& 0& 0& 0& y_{12}& y_{11}& y_{10}& y_9\\ =& c_{17}& p_{16}& p_{15}& p_{14}& p_{13}& p_{12}& p_{11}& p_{10}& p_9\end{array},$

where (q₁₃, . . . , q₆) and (r₁₃, r₁₂) are computed in first circuit 310, and (y₁₂, y₁₁, y₁₀, y₉) and x₉ are computed in the second circuit 320.

As mentioned earlier, the third circuit 330 uses several ancillary bit-values and auxiliary bit-values that are determined by the first circuit 310 and the second circuit 320. For example, the ancillary bit-value (q_10.8) 550 is computed at the first circuit 310 to represent:

q _10.8 =q ₁₀ ∧q ₉ ∧q ₈ =q ₁₀ ·q ₉ ·q ₈.

Further, in the second circuit 320, the result of the following addition can be determined using the LUTs 350:

$\begin{array}{ccccccc}& 0& 0& 0& 0& r_{13}& r_{12}\\ +& 0& q_{10}& q_9& q_8& q_7& q_6\\ =& t_{17}& z_{16}& z_{15}& z_{14}& z_{13}& z_{12}\end{array}$

The result of the addition can be computed as a Boolean function of at most six inputs that are computed in the first circuit 310 as follows:

z ₁₂ =z ₁₂(r₁₂,q₆)

z ₁₃ =z ₁₃(r₁₃,r₁₂,q₇,q₆)

z ₁₄ =z ₁₄(r₁₃,r₁₂,q₈,q₇,q₆)

z ₁₅ =z ₁₅(r₁₃,r₁₂,q₉,q₈,q₇,q₆)

z ₁₆ =z ₁₆(r₁₃,r₁₂,q₁₀,q_9.8,q₇,q₆),

and the bit

z _15.13 =z _15.13(r₁₃,r₁₂,q₉,q₈,q₇,q₆)=z₁₅·z₁₄·z₁₃

The z_15.13 bit-value is the sixth ancillary bit-value 680. The bit p₁₆ can be determined in the third circuit 330 as a Boolean function of six inputs that are determined by the LUTs 350 in the first circuit 310 and/or the second circuit 320:

p ₁₆ =p ₁₆(z₁₆,z_15.13,z₁₂,y₁₂,y_11.9,x₉)

The view 1210 in FIG. 12 depicts the LUT 350 for determining p₁₆ using the above six bit-value input.

Determining the final three MSBs using LUTs 350 is based on the following description of correctness. If N, d, and w, are integers, then:

$\begin{array}{cc}w\times d\ge N\mathrm{if}\mathrm{and}\mathrm{only}\mathrm{if}d\ge \lceil \frac{N}{w}\rceil .& \left(i\right)\\ w\times d<N\mathrm{if}\mathrm{and}\mathrm{only}\mathrm{if}d\le \lfloor \frac{N-1}{w}\rfloor .& \left(\mathrm{ii}\right)\end{array}$

The part (i) above holds true because if

$w\times d\ge N,d\ge \frac{N}{w},\therefore d\ge \lceil \frac{N}{w}\rceil .$

Conversely, if

$d\ge \lceil \frac{N}{w}\rceil ,w\times d\ge w\times \lceil \frac{N}{w}\rceil \ge w\times \frac{N}{w}=N.$

In the case (ii) above, if

$w\times d<N,w\times d\le N-1,\therefore d\le \frac{N-1}{w},\mathrm{and}d\le \lfloor \frac{N-1}{w}\rfloor .$

Conversely, if

$d\le \lfloor \frac{N-1}{w}\rfloor ,w\times d\le w\times \lfloor \frac{N-1}{w}\rfloor \le w\times \frac{N-1}{w}=N-1.$

Now, a description is provided for determining the MSB p₁₉ using two LUTs 350. Consider t=┌2¹⁹/w┐. P₁₉(d)=1↔d≥t. This holds true because P₁₉(d)=1 if and only if w×d≥2¹⁹. It should be noted that here, 19 is used because the result of a 12-bit d and an 8-bit w cannot exceed 2¹⁹. However, in the cases where w or d have a different number of bits, the exponent in the above condition is different. Based on the description herein, a person skilled in the art can determine that for every dεB¹², the function P₁₉(d) can be evaluated using two layers of LUTs 350.

Accordingly, referring back to the flowchart in FIG. 4, the third circuit 330 determines whether d≥t, which can be precomputed as a threshold based on the known w, at block 440. If the condition is satisfied, the p₁₉ is set to 1, at block 442, else p₁₉ is set to 0, at block 444.

FIG. 13 depicts lookup tables for determining p₁₉ according to one or more embodiments of the present invention. The LUTs 350 include a first LUT 1310, a second LUT 1320, and a third LUT 1330 that compares d with the precomputed threshold t. For this purpose, t is represented as t=┌2¹⁹/w┐=u·2⁶+v, where v<2⁶. Further, d is represented as d=g·2⁶+h (g<2⁶, and h<2⁶). Accordingly, setting p₁₉ to 1 if and only if d≥t, implies setting p₁₉ to 1 if and only if ((u<g) OR (g=u AND v≤h)).

Using only 6-to-1 Boolean functions, the first LUT 1310 determines if u<g, the second LUT 1320 determines if g=u and the third LUT 1330 determines if v≤h. The output of the LUTs is a 1, if the respective conditions hold true, and 0 otherwise. Further, a fourth LUT 1340 receives the outputs from the first LUT 1310, the second LUT 1320, and the third LUT 1330. Depending on the received bit-values, the fourth LUT 1340 determines the value of p₁₉.

Now, a description is provided for determining the MSB p₁₈ using two LUTs 350. It should be noted that p₁₈=1, if and only if one of the following conditions holds:

2¹⁸≤w×d<2¹⁹  (i)

2¹⁹+2¹⁸≤w×d  (ii)

The following three thresholds can be precomputed based on the known w:

$t_{01}=\lceil \frac{2^{18}}{w}\rceil t_{10}=\lfloor \frac{2^{19}-1}{w}\rfloor t_{11}=\lceil \frac{2^{19}+2^{18}}{w}\rceil$

Accordingly, the method 400 includes setting p₁₈ to 1, at block 452, and else to 0, at block 454, based on the third circuit 330 determining, at block 450, whether the following condition holds:

t ₀₁ ≤d≤t ₁₀  (i)

t ₁₁ ≤d.  (ii)

The above is further equivalent to setting p₁₈ to 1 if and only if one of the following conditions holds:

(t₀₁<d<t₁₀) or (t₁₁<d)  (i)

d∈{t ₀₁ ,t ₁₀ ,t ₁₁}.  (ii)

Again, consider d represented as d=g·2⁶+h. Let us denote B²={01, 10, 11}, and then, for every β∈B², t_β=u_β·2⁶+v_β, where 0≤v_β≤2⁶. Accordingly, determining the value for p₁₈ can be stated as p₁₈=1 if and only if one of the following conditions holds:

1. g>u₀₁ or (g=u₀₁ and h≥v₀₁)(i.e. d≥t₀₁)

and

2. g<u₁₀ or (g=u₁₀ and h≤v₁₀)(i.e., d≤t₁₀)  (i)

g>u ₁₁ or (g=u₁₁ and h≥v₁₁)(i.e.,d≥t₁₁)  (ii)

This can be simplified as p₁₈=1 if and only if one of the following eight conditions holds:

00:(u₀₁<g<u₁₀) or (u₁₁<g)

01:g=u₀₁ and h≥v₀₁

10:g=u₁₀ and h≤v₁₀

11: g=u₁₁ and h≥v₁₁

Consider the notation, that with any inequality of variables x<y, z≤w, etc., a truth value ∅(x<y)∈{0,1}, where 1 is “true,” and 0 is “false,” and logical connectives can be applied in the form, for example, ∅(x=y)=∅(x≤y)∧∅(x≥y).

Accordingly, the above eight conditions can be succinctly stated as:

P ₁₈(d)=[ϕ(t₀₁≤d)∧ϕ(d≤t₁₀)]∨ϕ(t₁₁≤d).

The values for t₀₁, t₁₀, and t₁₁ can be represented as:

t ₀₁ =u ₀₁·2⁶+v₀₁ where 0≤v₀₁<2⁶,

t ₁₀ =u ₁₀·2⁶+v₁₀ where 0≤v₁₀<2⁶,

t ₁₁ =u ₁₁·2⁶+v₁₁ where 0≤v₁₁<2⁶.

Now, for every β∈{01, 10, 11}, u_β=t_β/2⁶; hence, u₀₁≤u₁₀≤u₁₁. Each possible number g is related to u₀₁, u₁₀, and u₁₁ in one of seven possible ways, which can be labeled with three bits as follows:

(001):g<u₀₁

(010):g=u₀₁

(011):u₀₁<g<u₁₀

(100):g=u₁₀

(101):u₁₀<g<u₁₁

(110):g=u₁₁

(111):u₁₁<g

It follows that given g, the particular case label (x₁, x₂, x₃) can be returned by three 6-to-1 Boolean functions, x₁(g), x₂(g), x₃(g). Given (x₁, x₂, x₃), the information required for the evaluation of P₁₈(d) can be expressed as:

(u₀₁<g)≡x₁∨(¬x₁∧x₂∧x₃)

(u₀₁=g)≡x₁∧¬x₂∧x₃

(g<u₁₀)≡¬x₁

(g=u₁₀)≡x₁∧¬x₂∧¬x₃

(u₁₁<g)≡x₁∧x₂∧x₃

(u₁₁=g)≡x₁∧x₂∧¬x₃

The situation with respect to the relation of h to the v_β is simpler. The only information required for the evaluation of P₁₈(d) is captured by the following 6-to-1 Boolean functions:

$y_1\left(h\right)=\{\begin{array}{cc}1& \mathrm{if}h\ge v_{01}\\ 0& \mathrm{otherwise}\end{array}{y}_2\left(h\right)=\{\begin{array}{cc}1& \mathrm{if}h\le v_{10}\\ 0& \mathrm{otherwise}\end{array}{y}_3\left(h\right)=\{\begin{array}{cc}1& \mathrm{if}h\ge v_{11}\\ 0& \mathrm{otherwise}.\end{array}$

At this stage, it can be shown that for every d∈B¹² the function P₁₈(d) can be evaluated in two layers. The evaluation of P₁₈(d) relies on the inequality relations of d to the t_βs. Accordingly:

d≥t ₀₁↔(g>u₀₁)∨[(g=u₀₁)∧(h≥v₀₁)]

d≤t ₁₀↔(g<u₁₀)∨[(g=u₁₀)∧(h≤v₁₀)]

d≥t ₁₁↔(g>u₁₁)∨[(g=u₁₁)∧(h≥v₁₁)]

Further:

ϕ(d≥t₀₁)=ϕ(g>u₀₁)∨(ϕ(g=u₀₁)∧y₁(h))

ϕ(d≤t₁₀)=ϕ(g<u₁₀)∨(ϕ(g=u₁₀)∧y₂(h))

ϕ(d≥t₁₁)=ϕ(g>u₁₁)∨(ϕg=u₁₁)∨h₃(y))

Thus, it follows that the relations of d to the t_βs can be evaluated by the following 6-to-1 Boolean function, applied to the 6-tuple (x₁(g), x₂(g), x₃(g), y₁(h), y₁(h), y₃(h)).

FIG. 14 depicts lookup tables for determining p₁₈ according to one or more embodiments of the present invention. The LUTs 350 for determining p₁₈ are in a two-layer setup. The LUTs 350 include a first LUT 1410, a second LUT 1420, and a third LUT 1430 that determine x₁(g), x₂(g), x₃(g), respectively. Further, the LUTs 350 include a fourth LUT 1440, a fifth LUT 1450, and a sixth LUT 1460 that determine y₁(h), y₂(h), y₃(h), respectively. The bit-values of the x₁(g), x₂(g), x₃(g), y₁(h), y₂(h), y₃(h), are used to determine p₁₈.

It can be shown that if 1≤w≤256, then u₀₁<u₁₀. That is because even if w=256,

$u_{01}=\lfloor \frac{\lfloor 2^{18}\text{/}256\rfloor }{2^6}\rfloor =\lfloor \frac{2^{10}}{2^6}\rfloor =2^4;\mathrm{and}$ $u_{10}=\lfloor \frac{\lceil \left(2^{19}-1\right)\text{/}256\rceil }{2^6}\rfloor =\lfloor \frac{2^{11}-1}{2^6}\rfloor =2^5-1$

Now, a description is provided for determining the third MSB p₁₇ using three layers of LUTs. p₁₇=1 if and only if one of the following conditions holds:

2¹⁷≤w×d<2¹⁸  (i)

2¹⁸+2¹⁷≤w×d<2¹⁹  (ii)

2¹⁹+2¹⁷≤w×d<2¹⁹+2¹⁷  (iii)

2¹⁹+2¹⁸+2¹⁷≤w×d  (iv)

The conditions can be restated using seven thresholds:

$t_{001}=\lceil \frac{2^{17}}{w}\rceil t_{010}=\lfloor \frac{2^{18}-1}{w}\rfloor t_{011}=\lceil \frac{2^{18}+2^{17}}{2}\rceil t_{100}=\lfloor \frac{2^{19}-1}{w}\rfloor$ $t_{101}=\lceil \frac{2^{19}+2^{17}}{w}\rceil t_{110}=\lfloor \frac{2^{19}+2^{18}-1}{w}\rfloor t_{111}=\lceil \frac{2^{19}+2^{18}+2^{17}}{w}\rceil$

The conditions can be restated using these seven thresholds as:

t ₀₀₁ ≤d≤t ₀₁₀  (i)

t ₀₁₁ ≤d≤t ₁₀₀  (ii)

t ₁₀₁ ≤d≤t ₁₁₀  (iii)

t ₁₁₁ ≤d.  (iv)

Referring to the flowchart in FIG. 4, method 400 includes setting p₁₇=1, at block 462, if the above conditions using the thresholds are met, at block 460; otherwise, p₁₇=0, at block 464. The conditions can be further restated as p₁₇=1 if and only if one of the following conditions holds:

(t₀₀₁<d<t₀₁₀) or (t₀₁₁<d<t₁₀₀) or (t₁₀₁<d<t₁₁₀) or (t₁₁₁<d)  (i)

d∈{t ₀₀₁ ,t ₀₁₀ ,t ₀₁₁ ,t ₁₀₀ ,t ₁₁₀ ,t ₁₁₁}.  (ii)

Again, consider d represented as d=g·2⁶+h. Let us denote B³={001, 010, 011, 100, 101, 110, 111}, and then, for every β∈B³, t_β=u_β·2⁶+v_β, where 0≤v_β≤2⁶. Accordingly, determining the value for p₁₈ can be stated as p₁₇=1 if and only if one of the following conditions holds:

1. g>u₀₀₁ or (g=u₀₀₁ and h≥v₀₀₁)(i.e., d≥t₀₀₁)

and

2. g<u₀₁₀ or (g=u₀₁₀ and h≤v₀₁₀)(i.e., d≤t₀₁₀)  (i)

1. g>u₀₁₁ or (g=u₀₁₁ and h≥v₀₁₁)(i.e., d≥t₀₁₁)

and

2. g<u₁₀₀ or (g=u₁₀₀ and h≤v₁₀₀)(i.e., d≤t₁₀₀)  (ii)

1. g>u₁₀₁ or (g=u₁₀₁ and h≥v₁₀₁)(i.e., d≥t₁₀₁)

and

2. g<u₁₁₀ or (g=u₁₁₀ and h≤v₁₁₀)(i.e., d≤t₁₁₀)  (iii)

g<u ₁₁₁ or (g=u₁₁₁ and h≥v₁₁₁)(i.e., d≥t₁₁₁).

This can be simplified as p₁₇=1 if and only if one of the following eight conditions holds:

000:(u₀₀₁<g<u₀₁₀) or (u₀₁₁<g<u₁₀₀) or (u₁₀₁<g<u₁₁₀) or (u₁₁₁<g)

001:g=u₀₀₁ and h≥v₀₀₁

010:g=u₀₁₀ and h≤v₀₁₀

011:g=u₀₁₁ and h≥v₀₁₁

100:g=u₁₀₀ and h≤v₁₀₀

101:g=u₁₀₁ and h≥v₁₀₁

110:g=u₁₁₀ and h≤v₁₁₀

111:g=u₁₁₁ and h≥v₁₁₁

Any Boolean function of (x₁, . . . , x₄) is also a Boolean function of g, so it can be evaluated in the first circuit 310. Accordingly, to compress the representation to three bits based on the following:

If g satisfies one of the following, then P₁₇(d)=1:

u ₀₀₁ <g<u ₀₁₀  (i)

u ₀₁₁ <g<u ₁₀₀  (ii)

u ₁₀₁ <g<u ₁₁₀  (iii)

u ₁₁₁ <g  (iv)

If g satisfies one of the following, then P₁₇(d)=0:

g<u ₀₀₁  (i)

u ₀₁₀ <g<u ₀₁₁  (ii)

u ₁₀₀ <g<u ₁₀₁  (iii)

u ₁₁₀ <g<u ₁₁₃  (iv)

However, this still needs encoding of seven possible equalities, namely g=u_β, β∈B³, and so, three bits cannot be used to encode nice cases. However, for every E B³, the case g=u_p can be encoded by 0β; for example, g=u₀₁₁ is encoded by 011. Accordingly, the case for P₁₇(d)=1 can be encoded by:

(u₀₀₁<g<u₀₁₀) or (u₀₁₁<g<u₁₀₀) or (u₁₀₁<g<u₁₁₀) or (u₁₁₁<g)

Additionally, the case for P₁₇(d)=0 can be encoded by:

(u₀₁₀<g<u₀₁₁) or(u₁₀₀<g<u₁₀₁) or(u₁₁₀<g<u₁₁₁)

This four-bit encoding is denoted as (z₁, z₂, z₃, z₄). The encoding is depicted by view 1510 in FIG. 15. Thus, the four Boolean functions are:

z ₁=ϕ(u₀₀₁<g<u₀₁₀)∨ϕ(u₀₁₁<g<u₁₀₀)∨ϕ(u₁₀₁<g<u₁₁₀)∨ϕ(u₁₁₁<g)

z ₂=ϕ(g=u₁₀₀)∨ϕ(g=u₁₀₁)∨ϕ(g=u₁₁₀)∨ϕ(g=u₁₁₁)

z ₃=ϕ(g=u₀₁₀)∨ϕ(g=u₀₁₁)∨ϕ(g=u₁₁₀)∨ϕ(g=u₁₁₁)

z ₄=ϕ(g=u₀₀₁)∨ϕ(g=u₀₁₁)∨ϕ(g=u₁₀₁)∨ϕ(g=u₁₁₁)

The situation with respect to the relation of h to the v_βs is simpler but more complicated than the case of p₁₈. Here, the following truth-values are required:

ϕ(h≥v₀₀₁),ϕ(h≤v₀₁₀),

ϕ(h≥v₀₁₁),ϕ(h≤v₁₀₀),

ϕ(h≥v₁₀₁),ϕ(h≤v₁₁₀),

ϕ(h≥v₁₁₁).

Let v₁<v₂< . . . <v_l (l≤7) be the distinct elements of {v_β:β∈B³} and let ψ(β)∈{1, . . . , l} be the index such that v_ψ(β)=v_β. Thus, the above seven values can be expressed as:

ϕ(h≥v_ψ(001)),ϕ(h≤v_ψ(010)),

ϕ(h≥v_ψ(011)),ϕ(h≤v_ψ(100)),

ϕ(h≥v_ψ(101)),ϕ(h≤v_ψ(110)),

ϕ(h≥v_ψ(111)),

The relations of h to all of these seven values can be captured by three bits (y₁, y₂, y₃) as follows. First note, that each occurrence of v_β is involved in precisely one inequality, namely, depending on β either ∅(h≥v_p) has to be known or ∅(h≤v_p) has to be known. The former occurs when β∈{001, 011, 101, 111}, and the latter when β∈{010, 100, 110}. Therefore, there are precisely seven cases that are needed to characterize the location of h with respect to v₁<v₂< . . . <v_l so that the information required is retrieved. The cases can be viewed as a partition of the set {0, 1, . . . , 63} into at most eight intervals, some of which may consist of a single point. These seven cases are defined by inserting the seven inequality signs that occur in the above seven conditions in the appropriate places. The inequality signs also take into account v₁, . . . , v_l as follows. Let 1≤i≤1, and consider a certain value v_i. If i=ψ(β), then (i) if β∈{001, 011, 101, 111}, then include an inequality≤v_i, and (ii) if β∈{010, 100, 110}, then include an inequality v_i≤. If there exists β₁∈{001, 011, 101, 111}, and β₂ ∈{010,100,110}, such that i=ψ(β₁)=ψ(β₂), then two inequalities are included: ≤v_i, and v_i≤. If it has to be known whether or not h≤v_β, then in the partition v_β must be the right endpoint of one of the intervals, and if it has to be known whether or not h≥v_β, then in the partition v_β must be the left endpoint of one of the intervals. This way, if it is known which of the intervals contains h, then the information that is required about its relation to any v_β is known. For example, suppose:

v₀₀₁=3 v₀₁₀=4v₀₁₁=7 v₁₀₀=8v₁₀₁=11 v₁₁₀=12v₁₁₁=15

Here, it is to be determined whether or not h≥3, whether or not h<4, whether or not h≥7, whether or not h≤8, whether or not h≥11, whether or not h≤12, and whether or not h≥15. Therefore, the partition into eight intervals is the following:

000:0≤h≤2

001:3≤h≤4

010:5≤h≤6

011:7≤h≤8

100:9≤h≤10

101:11≤h≤12

110:13≤h≤14

111:15≤h≤63

The labels on the left provide the encoding with three bits, so the corresponding three Boolean functions are represented in view 1520 in FIG. 15. The Boolean functions b₁, b₂, and b₃ are the following:

b ₁(h)=ϕ(9≤h≤63)

b ₂(h)=ϕ(5≤h≤8)∨ϕ(13≤h≤63)

b ₃(h)=ϕ(3≤h≤4)∨ϕ(7≤h≤8)∨ϕ(11≤h≤12)∨ϕ(15≤h≤63).

Thus, it follows that the relations of d to the t_βs can be evaluated by a single 7-to-1 Boolean function ƒ(z₁, . . . , z₄, b₁, b₂, b₃). This evaluation can be carried out as follows. First, a Boolean function ƒ(z₂, z₃, z₄, b₁, b₂, b₃) is defined and implemented in the second circuit 320 by setting its value to 1 when (z₂, z₃, z₄)≠(0, 0, 0), and every x in the interval indicated by (b₁, b₂, b₃) satisfies the bound on h that is required given that g has the value indicated by (z₂, z₃, z₄); otherwise, ƒ(z₂, z₃, z₄, b₁, b₂, b₃)=0. In the third circuit 330, the value of P₁₇ is set to 1 if z₁=1 or ƒ(z₂, z₃, z₄, b₁, b₂, b₃)=1; otherwise, P₁₇ is set to 0.

FIG. 16 depicts a three-layer LUT circuit for determining p₁₇ according to one or more embodiments of the present invention. The LUTs 350 include a set of four LUTs—a first LUT 1610, a second LUT 1620, a third LUT 1630, and a fourth LUT 1640—for determining results of z₁, z₂, z₃, and z₄, respectively by comparing portions of g and u as described above. Further, the LUTs 350 include another set of three LUTs—a fifth LUT 1650, a sixth LUT 1660, and a seventh LUT 1670—for determining b₁, b₂, b₃, respectively by encoding h as described above. An eighth LUT 1680 uses the z₂, Z₃, Z₄, and b₁, b₂, b₃ to determine an output a₁. A ninth LUT 1690 uses z₁ and a₁ to determine p₁₇.

Accordingly, embodiments of the present invention provide a circuit of 6-input Boolean gates for multiplying a given (known) Boolean vector w=(w₇, w₆, w₅, w₄, w₃, w₂, w₁, w₀) by any Boolean input vector d=(d₁₁, d₁₀, d₉, d₈, d₇, d₆, d₅, d₄, d₃, d₂, d₁, d₀). w has a predetermined length, for example, eight bits. d has a predetermined length, for example, twelve bits. By implementing the circuit using LUTs, for example, in an FPGA, an ASIC, or any other electronic circuit or device, embodiments of the present invention improve the efficiency of determining the product result in lesser time than performing the computation. The circuit can be used in a variety of computing environments, such as a neural network system, a computing device, a quantum computer, a mainframe computer, a memory controller, or any other type of apparatus that requires computing multiplications, and particularly where one of the numbers in the multiplication is a known value.

Further, embodiments of the present invention use FPGAs that limit each of the LUTs to use at most six inputs. Accordingly, embodiments of the present invention facilitate a practical application of determining a multiplication result and improving the efficiency of such computations performed by present solutions. Embodiments of the present invention, accordingly, provide an improvement to a particular technology, in this case, computing technology. Further yet, embodiments of the present invention facilitate improvements to present solutions such as neural networks and other types of computing systems by improving their efficiency at computing such multiplications, the results of which are used in various applications.

The neural network system 200 can be implemented using a computer system or any other apparatus. Turning now to FIG. 17, a computer system 1700 is generally shown in accordance with an embodiment. The computer system 1700 can be an electronic, computer framework comprising and/or employing any number and combination of computing devices and networks utilizing various communication technologies, as described herein. The computer system 1700 can be easily scalable, extensible, and modular, with the ability to change to different services or reconfigure some features independently of others. The computer system 1700 may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, the computer system 1700 may be a cloud computing node. Computer system 1700 may be described in the general context of computer system executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system 1700 may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

As shown in FIG. 17, the computer system 1700 has one or more central processing units (CPU(s)) 1701a, 1701b, 1701c, etc. (collectively or generically referred to as processor(s) 1701). The processors 1701 can be a single-core processor, multi-core processor, computing cluster, or any number of other configurations. The processors 1701, also referred to as processing circuits, are coupled via a system bus 1702 to a system memory 1703 and various other components. The system memory 1703 can include a read-only memory (ROM) 1704 and a random access memory (RAM) 1705. The ROM 1704 is coupled to the system bus 1702 and may include a basic input/output system (BIOS), which controls certain basic functions of the computer system 1700. The RAM is read-write memory coupled to the system bus 1702 for use by the processors 1701. The system memory 1703 provides temporary memory space for operations of said instructions during operation. The system memory 1703 can include random access memory (RAM), read-only memory, flash memory, or any other suitable memory systems.

The computer system 1700 comprises an input/output (I/O) adapter 1706 and a communications adapter 1707 coupled to the system bus 1702. The I/O adapter 1706 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 1708 and/or any other similar component. The I/O adapter 1706 and the hard disk 1708 are collectively referred to herein as a mass storage 1710.

Software 1711 for execution on the computer system 1700 may be stored in the mass storage 1710. The mass storage 1710 is an example of a tangible storage medium readable by the processors 1701, where the software 1711 is stored as instructions for execution by the processors 1701 to cause the computer system 1700 to operate, such as is described hereinbelow with respect to the various Figures. Examples of computer program product and the execution of such instruction is discussed herein in more detail. The communications adapter 1707 interconnects the system bus 1702 with a network 1712, which may be an outside network, enabling the computer system 1700 to communicate with other such systems. In one embodiment, a portion of the system memory 1703 and the mass storage 1710 collectively store an operating system, which may be any appropriate operating system, such as the z/OS or AIX operating system from IBM Corporation, to coordinate the functions of the various components shown in FIG. 17.

Additional input/output devices are shown as connected to the system bus 1702 via a display adapter 1715 and an interface adapter 1716 and. In one embodiment, the adapters 1706, 1707, 1715, and 1716 may be connected to one or more I/O buses that are connected to the system bus 1702 via an intermediate bus bridge (not shown). A display 1719 (e.g., a screen or a display monitor) is connected to the system bus 1702 by a display adapter 1715, which may include a graphics controller to improve the performance of graphics intensive applications and a video controller. A keyboard 1721, a mouse 1722, a speaker 1723, etc. can be interconnected to the system bus 1702 via the interface adapter 1716, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit. Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Thus, as configured in FIG. 17, the computer system 1700 includes processing capability in the form of the processors 1701, and, storage capability including the system memory 1703 and the mass storage 1710, input means such as the keyboard 1721 and the mouse 1722, and output capability including the speaker 1723 and the display 1719.

In some embodiments, the communications adapter 1707 can transmit data using any suitable interface or protocol, such as the internet small computer system interface, among others. The network 1712 may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. An external computing device may connect to the computer system 1700 through the network 1712. In some examples, an external computing device may be an external web server or a cloud computing node.

It is to be understood that the block diagram of FIG. 17 is not intended to indicate that the computer system 1700 is to include all of the components shown in FIG. 17. Rather, the computer system 1700 can include any appropriate fewer or additional components not illustrated in FIG. 17 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Further, the embodiments described herein with respect to computer system 1700 may be implemented with any appropriate logic, wherein the logic, as referred to herein, can include any suitable hardware (e.g., a processor, an embedded controller, or an application-specific integrated circuit, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware, in various embodiments.

The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer-readable program instructions described herein can be downloaded to respective computing/processing devices from a computer-readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing/processing device.

Computer-readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source-code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer-readable program instruction by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general-purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer-implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.

Various embodiments of the invention are described herein with reference to the related drawings. Alternative embodiments of the invention can be devised without departing from the scope of this invention. Various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.

The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” may be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The terms “a plurality” may be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term “connection” may include both an indirect “connection” and a direct “connection.”

The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5% or 2% of a given value.

For the sake of brevity, conventional techniques related to making and using aspects of the invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs to implement the various technical features described herein are well known. Accordingly, in the interest of brevity, many conventional implementation details are only mentioned briefly herein or are omitted entirely without providing the well-known system and/or process details.

Claims

1. A method for multiplying two binary numbers, the method comprising: configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w), the lookup tables being configured in three layers;receiving, by the integrated circuit, an input binary number (d); anddetermining, by the integrated circuit, a binary multiplication result (p) of the known binary number w and the input binary number d by determining each bit (pi) from p using the lookup tables, based on a specific combination of bits from the known binary number w and from the input binary number d, wherein the notation jx is binary notation to represent the xth rightmost bit of a binary number j, bit j0 being the rightmost bit of j.

2. The method of claim 1, wherein the known binary number w is an 8-bit binary number.

3. The method of claim 1, wherein the input binary number d has a predetermined number of bits.

4. The method of claim 3, wherein the input binary number d is a 12-bit binary number.

5. The method of claim 4, wherein the input binary number d is received from a 12-bit image sensor.

6. The method of claim 1, wherein bits p5, p4, p3, p2, p1, and p0 of the multiplication result p are determined by a first circuit from the integrated circuit based on bits d5, d4, d3, d2, d1, and do of the input binary number d, the first circuit comprising a first one of the layers of the lookup tables.

7. The method of claim 6, wherein bits p8, p7, and p6, of the multiplication result p are determined by a second circuit from the integrated circuit based on a first set of auxiliary bits computed by the first circuit, the second circuit comprising a second one of the layers of the lookup tables.

8. The method of claim 7, wherein bits p16, p15, p14, p13, p12, p11, and p10 of the multiplication result p are determined by a third circuit from the integrated circuit based on auxiliary bits computed by the second circuit, the third circuit comprising a third one of the layers of the lookup tables.

9. The method of claim 8, wherein determining bit p19 of the multiplication result p comprises: determining, by using a subset of the lookup tables, that t≤d, wherein t=┌219/w┐ is a precomputed threshold, and d is the input binary number; andin response to t≤d, setting p19 to 1, and otherwise setting p19 to 0.

10. The method of claim 8, wherein determining bit p18 of the multiplication result p comprises: precomputing threshold values t01, t10, and t11 using the known binary number w: t01=┌218/w┐, t10=└(219−1)/w┘, andt11=┌(219+218)/w┐; andin response to (t11≤d) or (t01≤d≤t10), setting the bit p18 to 1, and otherwise setting the bit p18 to 0, d being the input binary number.

11. The method of claim 8, wherein determining bit p17 of the multiplication result p comprises: precomputing a plurality of threshold values using the known binary number w: t001=┌217/w┐, t010=└(218−1)/w┘, t011=┌(218+217)/w┐, t100=└(219−1)/w┘, t101=┌(219+217)/w┐, t110=└(219+218−1)/w┘, andt111=┌(219+218+217)/w┐; andsetting the bit p17 to 1 in response to a subset of the plurality of threshold values: t111≤d, t101≤d≤t110,t011≤d≤t100, andt001≤d≤t010; andsetting p17 to 0 otherwise, wherein d is the input binary number.

12. A system comprising: a memory device that stores a known binary number (w); anda multiplication circuit that is configured to perform a method to determine a multiplication result (p) of the known binary number w with an input binary number (d) that is received dynamically, the method comprising: configuring a plurality of lookup tables in the multiplication circuit based on the known binary number w, wherein the lookup tables are setup in three layers; anddetermining the multiplication result p of the known binary number w and the input binary number d using the lookup tables, wherein each bit (pi) from the multiplication result p is determined from the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein jx is a binary notation that represents the xth rightmost bit of j, with bit j0 being the rightmost bit of j.

13. The system of claim 12, wherein bits p5, p4, p3, p2, p1, and p0 of the multiplication result p are determined by a first layer of the lookup tables from the multiplication circuit based on bits d5, d4, d3, d2, d1, and d0 of input binary number d.

14. The system of claim 13, wherein the bits p8, p7, and p6, of the multiplication result p, are determined by a second layer of the lookup tables from the multiplication circuit based on a first set of auxiliary bits computed by the first layer.

15. The system of claim 14, wherein bits p16, p15, p14, p13, p12, p11, and p10 of the multiplication result p are determined by a third layer of the lookup tables from the multiplication circuit based on auxiliary bits computed by the second layer.

16. The system of claim 13, wherein determining bit p19 of the multiplication result p comprises: determining, using a subset of lookup tables, that t≤d, wherein t=┌219/w┐ is a precomputed threshold; andin response to t≤d, setting p19 to 1, and otherwise setting the bit p19 to 0, d being the input binary number.

17. The system of claim 13, wherein determining bit p18 of the multiplication result p comprises: precomputing a plurality of threshold values t01, t10, and t11 based on the known binary number w: t01=┌218/w┐, t10=└(219−1)/w┘, andt11=┌(219+218)/w┐; andin response to (t11≤d) or (t01≤d≤t10), setting the bit p18 to 1, and otherwise setting the bit p18 to 0, wherein d is the input binary number.

18. The system of claim 11, wherein determining bit p17 of the multiplication result p comprises: precomputing a plurality of threshold values using the known binary number: t001=┌217/w┐, t010=└(218−1)/w┘, t011=┌(218+217)/w┐, t100=└(219−1)/w┘, t101=┌(219+217)/w┐, t110=└(219+218−1)/w┘, andt111=┌(219+218+217)/w┐; andsetting the bit p17 to 1 in response to: t111≤d, t101≤d≤t110,t011≤d≤t100, andt001≤d≤t010; andsetting the bit p17 to 0 otherwise, wherein d is the input binary number.

19. A neural network system comprising: a multiplication circuit configured to determine a multiplication result (p) of multiplying a weight value (w) that has a known value with an input value (d) that is received dynamically, wherein, p, d, and w are binary numbers, determining the multiplication result p comprises:configuring a plurality of lookup tables in an integrated circuit based on the weight value w that is a known value, the lookup tables are arranged in three layers; andoutputting the multiplication result p using the lookup tables, wherein each bit of the multiplication result p is independently determined from the lookup tables based on specific combination of bits from the weight value w and from the input value d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.

20. The neural network system of claim 19, wherein the integrated circuit is a field programmable gate array.

21. The neural network system of claim 20, wherein each of the lookup tables receives at most 6 input bit-values and outputs a single bit-value in response.

22. An electronic circuit for determining a multiplication result (p) of a weight value (w) and an input value (d) that is received dynamically, wherein determining the multiplication result comprises: configuring a plurality of lookup tables based on the weight value (w), wherein the lookup tables are configured in three layers; andoutputting a respective bit (pi) of the multiplication result (p) using the lookup tables based on specific combination of bits from the weight value w and from the input value d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.

23. The electronic circuit of claim 22, wherein: a first subset of the lookup tables determines bits p5, p4, p3, p2, p1, and p0 of the multiplication result p;a second subset of the lookup tables determines bits p8, p7, and p6, of the multiplication result p;a third subset of the lookup tables determines bits p16, p15, p14, p13, p12, p11, and p10 of the multiplication result p; anda fourth subset of the lookup tables determines bits p19, p18, and p17 of the multiplication result p.

24. A device comprising: a field programmable gate array that includes a plurality of lookup tables configured in three layers to realize a multiplication circuit for two binary numbers.

25. The field programmable gate array of claim 24, wherein each of the lookup tables includes at most 6 inputs.

26. A method comprising: using the device of claim 24 to multiply (i) a 12-bit variable input binary number by (ii) an 8-bit known value binary number.

27. The method of claim 26, wherein the input binary number is obtained from a 12-bit sensor.