1. Field of the Invention
The invention relates to flash memory devices, and more particularly to multiple-level-cell (MCL) flash memory devices.
2. Description of the Related Art
NAND flash memories are classified into single-level-cell (SLC) flash memories and multiple-level-cell (MLC) flash memories. A memory cell of a SLC flash memory can only store a single data bit. A memory cell of an MLC flash memory, however, can store a plurality of data bits. When an MLC flash memory has the same number of memory cells as that of an SLC flash memory, the MLC flash memory has greater data storage capacity than that of the SLC flash memory. The MLC flash memory therefore has lower manufacturing cost than the SLC flash memory.
An MLC flash memory comprises a plurality of blocks, and each of the blocks comprises a plurality of pages for storing data. The pages of the MLC flash memory are divided into weak pages and strong pages. An MLC flash memory has the same number of strong pages and weak pages. Weak pages have lower data endurance, lower data retention, and a slower data access speed than those of strong pages. In general, pages of an SLC flash memory have higher data endurance, higher data retention, and a faster data access speed than those of an MLC flash memory.
Data used by a host can be roughly divided into system data and user data. System data has higher importance and requires storage in a storage area with higher data endurance, higher data retention, and a faster data access speed. User data requires storage in a storage area with greater storage capacity. To meet requirements of system data and user data, a conventional flash memory device needs to be equipped with two kinds of flash memories respectively corresponding to system data and user data. Referring to
Because the conventional flash memory device 104 comprises two kinds of flash memories 114 and 116, the conventional flash memory device 104 has high circuit design complexity. For example, the flash memories 114 and 116 may require different data buses and chip enable circuits. A circuit design with higher complexity increases manufacturing costs of the conventional flash memory device 100. A flash memory device comprising a single flash memory which has two data storage areas with different properties respectively suiting system data and user data is therefore required.
The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, writes the data to the strong pages of the first blocks of the turbo area when the data is important data, and writes the data to the pages of the second blocks of the normal area when the data is not important data.
The invention also provides a method for writing data to a flash memory device. In one embodiment, the flash memory device is coupled to a host. First, a plurality of blocks of a multiple-level-cell (MLC) flash memory is divided into a plurality of first blocks of a turbo area and a plurality of second blocks of a normal area, wherein each of the first blocks and the second blocks comprises a plurality of pages, and the pages of the first blocks and the second blocks are classified into strong pages with high data endurance and weak pages with low data endurance. Data to be written to the MLC flash memory is then received from the host. Whether the data is important data is then determined. When the data is important data, the data is then written to the strong pages of the first blocks of the turbo area. When the data is not important data, the data is then written to the pages of the second blocks of the normal area.
The invention also provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a plurality of multiple-level-cell (MLC) flash memory and a controller. Each of the MLC flash memories comprises a turbo area and a normal area, wherein the turbo area and the normal area comprises a plurality of blocks, each of the blocks comprises a plurality of pages, and the pages are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the flash memory device from the host, determines whether the data is important data, writes the data to the strong pages of a plurality of first blocks of the turbo areas of the MLC flash memories when the data is important data, and writes the data to the pages of a plurality of second blocks of the normal areas of the MLC flash memories when the data is not important data, wherein the first blocks have the same indexes in the MLC flash memories, and the second blocks have the same indexes in the MLC flash memories.
The invention also provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a turbo multiple-level-cell (MLC) flash memory and a controller. The turbo MLC flash memory comprises a plurality of first blocks, wherein each of the first blocks comprises a plurality of pages, and the pages of the first blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The MLC flash memory comprises a plurality of second blocks, wherein each of the second blocks comprises a plurality of pages. The controller receives data to be stored into the flash memory device from the host, determines whether the data is important data, writes the data to the strong pages of the first blocks of the turbo MLC flash memory when the data is important data, and writes the data to the pages of the second blocks of the MLC flash memory when the data is not important data.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Referring to
The pages of the blocks 231˜23M and 251˜25N are divided into strong pages and weak pages. Referring to
To increase the data access speed for accessing data stored in the turbo area, and increase data endurance and data retention of blocks 231˜23M of the turbo area 222, the controller 212 only stores data in the strong pages of the blocks 231˜23M of the turbo area 222. Because strong pages have higher data endurance, higher data retention, and a faster data access speed, the performance of the turbo area 222 of the MLC flash memory 214 is maximized. In one embodiment, the data endurance of the turbo area 222 is increased by 5 times than that of the normal area 224, and the data retention of the turbo area 222 is increased by 5˜10 times than that of the normal area 224. Because the controller 212 only uses strong pages of the turbo area 222 for data storage, the data capacity of the turbo area 222 is reduced by half.
When the controller 212 stores data to the blocks 251˜25N of the normal area 224, the controller 212 equally stores data to strong pages and weak pages of the blocks 251˜25N to maximize the data storage capacity of the normal area 224. The MLC flash memory 214 therefore has a turbo area 222 with a higher data access speed and a normal area 224 with greater data storage capacity. In one embodiment, to avoid the blocks 231˜23M of the turbo area 222 from being exchanged with the blocks 251˜25N of the normal area 224, the controller 212 independently performs wear-leveling on the blocks 231˜23M of the turbo area 222, independently performs wear-leveling on the blocks 251˜25N of the normal area 224, and does not perform wear-leveling between the blocks 231˜23M of the turbo area 222 and the blocks 251˜25N of the normal area 224. In addition, the controller 212 maintains an address link table for recording a mapping relationship between the logical addresses and physical addresses of the blocks 231˜23M of the turbo area 222, and maintains an address link table for recording a mapping relationship between the logical addresses and physical addresses of the blocks 251˜25N of the normal area 224.
Referring to
Assume that a logical address range used by the host 202 is from 0 to 4095, and the boundary value is set to 1024. The first logical address range is therefore from 0 to 1023, and the second logical address range is from 1024 to 4095. The controller 212 then compares a logical address of the received data with the boundary value to determine whether the received data is important data. In one embodiment, when the logical address of the data is less than the boundary value, the logical address of the data falls in the first logical address range, and the controller 212 determines that the data is important data.
The controller 212 then determines whether the data is to be written to the turbo area 222 or the normal area 224 of the MLC flash memory 214. When the controller 212 determines that the data is important data, the controller 212 obtains a target block from a plurality of blocks 231˜23M of the turbo area 222 (step 406), and writes the data to a plurality of strong pages of the target block (step 408). In one embodiment, after the target block is obtained, the controller 212 selects a plurality of target pages from pages of the target block, determines whether the target pages are strong pages, and writes the data to the target pages when the target pages are strong pages. When the controller 212 determines that the data is not important data, the controller 212 obtains a target block from a plurality of blocks 251˜25N of the normal area 224 (step 412), and writes the data to a plurality of pages of the target block (step 414) without determining whether the pages are strong pages or weak pages.
Referring to
The controller 501 respectively enables the MLC flash memories 502 and 504 by respectively enabling chip enable signals CE1 and CE2. When the controller 501 receives data from a host, the controller 501 determines whether the data is important data as described in step 404 of the method 400. When the data is important data, the controller 501 writes data to strong pages of corresponding blocks of the turbo areas 520 and 540 in the MLC flash memories 502 and 504. When the data is not important data, the controller 501 writes data to pages of corresponding blocks of the normal areas 530 and 550 in the MLC flash memories 502 and 504. Because the flash memory device 500 has a single data bus for transmitting data, the controller 501 alternately enables the MLC flash memories 502 and 504, and then alternately writes data to pages of corresponding blocks of the MLC flash memories 502 and 504.
In one embodiment, the controller 501 writes odd sectors of the data to a Y-th strong page of an X-th block of the turbo area 520 of the MLC flash memory 502, and writes even sectors of the data to a Y-th strong page of an X-th block of the turbo area 540 of the MLC flash memory 504. In another embodiment, the controller 501 writes odd bytes of the data to a Y-th strong page of an X-th block of the turbo area 520 of the MLC flash memory 502, and writes even bytes of the data to a Y-th strong page of an X-th block of the turbo area 540 of the MLC flash memory 504. In addition, to prevent the blocks 521˜52M and 541˜54M of the turbo areas 520 and 540 from being exchanged with the blocks 531˜53N and 551˜55N of the normal areas 530 and 550, the controller 501 independently performs wear-leveling on the blocks 521˜52M and 541˜54M of the turbo areas 520 and 540, and independently performs wear-leveling on the blocks 531˜53N and 551˜55N of the normal areas 530 and 550.
Referring to
The controller 601 writes data to the MLC flash memory 602 via the data bus D1, and writes data to the MLC flash memory 604 via the data bus D2. When the controller 601 receives data from a host, the controller 601 determines whether the data is important data as step 404 of the method 400. When the data is important data, the controller 601 writes data to strong pages of corresponding blocks of the turbo areas 620 and 640 in the MLC flash memories 602 and 604. When the data is not important data, the controller 601 writes data to pages of corresponding blocks of the normal areas 630 and 650 in the MLC flash memories 602 and 604. The controller 601 alternately writes data to pages of corresponding blocks of the MLC flash memories 602 and 604.
In one embodiment, the controller 601 writes odd sectors of the data to a Y-th strong page of an X-th block of the turbo area 620 of the MLC flash memory 602, and writes even sectors of the data to a Y-th strong page of an X-th block of the turbo area 640 of the MLC flash memory 604. In another embodiment, the controller 601 writes odd bytes of the data to a Y-th strong page of an X-th block of the turbo area 620 of the MLC flash memory 602, and writes even bytes of the data to a Y-th strong page of an X-th block of the turbo area 640 of the MLC flash memory 604. In addition, to prevent the blocks 621˜62M and 641˜64M of the turbo areas 620 and 640 from being exchanged with the blocks 631˜63N and 651˜65N of the normal areas 630 and 650, the controller 601 independently performs wear-leveling on the blocks 621˜62M and 641˜64M of the turbo areas 620 and 640, and independently performs wear-leveling on the blocks 631˜63N and 651˜65N of the normal areas 630 and 650.
Referring to
The controller 701 enables the turbo MLC flash memories 720 and 740 via a chip enable signal CE1, and enables the MLC flash memories 730 and 750 via a chip enable signal CE2. When the chip enable signal CE1 is enabled, the controller 701 sends data to the turbo MLC flash memory 720 via the data bus D1, and sends data to the turbo MLC flash memory 740 via the data bus D2. When the chip enable signal CE2 is enabled, the controller 701 sends data to the MLC flash memory 730 via the data bus D1, and sends data to the MLC flash memory 750 via the data bus D2. When the controller 701 receives data from a host, the controller 701 determines whether the data is important data as step 404 of the method 400. When the data is important data, the controller 701 writes the data to strong pages of corresponding blocks of the turbo MLC flash memories 720 and 740. When the data is not important data, the controller 701 writes the data to pages of corresponding blocks of the MLC flash memories 730 and 750.
In one embodiment, the controller 701 writes odd sectors of the data to a Y-th strong page of an X-th block of the turbo MLC flash memory 720, and writes even sectors of the data to a Y-th strong page of an X-th block of the turbo MLC flash memory 740. In another embodiment, the controller 601 writes odd bytes of the data to a Y-th strong page of an X-th block of the turbo MLC flash memory 720, and writes even bytes of the data to a Y-th strong page of an X-th block of the turbo MLC flash memory 740. In addition, to prevent the blocks 721˜72M and 741˜74M of the turbo MLC flash memories 720 and 740 from being exchanged with the blocks 731˜73N and 751˜75N of the MLC flash memories 730 and 750, the controller 701 independently performs wear-leveling on the blocks 721˜72M and 741˜74M of the turbo MLC flash memories 720 and 740, and independently performs wear-leveling on the blocks 731˜73N and 751˜75N of the MLC flash memories 730 and 750.
A controller 212 divides a plurality of blocks of an MLC flash memory 214 shown in
Referring to
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
This application claims the benefit of U.S. Provisional Application No. 61/097,627, filed on Sep. 17, 2008, and U.S. Provisional Application No. 61/180,168, filed on May 21, 2009, the entirety of which are incorporated by reference herein.
Number | Date | Country | |
---|---|---|---|
61097627 | Sep 2008 | US | |
61180168 | May 2009 | US |