This application claims the benefit of Korean Patent Application No. 10-2007-0003395, filed on Jan. 11, 2007, the subject matter of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device. More particularly, the invention relates to a flash memory device including a charge trap layer with trap sites storing charge, and a method of manufacturing same.
2. Description of the Related Art
Flash memory incorporating a charge trapping layer is one form of nonvolatile memory commonly used in many types of host devices and applications, such as mobile telecommunication systems, memory cards, etc.
A conventional charge-trap type flash memory device has a gate stack structure implemented by sequentially stacking a tunneling insulating layer, a charge trap layer, a blocking insulating layer and a gate electrode on a semiconductor substrate. The tunneling insulating layer contacts a source and a drain formed by of impurity regions in the semiconductor substrate. The charge trap layer has a material composition that traps and stores electrical charge passing through the tunneling insulating layer. The blocking insulating layer blocks charge leakage between the charge trap layer and the gate electrode.
In the conventional charge-trap type flash memory device, programming is carried out as charge (e.g., electrons) passes through the tunneling insulating layer under the influence of an applied voltage and is trapped in the trap sites within the charge trap layer. In the charge-trap type flash memory device, a threshold voltage (Vth) varies in accordance with the presence of charge trapped in the charge trap layer. Thus, as the charge trap density of the charge trap layer increases, the quality of programming and erasing operations performed by the charge-trap type flash memory device are improved. Unfortunately, increased charge retention capabilities for conventional charge-trap type flash memory device are often accompanied by degradation of performance in other regards.
On the other hand, as the charge trap density provided by the charge trap layer decreases, the speed of programming and erasing operations performed by the charge-trap type flash memory device will decrease. Yet, reduced charge retention characteristics for a charge-trap type flash memory device offer other performance advantages. In sum, it is very difficult to simultaneously satisfy demands for improved efficiency in programming and erasing operation while also balancing the charge retention characteristics of a charge trapping material used in the fabrication of a charge-trap type flash memory device.
These difficulties are exacerbated by ongoing attempts to increase the overall integration density of memory cells forming flash memory devices and thereby increase the data storage capacity per unit area of such devices. For example, in order to increase the data storage capacity of flash memory devices, attempts have been made to decrease the overall size of individual memory cells by improving the photolithography processes used during fabrication.
However, reductions in the size of constituent nonvolatile memory cells risk alteration of the properties defining the various layers and regions forming the memory cells, such as the charge trapping layer, tunneling insulating layer, etc. Any defect in the tunneling insulating layer, will allow trapped charge to escape. As the overall size of nonvolatile memory cells is reduced, the thickness of the constituent tunneling insulating layer must also be reduced. Such layer “thinning” increases the possibility of charge loss from the charge trap layer. This is particularly true over the lifetime of the flash memory device as repeated programming, reading and erasing operations tend to degrade the tunneling insulating layer. This well understood temporal phenomenon is referred to as stress induced leakage current (SILC).
Of further note, many conventional flash memory devices incorporate a silicon-oxide-nitride-oxide-silicon (SONOS) type structure. More particularly, the silicon nitride layer in the SONUS type structure serves as the charge trapping layer. This type of flash memory device secures a relatively large memory window and has proven to be an effect design. However, charge loss due to stress induced leakage current (SILC) is particularly pronounced for this type of tunneling insulating layer following repeated memory device operations.
Embodiments of the invention provide a flash memory device having improved charge storage capacity while preventing charge loss from a constituent charge trap layer caused by degradation of the tunneling insulating layer, regardless of its decreased thickness as required by contemporary and emerging charge-trap type flash memory devices characterized by reduced overall memory cell size.
Embodiments of the invention also provide a method of manufacturing a flash memory device that simply and easily forms a charge trap layer having a structure preventing charge loss from the charge trap layer under the foregoing conditions.
In one embodiment, the invention provides a flash memory device comprising; a tunneling insulating layer formed on a semiconductor substrate, a charge trap layer formed on the tunneling insulating layer, a blocking insulating layer formed on the charge trap layer, and a control gate electrode formed on the blocking insulating layer, wherein the charge trap layer comprises; at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other, such that each nano dot is at least partially encircled by the first trap layer, wherein the plurality of nano dots is formed from a second material having a second band gap energy lower than the first band gap energy.
In another embodiment, the invention provides a method of manufacturing a flash memory device comprising; forming a tunneling insulating layer on a semiconductor substrate, forming a charge trap layer on the tunneling insulating layer, forming a blocking insulating layer on the charge trap layer, and forming a control gate electrode on the blocking insulating layer, wherein forming the charge trap layer comprises; forming at least one hybrid trap layer on the tunneling insulating layer, the hybrid trap layer comprising a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other such that each nano dot is at least partially encircled by the first trap layer, wherein the plurality of nano dots is formed from a second material having a second band gap energy lower than the first band gap energy.
Embodiments of the invention will be described with reference to the attached drawings in which:
Embodiments of the invention will now be described in some additional detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are presented as teaching examples. Throughout the drawings, the relative thickness of various layers and regions may have been exaggerated for clarity of illustration. Throughout the written description and drawings, like reference numbers are used to indicate like or similar elements, layers, and regions.
FIG. (FIG.) 1 is a sectional view illustrating a portion of a flash memory device 100 according to an embodiment of the invention.
Referring to
Referring to
The nano dots 144 may be formed from a semiconductor material or a metal or metal alloy. For example, the nano dots 144 may be formed from a semiconductor material such as Si, Ge and SiGe or a metal material such as W, WN, TaN, Co and Pt.
The nano dots 144 may have a nitride surface 146. However, the nitride surface 146 is not essential and can be omitted.
The nano dots 144 may each have a particle size ranging from between about several nanometers (nm) to several hundreds of nanometers (nm).
In the structure of the first hybrid trap layer 132 of
The nano dots 144 are generally arranged in the same horizontal plane of first trap layer 142 in the first hybrid trap layer 132 and the second hybrid trap layer 134.
Referring to
Although the example of charge trap layer 130 illustrated in
The structure illustrated in
The structure illustrated in
Although not illustrated, the charge trap layer 130 illustrated in
If the lower trap layer is not formed between the first hybrid trap layer 132 and the tunneling insulating layer 120, the first hybrid trap layer 132 contacts the tunneling insulating layer 120 as illustrated in
As illustrated in
In the exemplary charge trap layers 130, 130A and 130B illustrated in
Certain functional aspects of the respective elements forming the charge trap layer 130 illustrated in
First, the nano dots 144 on the first hybrid trap layer 132 are formed from a material with a band gap energy lower than that of the first trap layer 142, thereby providing a deep trap level and improving the charge retention characteristics. Also, the potential well formed in the charge trap layer 130 is provided by the nano dots 144, so that the charge loss caused by the leakage of thermally activated charge to the tunneling insulating layer 120 after programming can be decreased.
The first trap layer 142 in the first hybrid trap layer 132 separates the nano dots 144 from each other. Accordingly, the nano dots 144 are formed within the first trap layer 142 at a relatively high density to increase charge storage capacity.
The density of the nano dots 144 within the charge trap layer 130 can be increased by the nano dots 144 in the second hybrid trap layer 134. Hence, the nano dots 144 in the second hybrid trap layer 134 improve the charge storage capacity of the charge trap layer 130.
The first trap layer 142 in the second hybrid trap layer 134 impedes the loss of the charge trapped in the nano dots 144 in the second hybrid trap layer 134 through the blocking insulating layer 160. Also, the blocking insulating layer 160, which in one embodiment is formed from a metal oxide layer such as Al2O3, prevents degradation in the charge trapping characteristics of the nano dots 144 due to the formation of oxidized surfaces of the nano dots 144 during forming the blocking insulating layer 160.
Referring to
Referring to
If the nano dot seeds 143 are formed from silicon (Si), the silicon source gas may be supplied on the tunneling insulating layer 120 for a predetermined time of about 1-2 minutes at a constant ambient temperature of about 500˜550° C., for example. The silicon source gas may be at least one gas selected from the group consisting of SiH4, SI2H6 and SiH2Cl2. While forming the nano dot seeds 143, a constant ambient pressure of about 0.1˜10 Torr may established, for example.
Referring to
In order to form the nano dots 144 composed of the crystalline silicon dots, the silicon seeds may be grown by supplying the silicon source gas onto the resultant structure formed with the silicon seeds thereon by maintaining a pressure of about 0.1˜10 Torr at a temperature of about 570˜600° C. for about 15˜20 minutes. Specifically, the nano dots 144 each may have a particle size WD of about 5 nm. Also, the nano dots 144 may be formed so as to maintain an approximate mean distance WG between respective nano dots 144 by about 5 nm.
Referring to
However, the nitridation of the surfaces of the nano dots 144 may be omitted in some embodiments of the invention.
Referring to
The first trap layer 142 may be formed from at least one material selected from the group consisting of Si3N4, HfSiO, HfAlO, SRN and SiON. The first trap layer 142 may cover the nano dots 144 to a thickness D1 that is similar to the distance WG between respective nano dots 144 formed on the tunneling insulating layer 120. In order to form the first trap layer 142, a low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) process may be performed, for example.
Referring to
The second hybrid trap layer 134 includes, similarly to the first hybrid trap layer 132, the nano dots 144 with the nitride surfaces 146 and the first trap layer 142 encircling the nano dots 144. In the second hybrid trap layer 134, the first trap layer 142 may cover the nano dots 144 to the thickness D1 that is similar to the distance WG between respective nano dots 144 formed on the first hybrid trap layer 132.
The first hybrid trap layer 132 and the second hybrid trap layer 134 form the charge trap layer 130. In the current embodiment, the charge trap layer 130 structure as illustrated in
Referring to
The blocking insulating layer 160 may be formed by a physical vapor deposition (PVD), an atomic layer deposition (ALD) or a chemical vapor deposition (CVD) process. The blocking insulating layer 160 may be formed from at least one material selected from the group consisting of Al2O3, SiO2, HfO2, ZrO2, LaO, LaAlO, LaHfO and HfAlO.
Referring to
Thereafter, the control gate electrode 170, the blocking insulating layer 160, the charge trap layer 130 and the tunneling insulating layer 120 are sequentially patterned to form a gate stack structure 110 as illustrated in
Referring to
Example 2 shows a case similar to Example 1 except that the Si3N4 layer forming the first hybrid trap layer was formed to a thickness of 50 Å.
Example 3 shows a case of forming the charge trap layer similar to Example 1.
Example 4 is a case of omitting the forming of the Si3N4 layer after forming the silicon nanocrystals Si NC when forming the second hybrid trap layer.
Example 5 shows a case of forming the charge trap layer similar to Example 2. The comparative example shows a charge trap layer formed of a Si3N4 layer to a thickness of 70 Å.
In respective Examples 1 through 5 and the comparative example, an Al2O3 layer to a thickness of 200 Å was formed on the charge trap layer and then annealed at a temperature of about 1050° C. for about 2 minutes to form a blocking insulating layer, and a TaN layer of about 200 Å was formed thereon to form a control gate electrode. In each case, the gate stack structure had a size of 1 μm both in length and width.
In order to obtain the result of
As described in
In
Example 7 was similar to Example 1, however, the forming of the silicon nano dots is omitted and the Si3N4 layer forming the first hybrid trap layer was formed to a thickness of 50 Å.
Example 8 was similar to Example 1, however, the Si3N4 layer forming the first hybrid trap layer is formed to a thickness of 50 Å.
In respective Examples 6, 7 and 8, the SiO2 layer was formed to a thickness of 40 Å as the tunneling insulating layer.
Example 9 was similar to Example 8 except that the SiO2 layer was formed having a thickness of 45 Å as the tunneling insulating layer.
From the evaluation results of
A flash memory device according to an embodiment of the invention will include a hybrid trap layer as a charge trap layer. The hybrid trap layer may include a film-shaped first trap layer formed from a first material having a band gap energy of a first level, and a plurality of nano dots which are separated from each other by a predetermined distance under a state of being partially encircled by the first trap layer and are formed from a second material having a band gap energy lower than the first level. Therefore, the nano dots having the band gap energy lower than the first trap layer are formed adjacent to the tunnelling insulating layer in flash memory devices according to embodiments of the invention, so that charge may be trapped at a low trap level in order to improve charge retention characteristics. Also, charge trap sites are increased within the charge trap layer to improve the reliability of the flash memory device. Furthermore, the charge trap density for the charge trap layer is improved in order to increase a charge storage capacity, and multilevel cells will be more easily fabricated.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2007-0003395 | Jan 2007 | KR | national |