Patent Grant
12165688
The present disclosure relates generally to memory and, in particular, in one or more embodiments, the present disclosure relates to instruction dynamic random access memory (DRAM) within flash memory devices.
Memories (e.g., memory devices) are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.
Flash memory may include ROM to store computer-readable executable instructions (e.g., firmware) for operating the flash memory. In addition, flash memory may include content-addressable memory (CAM) and static random access memory (SRAM) to store a limited set of firmware instructions that may be used to replace firmware instructions stored in the ROM.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.
Ranges might be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment might include from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
In flash memory devices including read only memory (ROM) to store computer-readable executable instructions (e.g., firmware), flexibility is limited and there may be a long turnaround time if changes are needed to the firmware to fix bugs or to improve performance. Content-addressable memory (CAM) and static random access memory (SRAM) may be used to store a limited set of firmware instructions that may be used to replace firmware instructions stored in the ROM, but the capacity to support updates to the firmware after the ROM is programmed in silicon is typically small. In addition, SRAM is about ten times the size as ROM, thus SRAM has a relatively high cost compared to ROM. Dynamic random access memory (DRAM) is comparable in area to ROM, is comparable/slightly slower in performance compared to ROM, and is easily updated.
Accordingly, disclosed herein are flash memory devices including embedded DRAM memory cells, which are post-silicon programmable and lower cost than SRAM memory cells, to replace the majority of the instruction ROM, as well as the instruction CAM and the instruction SRAM, to store firmware instructions. A small portion of the instruction ROM may be kept to support limited operations, such as memory device initialization, power on reset (POR) trim loading, special test modes, etc. Each time the memory device is initialized (e.g., powered up), the firmware instructions might be loaded into the DRAM and all firmware algorithms might be executed by loading the instructions from the DRAM. By using DRAM, updates to the firmware instructions to fix bugs or to improve performance might be simplified compared to updating the firmware instructions in ROM. Also disclosed herein is refresh conflict management to minimize and/or avoid any potential performance penalties caused by conflicts between periodic DRAM refreshes and firmware instruction execution.
In one example, the array of flash memory cells 104 might include a NAND memory array. In other examples, the array of flash memory cells 104 might include a NOR memory array. Controller 106 might include a microcontroller, a control unit (CU), a central processing unit (CPU), or other suitable logic circuitry for loading and executing instructions (e.g., firmware instructions) stored in the array of DRAM memory cells 102. As described in more detail below with reference to
As previously described, the controller 106 might be configured to execute first instructions stored in the array of DRAM memory cells 102 to access the array of flash memory cells 104 (e.g., for read and/or write operations and/or erase operations). Since the array of DRAM memory cells 102 is a volatile memory, the first instructions might be stored in a reserved portion of the non-volatile array of flash memory cells 104. Upon initialization (e.g., power up) of the memory device 100b, the controller 106 might be configured to execute second instructions (e.g., a limited subset of the firmware instructions) stored in the array of ROM memory cells 108 to copy the first instructions stored in the array of flash memory cells 104 and load/store the first instructions in the array of DRAM memory cells 102. The array of ROM memory cells 108 might also store instructions for POR trim loading and special test modes, etc. The array of ROM memory cells 108 might be much smaller than the array of DRAM memory cells 102.
The first instructions may be updated for bug fixes and/or performance improvements. In one example, the controller 106 might be configured to update the first instructions stored in the array of flash memory cells 104. In this case, upon initialization of the memory device 100b, the controller 106 might be configured to execute the second instructions stored in the array of ROM memory cells 108 to copy the updated first instructions stored in the array of flash memory cells 104 to the array of DRAM memory cells 102. The controller 106 might update the first instructions stored in the array of flash memory cells 104 by receiving the updated first instructions from a processor (e.g., 140 of
The array of SRAM memory cells 110 may store configuration data, such as dynamic trims and working variables. Since the array of SRAM memory cells 110 is a volatile memory, the configuration data might be stored in the reserved portion of the non-volatile array of flash memory cells 104. Upon initialization of the memory device 100b, the controller 106 might be configured to execute the second instructions stored in the array of ROM memory cells 108 to copy the configuration data stored in the array of flash memory cells 104 to the array of SRAM memory cells 110.
Memory device 100c includes an array of flash memory cells 104 that might be logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown in
A row decode circuitry 118 and a column decode circuitry 120 are provided to decode address signals. Address signals are received and decoded to access the array of flash memory cells 104. Memory device 100c also includes input/output (I/O) control circuitry 122 to manage input of commands, addresses and data to the memory device 100c as well as output of data and status information from the memory device 100c. An address register 124 is in communication with I/O control circuitry 122 and row decode circuitry 118 and column decode circuitry 120 to latch the address signals prior to decoding. A command register 134 is in communication with I/O control circuitry 122 and control logic 126 to latch incoming commands.
A controller 106 of the control logic 126 internal to the memory device 100c controls access to the array of flash memory cells 104 in response to the commands and may generate status information for the external processor 140, i.e., control logic 126 is configured to perform access operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of flash memory cells 104. The control logic 126 is in communication with row decode circuitry 118 and column decode circuitry 120 to control the row decode circuitry 118 and column decode circuitry 120 in response to the addresses. The control logic 126 might include DRAM 102 which might represent computer-usable memory for storing computer-readable instructions. For some embodiments, the DRAM 102 might store firmware.
Control logic 126 might also be in communication with a cache register 128. Cache register 128 latches data, either incoming or outgoing, as directed by control logic 126 to temporarily store data while the array of flash memory cells 104 is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data might be passed from the cache register 128 to the data register 130 for transfer to the array of flash memory cells 104; then new data might be latched in the cache register 128 from the I/O control circuitry 122. During a read operation, data might be passed from the cache register 128 to the I/O control circuitry 122 for output to the external processor 140; then new data might be passed from the data register 130 to the cache register 128. The cache register 128 and/or the data register 130 might form (e.g., might form a portion of) a page buffer of the memory device 100c. A page buffer might further include sensing devices (not shown in
Memory device 100c receives control signals at control logic 126 from processor 140 over a control link 142. The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) might be further received over control link 142 depending upon the nature of the memory device 100c. Memory device 100c receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor 140 over a multiplexed input/output (I/O) bus 144 and outputs data to processor 140 over I/O bus 144.
For example, the commands might be received over input/output (I/O) pins [7:0] of I/O bus 144 at I/O control circuitry 122 and might then be written into command register 134. The addresses might be received over input/output (I/O) pins [7:0] of I/O bus 144 at I/O control circuitry 122 and might then be written into address register 124. The data might be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 122 and then might be written into cache register 128. The data might be subsequently written into data register 130 for programming the array of flash memory cells 104. For another embodiment, cache register 128 might be omitted, and the data might be written directly into data register 130. Data might also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference might be made to I/O pins, they might include any conductive nodes providing for electrical connection to the memory device 100c by an external device (e.g., processor 140), such as conductive pads or conductive bumps as are commonly used.
It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device 100c of
Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) might be used in the various embodiments.
The instruction set (ISET) address space includes the array of ROM memory cells 108 and the array of DRAM memory cells 102 as indicated at 206. In one example, the array of DRAM memory cells 102 might provide at least 90% of the total ISET address space 206, while the array of ROM memory cells 108 might provide the remainder of the ISET address space 206. Compared to typical ISET address space that is comprised entirely of non-programmable ROM memory cells and/or higher cost SRAM memory cells, ISET address space comprised mostly of DRAM memory cells might have a lower cost and enable easier updating of the instruction code. In addition, all the instruction code may be updated since updates to the instruction code are not limited to the size of CAM and/or SRAM.
The controller 106 includes a program counter (PC) 210 and an instruction register (IR) 212. The program counter 210 might manage the memory address of the ISET address space of the array of ROM memory cells 108 and the array of DRAM memory cells 102. The program counter 210 might be used to address the instruction code to be executed next as indicated at 214. The addressed instruction code might then be output from the array of ROM memory cells 108 or the array of DRAM memory cells 102 as indicated at 216. The output from the array of ROM memory cells 108 or the array of DRAM memory cells 102 may then be loaded into the instruction register 212 for execution by the controller 106.
In one example, the array of DRAM memory cells 102 might have a block capacity of 4 kB by 21 bits to provide an 84 kB block capacity with a word size of 21 bits. In an example first option, the array of DRAM memory cells 102 might include 256 word lines (e.g., N=256) and 336 (16 by 21) bit lines (e.g., M=336). In this first option, a substantially even distribution of the array of DRAM memory cells 102 in the X/Y direction might be provided. In an example second option, the array of DRAM memory cells 102 might include 128 word lines (e.g., N=128) and 672 (32 by 21) bit lines (e.g., M=672). In this second option, the bit lines might be shorter in length compared to the first option. Shorter length bit lines might have smaller bit line capacitor loading, thus enabling a shorter refresh cycle time and providing a larger voltage swing resulting in an improved sensing margin. In this second option, however, the area for sensing circuits might be doubled and stronger word line drivers might be needed compared to the first option. In some embodiments, the array of DRAM memory cells 102 might be arranged in an open bit line array structure, where for each sensing circuit, the bit line pairs come from two different array segments. In other embodiments, the array of DRAM memory cells 102 might be arranged in a folded bit line array structure, where for each sensing circuit, the bit line pairs are within the same array segment.
where:
Trace 402 might represent the voltage level applied to a selected word line (e.g., one of word lines 3020 to 302N of
To read the value stored in the memory cell, at time T3, with the voltage level applied to the selected bit line at VPRE, the voltage level applied to the selected word line might be increased to VCCP, hence the memory cell transistor will be turned on. In response, the charge redistribution will take place between the bit line and the storage capacitor, and the delta voltage on the bit line may be sensed by a differential sense amplifier to determine the state of the memory cell (e.g., “0” or “1”), which is “1” in this example. At time T4, the voltage level of the selected bit line might be increased to VCC. The pull up due to a differential amplifier (described below with reference to
The trench capacitor 310 might be formed in p-doped substrate 500. The trench capacitor 310 might include an N+ well 502, a dielectric layer 504, and a polysilicon layer 506. The other terminal of the trench capacitor 310 might be electrically connected to the ground node 312 via an N+ polysilicon contact (not shown). In one example, the DRAM memory cell 305 might include two trench capacitors electrically connected in parallel to provide capacitor 310. In one embodiment, trench capacitor 310 has fixed dimensions to provide a 7.5 fF (+/−2.5 fF) target value for capacitor 310. In embodiments where two trench capacitors are electrically connected in parallel, capacitor 310 might have a value of 15 fF (+/−5 fF).
In one example, the area of unit block 700 might be less than about 1.29 μm2. In this case, each transistor 306 might have a width of about 135 nm and a length of about 145 nm. The minimum space design rule 710 between a polysilicon contact (for a vertical connection 516) to a polysilicon gate 511 might be about 167.5 nm. The minimum space design rule 712 between the N+ surround of a polysilicon contact (for a vertical connection 516) might be about 62.5 nm. The minimum space design rule 714 between the N+ space 512 (for a transistor) to the N+ space 502 (for trench capacitors) in the bit line direction might be about 100 nm. The minimum space design rule 716 between the N+ space 512 (for a first transistor) to the N+ space 512 (for an adjacent transistor) in the word line direction might be about 100 nm. In one example, these design rules might result in a DRAM memory having about 5% more area compared to a ROM memory of the same number of memory cells.
In another example, the area of unit block 700 might be less than about 1.17 μm2. In this case, each transistor 306 might have a width of about 135 nm and a length of about 145 nm. The minimum space design rule 710 between a polysilicon contact (for a vertical connection 516) to a polysilicon gate 511 might be reduced from about 167.5 nm to about 160 nm. The minimum space design rule 712 between the N+ surround of a polysilicon contact (for a vertical connection 516) might be reduced from about 62.5 nm to about 15 nm. The minimum space design rule 714 between the N+ space 512 (for a transistor) to the N+ space 502 (for trench capacitors) in the bit line direction might be reduced from about 100 nm to about 85 nm. The minimum space design rule 716 between the N+ space 512 (for a first transistor) to the N+ space 512 (for an adjacent transistor) in the word line direction might be reduced from about 100 nm to about 60 nm. In one example, these design rules might result in a DRAM memory having about 5% less area compared to a ROM memory of the same number of memory cells.
In yet another example, the area of unit block 700 might be less than about 1.04 μm2. In this case, each transistor 306 might have a width of about 135 nm and a length of about 50 nm. The minimum space design rule 710 between a polysilicon contact (for a vertical connection 516) to a polysilicon gate 511 might be reduced from about 167.5 nm to about 160 nm. The minimum space design rule 712 between the N+ surround of a polysilicon contact (for a vertical connection 516) might be reduced from about 62.5 nm to about 15 nm. The minimum space design rule 714 between the N+ space 512 (for a transistor) to the N+ space 502 (for trench capacitors) in the bit line direction might be reduced from about 100 nm to about 85 nm. The minimum space design rule 716 between the N+ space 512 (for a first transistor) to the N+ space 512 (for another transistor) in the word line direction might be reduced from about 100 nm to about 60 nm. In one example, these design rules might result in a DRAM memory having about 15% less area compared to a ROM memory of the same number of memory cells.
A memory cell 305, including a transistor 306 and a capacitor 310, is electrically connected between a bit line 304 and a word line 302. A memory cell 305_b is electrically connected between another bit line 304_b and another word line 302_b. Bit line 304 is electrically connected to one side of the source-drain path of transistors 810, 814, 826, 830, and 842, and to the gates of transistors 812 and 816. Bit line 304_b is electrically connected to one side of the source-drain path of transistors 812, 816, 828, and 844, the other side of the source-drain path of transistor 830, and to the gates of transistors 810 and 814. The other side of the source-drain paths of transistors 810 and 812 are electrically connected to a SAP signal node 804. The other side of the source-drain paths of transistors 814 and 816 are electrically connected to a SAN signal node 806. The other side of the source-drain path of transistors 826 and 828 are electrically connected to a VCC/2 (e.g., VPRE) voltage node 824. The gates of transistors 826, 824, and 830 are electrically connected to an equalizer enable (EQ_EN) signal node 822. The gates of transistors 842 and 844 are electrically connected to a column select (CSEL) signal node 840. The other side of the source-drain path of transistor 842 is electrically connected to one side of the source-drain path of transistor 852 through an output signal path 870. The other side of the source-drain path of transistor 844 is electrically connected to one side of the source-drain path of transistor 856 through an output_b signal path 870_b. The gates of transistors 852 and 856 are electrically connected to a write enable (WEN) signal node 850. The other side of the source-drain path of transistor 852 is electrically connected to an output of write driver 854. The other side of the source-drain path of transistor 856 is electrically connected to an output of write driver 858. A controller 106 (
During an access phase as indicated at 922, the selected word line 302 is overdriven to VCCP to turn on the memory cell transistor 306 to enable charge sharing between the storage capacitor 310 and the bit line 304. If the memory cell stores a digital value of “1” (as in the example of
During a sense phase as indicated at 924, the SAN signal node 806 is pulled towards GND and the SAP signal node 804 is pulled towards VCC. The small voltage difference between the bit line 304 and the bit line 304_b is then amplified by the cross-connected sense amplifier circuit 802. The voltage level of the bit line 304 and the voltage level of the bit line 304_b are driven to complementary maximum and minimum voltage levels (e.g., VCC and GND). The CEL signal node 840 is then biased to turn on the output transistors 842 and 844, so that the voltage level on the bit line 304 and the voltage level on bit line 304_b may be read out of the sensing/writing circuit 800 on output signal path 870 and output_b signal path 870_b, respectively. During a restore phase as indicated at 926, after the bit lines 304 and 304_b reach their maximum and minimum voltage levels (e.g., VCC and GND), the overdriven memory cell transistor 306 remains active, and the fully driven bit line voltage now restores (discharges if content is “0”) the charge in the storage capacitor 310.
To write data to memory cell 305, the bit lines 304 and 304_b are precharged as indicated at 920. The bit lines 304 and 304_b are then pulsed up or down by the sense amplifier circuit 802 according to the original contents of the memory cell. The CSEL signal node 840 and the WEN signal node 850 are then biased to enable the write driver 854 to overdrive the sense amplifier circuit 802 to write the desired value of “0” or “1” in the storage capacitor 310 by charging or discharging the storage capacitor 310.
Since the storage capacitor 310 of a memory cell slowly discharges due to leakage, the memory cell is periodically refreshed to maintain its state by reading the memory cell, which includes the precharge phase 920, access phase 922, sense phase 924, and restore phase 926 described above, except that the CSEL signal node 840 might remain biased to keep output transistors 842 and 844 turned off. A refresh operation might refresh all the memory cells in the same row (e.g., connected to the same word line) at once. During a refresh operation, normal read/write operations for the part of the DRAM memory that is being refreshed are blocked.
Each control circuit 10020 to 10025 includes a controller 10040 to 10045 and a DRAM memory 10060 to 10065, respectively. In some examples, DRAM memory 10060 might have a larger capacity than DRAM memory 10061, and DRAM memory 10061 might have a larger capacity than each of DRAM memories 10062 to 10065, which might have the same capacity. An output of the oscillator 1010 might be electrically connected to a first input of the refresh manager 1012 through a signal path 1011. A second input of refresh manager 1012 might receive a refresh period on a signal path 1016. An output of each controller 10040 to 10045 might be electrically connected to a third input of refresh manager 1012 through authorization/mask signal paths 1014. An input of each controller 10040 to 10045 might be electrically connected to a first output of refresh manager 1012 through a stall signal path 1018. A second output of refresh manager 1012 might be electrically connected to an input of refresh circuit 1030 through a go signal path 1020. A third input of refresh manager 1012 might be electrically connected to a first output of refresh circuit 1030 through a busy signal path 1022. A second output of refresh circuit 1030 might be electrically connected to an input of each DRAM memory 10060 to 10065 through signal paths 1032.
In one example, architecture 1000 might be part of control logic 126 (
The DRAM memories 10060 to 10065 are periodically refreshed to preserve the content of the DRAM memory cells. In one example, half of each DRAM memory 10060 to 10065 might be refreshed in less than about 1 μs and the refresh interval might be less than about 6 ms. While a controller 10040 to 10045 is currently executing instructions, the refresh of the respective DRAM memory 10060 to 10065 should be avoided to prevent execution errors. When a controller 10040 to 10045 is not currently executing instructions, which might be referred to as a stall, the respective DRAM memory 10060 to 10065 may be refreshed without generating execution errors. A DRAM memory 10060 to 10065 may be also refreshed without generating execution errors when the respective controller 10040 to 10045 is in a sleep phase. Therefore, each respective controller 10040 to 10045 might be configured to set a mask bit on an authorization/mask signal path 1014 in response to the respective controller 10040 to 10045 not being stalled. Each respective controller 10040 to 10045 might also be configured to set the mask bit on the authorization/mask signal path 1014 in response to the respective controller 10040 to 10045 executing critical instructions that should not be stalled. The refresh manager 1012 might be configured to periodically generate a refresh request and generate a refresh go signal on go signal path 1020 in response to the refresh request and an unset mask bit from each controller 10040 to 10045. The refresh circuit 1030 might be configured to refresh the DRAM memory 10060 to 10065 of each control circuit 10020 to 10025 in response to the go signal on signal path 1020. While refresh circuit 1030 is refreshing the DRAM memories 10060 to 10065, refresh circuit 1030 might generate a busy signal on busy signal path 1022.
There may be many sleep phases during the execution of the instructions by the controllers 10040 to 10045. Thus, each respective controller 10040 to 10045 might be configured to set a respective authorization bit on an authorization/mask signal path 1014 in response to the respective controller 10040 to 10045 being in a sleep phase. The refresh manager 1020 might be configured to generate the refresh go signal on refresh go signal path 1020 in response to the respective authorization bit being set for all the respective controllers 10040 to 10045. Therefore in this case, the refresh manager 1020 might not wait for a refresh request. In this way, execution of critical instructions by controllers 10040 to 10045 are less likely to be impacted since the refresh operation is favored in the waiting or non-critical phases of instruction execution.
The refresh manager 1012 might count the events generated by the oscillator 1010, and based on the refresh period input on signal path 1016, generate a refresh request to launch the refresh circuit 1030 when needed. In response to the refresh go signal on signal path 1020, the refresh circuit 1030 processes the refresh go signal and an internal counter sends addresses and other control logic signals to DRAM memories 10060 to 10065, which physically execute the refresh operation row by row until half of the capacity of each memory is refreshed within one refresh cycle. The refresh manager 1012 may force a stall of all controllers 10040 to 10045 via signal path 1018 while the refresh operation is active (as indicated by the busy signal on signal path 1022). There may be some critical firmware routines that should not be stalled. Therefore, in some embodiments, the refresh period may be set smaller than a maximum allowable refresh period to enable the refresh manager 1012 to postpone the refresh operation in the case of a mask signal being set. The refresh operation cannot be postponed forever, however, so the refresh manager 1012 may launch a watchdog timer. If the watchdog timer expires and the mask has not been unset, the controllers 10040 to 10045 might be forced to stall, the refresh operation might be implemented by refresh circuit 1030, and the currently executing operation might exit with an error as described in more detail below with reference to
If a mask bit is set, then at 1060 the refresh manager 1012 launches a watchdog timer. While the watchdog timer is running, at 1062 the refresh manager determines whether the mask bit remains set. If the mask bit has become unset, then at 1058 the refresh manager 1012 generates the refresh go signal, each DRAM memory 10060 to 10065 is refreshed by refresh circuit 1030, the refresh manager 1012 cancels the watchdog timer and returns to the idle state at 1052. In response to the mask bit remaining set, at 1064 the refresh manager determines whether the watchdog timer has expired. If the watchdog timer has not expired, the refresh manager returns to 1062 to again determine whether the set mask bit remains set. If the watchdog timer has expired, then at 1066 the refresh manager 1012 forces a stall of each controller 10040 to 10045, which results in an error being generated by the controller(s) forced to stall, the refresh manager 1012 generates the refresh go signal, and each DRAM memory 10060 to 10065 is refreshed by refresh circuit 1030. The refresh manager 1012 then returns to the idle state at 1052.
Thus, the refresh manager 1012 starts a watchdog timer in response to a refresh request and a set mask bit. The refresh manager 1012 generates the refresh go signal in response to the mask signal transitioning to unset prior to the watchdog timer expiring. In response to the watchdog timer expiring, the refresh manager 1012 forces a stall of each respective controller 10040 to 10045 and generates the refresh go signal.
Each control circuit 11020 to 11025 includes a controller 10040 to 10045, a DRAM memory 10060 to 10065, a refresh manager 11120 to 11125, and a refresh circuit 11300 to 11305, respectively. An output of the oscillator 1010 might be electrically connected to a first input of each refresh manager 11120 to 11125 through a signal path 1011. A second input (not shown) of each refresh manager 11120 to 11125 might receive a refresh period (e.g., as illustrated by refresh period signal path 1016 of
In one example, architecture 1100 might be part of control logic 126 (
The DRAM memories 10060 to 10065 are periodically refreshed to preserve the content of the DRAM memory cells. While a controller 10040 to 10045 is currently executing instructions, the refresh of the respective DRAM memory 10060 to 10065 should be avoided to prevent execution errors. When a controller 10040 to 10045 is not currently executing instructions, which might be referred to as a stall, the respective DRAM memory 10060 to 10065 may be refreshed without generating execution errors. Therefore, each respective controller 10040 to 10045 might be configured to set a mask bit on the respective authorization/mask signal path 11140 to 11145 in response to the respective controller 10040 to 10045 not being stalled. Each refresh manager 11020 to 11025 might be configured to periodically generate a refresh request and generate a refresh go signal on the respective go signal path 11200 to 11205 in response to the respective refresh request and a respective unset mask bit from each respective controller 10040 to 10045. Each refresh circuit 11300 to 11305 might be configured to refresh the respective DRAM memory 10060 to 10065 of each respective control circuit 10020 to 10025 in response to the go signal on the respective signal path 11200 to 11205. While each refresh circuit 11300 to 11305 is refreshing the respective DRAM memory 10060 to 10065, the respective refresh circuit 11300 to 11305 might generate a busy signal on the respective busy signal path 11220 to 11225.
Each refresh manager 11120 to 11125 might count the events generated by the oscillator 1010 and based on the refresh period, generate a refresh request to launch the respective refresh circuit 11300 to 11305 when needed. In response to the refresh go signal on the respective signal path 11200 to 11205, each refresh circuit 11300 to 11305 processes the respective refresh go signal and an internal counter sends addresses and other control logic signals to the respective DRAM memory 10060 to 10065, which physically executes the refresh operation row by row until half of the capacity of the respective memory is refreshed within one refresh cycle. Each refresh manager 11020 to 11025 may force a stall of the respective controller 10040 to 10045 via the respective signal path 11180 to 11185 while the refresh operation is active (as indicated by the busy signal on the respective signal path 11220 to 11225). Each refresh manager 11020 to 11025 might refresh the respective DRAM memory 10060 to 10065 during stalls of the respective controller 10040 to 10045. During the refresh-during-stalls, each refresh manager 11020 to 11025 may launch a respective watchdog timer. If stalls of the respective controller 10040 to 10045 are not enough time to complete the refresh operation and the respective watchdog timer expires, the respective controller 10040 to 10045 might be forced to stall, the refresh operation might be completed by the respective refresh circuit 11300 to 11305, and the currently executing operation might exit with an error as described in more detail below with reference to
Thus, each respective refresh manager 11120 to 11125 might be configured to periodically receive a refresh request and start a watchdog timer in response to the refresh request. The respective refresh circuit 11300 to 11305 might be configured to refresh the respective array of DRAM memory cells 10060 to 10065 during stalls of the respective controller 10040 to 10045 and with the watchdog timer not expired. Each respective refresh circuit 11300 to 11305 for each control circuit 11020 to 11025 might be configured to force a stall of the respective controller 10040 to 10045 and refresh the respective array of DRAM memory cells 10060 to 10065 in response to the watchdog timer expiring.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20050204091 | Kilbuck | Sep 2005 | A1 |
| 20170010817 | Lim | Jan 2017 | A1 |
| 20180329640 | Roohparvar | Nov 2018 | A1 |
| 20190278516 | Rowley | Sep 2019 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20230377626 A1 | Nov 2023 | US |
