Patent Grant
9048316
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
One of the important drivers for increased performance in computers is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. Tolerances play an important role in being able to shrink dimensions on a chip.
A split-gate flash memory cell has elements such as a floating gate and source and drain regions. However, controlling and shrinking the size of those elements in a split-gate flash memory cell are still challenging.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description that follows include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Mechanisms for forming a semiconductor device structure are provided in accordance with some embodiments of the disclosure.
After STIs 106 are formed, word line cells 102 are formed over substrate 101 across STIs 106 in accordance with some embodiments. In addition, memory gates 104 are formed adjacent to word line cells 102 over substrate 101. Details of the flash memory structure in
Word line cell 102 may be formed by depositing first polysilicon layer 110 over substrate 101, depositing insulating layer 112 over polysilicon layer 110, and patterning first poly silicon layer 110 and insulating layer 112. In some embodiments, first polysilicon layer 110 and insulating layer 112 are formed by CVD. In some embodiments, first polysilicon layer 110 and insulating layer 112 are formed by Furnace. In some embodiments, first polysilicon layer 110 and insulating layer 112 are patterned by forming a photoresist layer over insulating layer 112, patterning the photoresist layer, and etching insulating layer 112 and polysilicon layer 110. In some embodiments, insulating layer 112 and first polysilicon layer 110 are patterned by an anisotropic dry etching process.
In some embodiments, control gate has a thickness T1, and insulating layer 112 has a thickness T2. In addition, word line cell 102 has a height H1, which is a sum of T1 and T2.
After word line cell 102 is formed, a dielectric layer 114 is conformally formed over substrate 101 to cover word line cell 102, as shown in
After dielectric layer 114 is formed, a second polysilicon layer 116 is conformally formed over dielectric layer 114 as shown in
It should be noted that, at the top surface of STI 106, divots 108 are formed due to isotropic wet etch process during STIs formation. When dielectric layer 114 and second poly silicon layer 116 are formed over substrate 101, dielectric material of dielectric layer 114 and polysilicon of polysilicon layer 116 also fill in divots 108.
Next, an etching process is performed to remove some portions of second polysilicon layer 116 and form polysilicon spacers, as shown in
Next, resist layer 118 is formed to cover first polysilicon spacer 117aa, as shown in
After resist layer 118 is formed, second polysilicon spacer 117ba is removed, as shown in
Afterwards, an etching process is performed to remove exposed portions of dielectric layer 114, as shown in
After memory gate 104a is formed, source extension regions and drain extension regions may be formed in substrate 101 (not shown), and spacers are formed along sidewalls of word line cell 102 and memory gate 104 afterwards. More specifically, an insulating film 120 is conformally formed over substrate 101 to cover word line cell 102 and memory gate 104a, as shown in
Next, insulating film 120 is etched to form spacers 122aa, 122ba, and 122ca, as shown in
Next, a silicide layer 124 is formed over memory gate 104a, as shown in
Afterwards, a contact etch stop layer 126 is conformally formed over substrate 101 to cover word line cell 102 and memory gate 104, as shown in
After interlayer dielectric layer 128 is formed, an opening 130 is formed through interlayer dielectric layer 128 over memory gate 104a, as shown in
Next, contact 132 is formed in opening 130, as shown in
As mentioned previously, memory gate 104a is adjacent to word line cell 102 and is formed by etching polysilicon layer 116 without using any mask structure. However, in order to remove all the polysilicon (e.g. portions of polysilicon layer 116) within divots 108, polysilicon layer 116 is over-etched. Therefore, memory gate 104a has a relatively low average height. In addition, spacer 122aa formed at a sidewall of memory gate 104a has an average height even lower than the average height of memory gate 104a due to the slanted top surface. As a result, when contact 132 has extending portion 133 extending into spacer 122aa, a distance between substrate 101 (or STI 106 as shown in
More specifically, word line cell 102 is formed across STI 106 over substrate 101, and word line cell 102 includes a control gate and an insulating layer 112, as shown in
As shown in
After capping layer 302 is formed, a chemical mechanical polishing (CMP) process 303 is performed, as shown in
After second polysilicon layer 116 is grinded, oxide layer 304 is formed on exposed surface, which is not covered by capping layer 302, of second polysilicon layer 116, as shown in
Next, the remaining portions of capping layer 302 are removed, as shown in
After capping layer 302 is removed, portions of second polysilicon layer 116 which are not covered by oxide layer 304 are removed, as shown in
Next, resist layer 118 is formed to cover first polysilicon spacer 117ab, as shown in
After resist layer 118 is formed, second polysilicon spacer 117bb, which is not covered by resist layer 118, is removed, as shown in
Next, an etching process is performed to remove the exposed portions of dielectric layer 114 and oxide layer 304, as shown in
As described previously, memory gates 104b are formed by performing CMP process 303 to second polysilicon layer 116, forming oxide layer 304, and performing the etching process afterwards. Since second polysilicon layer 116 is grinded by CMP process 303, an angle θ between the top surface and a sidewall of memory gates 104b is in a range from about 75° to about 90° in accordance with some embodiments. In some embodiments, memory gate 104b is in a shape of a rectangle. In some embodiments, the top surface of memory gate 104b is parallel to the top surface of substrate 101 (or STI 106 as shown in
In addition, during the formation of polysilicon spacers 117ab and 117bb, oxide layer 304 is used as the mask. Therefore, the size of second polysilicon spacer 117bb (which forms memory gates 104b afterwards) is precisely controlled (compared to first polysilicon spacer 117aa, which is formed by etching without using any mask structure). In addition, although the etching process needs to be performed for a long time to ensure that all polysilicon within divots 108 is removed, first polysilicon spacer 117ab (memory gates 104b) can still remain its height (or average height) H2. As shown in
Afterwards, spacers are formed along the sidewalls of word line cell 102 and memory gate 104b. Similar to the processes described previously, insulating film 120 is conformally formed over substrate 101 to cover word line cell 102 and memory gate 104b, as shown in
Afterwards, insulating film 120 is etched to form spacers 122ab and 122cb, as shown in
As described previously, before and after spacers 122ab and 122cb are formed, source extension regions, drain extension regions, and source and drain regions may be formed in substrate 101 (not shown). In addition, since spacers 122ab and 122cb have large sizes, the distances between source and drain regions and gate structures (e.g. control gate 110 and memory gate 104b) also increase.
Next, silicide layer 124 is formed over memory gate 104b, as shown in
After interlayer dielectric layer 128 is formed, opening 130 is formed through interlayer dielectric layer 128, as shown in
Next, contact 132 is formed in opening 130, as shown in
As described above, since memory gate 104b has a relatively large height H2 (e.g. compared to the average height of memory gate 104a), spacer 122ab, formed at the sidewall of memory gate 104b, also has a relatively large average height H3 (e.g. compared to the average height of spacers 122aa). Therefore, when contact 132 has extending portion 133 extending into spacer 122ab, the distance between extending portion 133 of contact 132 and substrate 101 (or STI 106 as shown in
As shown in
As mentioned above, the formation of memory gate 104b includes performing CMP process 303, forming oxide layer 304, and performing the etching process afterwards. These processes enable the formation of memory gate 104b to be of a controllable size. For example, memory gate 104b has relatively large height H2 (e.g. compared to the average height of memory gate 104a). In addition, since height H2 of memory gate 104b is relatively large, average height H3 of spacer 122ab is also relatively large (e.g. compared to the average height of spacer 122aa). Therefore, contact 132 (especially extending portions 133 of contact 132) is far enough apart from substrate 101 that the risk of leakage is decreased. In addition, elements such as oxide layer 304 and spacers 122ab and 122cb are self-aligned to their target positions during the formation process, and therefore the size of the structure may be scaled down as required. In addition, additional operations for alignments are not required, and the fabrication processes and cost of forming the flash memory structure are decreased.
Embodiments of mechanisms for a flash memory structure are provided. The flash memory structure includes a word line cell, a memory gate adjacent to the word line cell, and a spacer aligned with the memory gate formed over a substrate. A size of the memory gate is precisely controlled. In addition, heights of the memory gate and the spacer are relatively large. The spacer with the relatively large average height prevents contact from being too close to, or even directly contacting, substrate 101. Therefore, leakage is avoided.
In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.
In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a top surface and a word line cell formed over the substrate. The word line cell includes a control gate and an insulating layer formed over the control gate. The semiconductor device structure further includes a memory gate adjacent to the word line cell, and the memory gate has a top surface. The semiconductor device structure further includes a spacer on a sidewall of the memory gate. In addition, the top surface of the memory gate is parallel to the top surface of the substrate.
In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes providing a substrate and forming a word line cell over the substrate. The word line cell has a top surface. The method further includes forming a polysilicon layer over the word line cell and forming a capping layer over the polysilicon layer. The method further includes performing a chemical mechanical polishing (CMP) process to the capping layer and the polysilicon layer to expose a top surface of the polysilicon layer. The top surface of the polysilicon layer is substantially level with the top surface of the word line cell. The method also includes forming an oxide layer on the top surface of the polysilicon layer and removing the capping layer. The method further includes removing portions of the polysilicon layer not covered by the oxide layer to form a first polysilicon spacer and a second polysilicon spacer.
Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20090309153 | Yanagi et al. | Dec 2009 | A1 |
| 20100054043 | Liu et al. | Mar 2010 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20150060974 A1 | Mar 2015 | US |
