FLASH MEMORY SYSTEM CONTROL SCHEME

Abstract

A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

FIG. 1 is a block diagram of a prior art Flash memory system;

FIG. 2 is a schematic of a prior art NAND Flash memory core;

FIG. 3 is an illustration of a conventional file structure for a Flash memory system;

FIG. 4 is a block diagram of a Flash memory system according to an embodiment of the present invention;

FIG. 5 is a timing diagram of program commands issued by the Flash controller of FIG. 4, according to an embodiment of the present invention;

FIG. 6 is a timing diagram showing program commands received by each memory device of the Flash memory system in FIG. 4;

FIG. 7 is a flow chart illustrating a high speed interleaved programming method, according to an embodiment of the present invention;

FIG. 8 is a graphical illustration of a file structure in the Flash memory system in FIG. 4 resulting from the high speed interleaved programming method of FIG. 7;

FIG. 9 is a flow chart illustrating a high speed wear leveling programming method, according to an embodiment of the present invention; and

FIG. 10 is a timing diagram showing interleaved program and read operations.

Claims

1. A method for controlling first and second Flash memory devices connected to a channel, comprising: a) executing a first operation in the first Flash memory device in response to a first command; and,b) initiating a second operation in the second Flash memory device in response to a second command, while the first Flash memory device is executing the first operation.

2. The method of claim 1, wherein the first Flash memory device and the second Flash memory device are serially connected to each other, and the second command is passed to the second Flash memory device through the first Flash memory device before the step of initiating.

3. The method of claim 1, wherein executing the first operation includes programming at least one page of a data file in the first Flash memory device.

4. The method of claim 3, wherein initiating the second operation includes initiating programming of at least one other page of the data file in the second Flash memory device.

5. The method of claim 4, further including initiating a third operation in the first Flash memory device in response to a third command.

6. The method of claim 3, wherein initiating the second operation includes initiating a read operation of data in the second Flash memory device.

7. The method of claim 3, wherein initiating the second operation includes initiating an erase operation in the second Flash memory device.

8. The method of claim 1, wherein executing the first operation includes one of a read operation and an erase operation in the first Flash memory device.

9. A method for high speed wear leveling programming in a Flash memory system having a plurality Flash memory devices, comprising: i. receiving a data file having k pages, k being an integer greater than 0;ii. selecting a programming profile corresponding to the size of k and configuration parameters of the Flash memory system;iii. programming at least one of the k pages of the data file in each of at least two of the plurality of Flash memory devices in accordance with the selected programming profile.

10. The method of claim 9, wherein the configuration parameters include j Flash memory devices, and each of the j Flash memory devices have i pages per block, where j and i are integer values greater than 0.

11. The method of claim 10, wherein the step of selecting includes calculating a ceiling function of z, where z=k/i.

12. The method of claim 11, wherein the programming profile includes a single file structure for storing k pages of the data file in z of j Flash memory devices when z is less than or equal to j.

13. The method of claim 12, wherein the step of programming includes sequentially providing program commands to each of the z Flash memory devices for programming the k pages, each program command for programming the at least one of the k pages.

14. The method of claim 11, wherein the programming profile includes a multiple file structure when z is greater than j.

15. The method of claim 14, wherein the multiple file structure includes storing m units of j*i pages of the data file in j Flash memory devices, and storing k−(m*j*i)) pages of the data file in z of j Flash memory devices when z is less than or equal to j, where m is an integer value greater than 0.

16. The method of claim 15, wherein the step of programming includes sequentially providing program commands to each of the j Flash memory devices for programming the j*i pages of the data file, each program command for programming the at least one of the k pages.

17. The method of claim 16, wherein the step of programming includes sequentially providing program commands to each of the z Flash memory devices for programming the k−(m*j*i)) pages, each program command for programming the at least one of the k pages.

18. A data file structure for a memory system having at least two memory devices connected to the same channel, comprising: portions of the data file stored in two of the at least two memory devices.

19. The data file structure of claim 18, wherein the portions are substantially equal in size to each other.

20. The data file structure of claim 18, wherein the portions are stored in each of the at least two memory devices of the memory system.

21. A method for high speed wear leveling programming in a Flash memory system having j Flash memory devices, each of the j Flash memory devices having i pages per block, where j and i are integer values greater than 0, the method comprising: a) receiving a data file having k pages, k being an integer greater than 0;b) providing commands for programming k pages within z of j memory devices if a ceiling function of z=k/i is less than or equal to j;c) providing commands for programming j*i pages within j memory devices if the ceiling function of z=k/i is greater than j;d) updating k by setting k=k−(j*i); and,e) repeating step b.

22. A Flash memory system comprising: a controller having a channel for providing a first command and a second command;a first Flash memory device coupled to the channel for executing a first operation in response to the first command; and,a second Flash memory device coupled to the channel for initiating a second operation in response to the second command while the first Flash memory device is executing the first operation.

23. The method of claim 22, wherein the first Flash memory device and the second Flash memory device are serially connected to each other, and the second command is passed to the second Flash memory device through the first Flash memory device.

24. The method of claim 22, wherein the first operation includes a programming operation, and the first Flash memory device programs at least one page of a data file.

25. The method of claim 24, wherein the second operation includes another programming operation, and the second Flash memory device programs at least one other page of the data file.