BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 (Prior Art) is a schematic illustration showing a conventional liquid crystal display.
FIG. 2A is a block diagram showing a flat display according to a first embodiment of the invention.
FIG. 2B is a timing chart showing timings of an operating voltage VDD, a reset signal Reset, an output start signal STV_OUT and an output clock signal CPV_OUT according to the first embodiment of the invention.
FIG. 3 is a block diagram showing a flat display according to a second embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
The invention provides a flat display and a timing controller thereof for eliminating a residual image of the flat display by way of timing control when the flat display is shut down. Thus, the thin film transistors in all scan rows of the pixel array can be quickly turned on to eliminate the residual image quickly without adding the reset circuit and the scan-row-fully-open pin XAO to the gate driver when the display is shut down. The flat display according to any embodiment of the invention will be described by taking, without limitation to, the liquid crystal display (LCD) as an example. It is to be specified that any flat display having the features of the invention is still deemed as falling within the spirit and the scope of the invention.
First Embodiment
FIG. 2A is a block diagram showing a flat display 20 according to a first embodiment of the invention. Referring to FIG. 2A, the flat display 20, such as a LCD, includes a timing controller 21, a gate driver 22, a source driver (not shown in FIG. 2A) and a pixel array 23. The timing controller 21 includes a voltage detecting circuit 212, a clock generator 214, a first multiplexer 216 and a second multiplexer 218. The voltage detecting circuit 212 detects a variation of an operating voltage VDD and thus outputs a reset signal Reset. The clock generator 214 outputs a start signal STV and a first clock signal CPV1, which are required to make the gate driver 22 operate normally. The first multiplexer 216 is controlled by the reset signal Reset to select the start signal STV or a constant voltage as an output signal STV_OUT, wherein the constant voltage and the start signal STV have opposite levels. For example, when the start signal STV for the normal operation is the low level voltage, the constant voltage may be the operating voltage VDD or any high level voltage generated by the timing controller 21 itself.
The second multiplexer 218 is controlled by the reset signal Reset to select the first clock signal CPV1 or a second clock signal CPV2 as an output signal CPV_OUT, wherein the second clock signal CPV2 has a frequency obviously higher than a frequency of the first clock signal CPV1. The second clock signal CPV2 may be generated by an oscillator in the timing controller 21. The second clock signal CPV2 may also be an oscillation clock signal provided by other circuits in the flat display 20. The gate driver 22 is coupled to the first multiplexer 216 and the second multiplexer 218, and outputs a gate signal to turn on each scan row of the pixel array 23 according to the output signals STV_OUT and CPV_OUT.
FIG. 2B is a timing chart showing timings of the operating voltage VDD, the reset signal Reset, the output start signal STV_OUT and the output clock signal CPV_OUT according to the first embodiment of the invention. When the flat display 20 operates normally, the voltage detecting circuit 212 outputs the reset signal Reset having the high level (i.e., the voltage level is H) according to the existence of the operating voltage VDD (=V0) to control the first multiplexer 216 to output the start signal STV to the gate driver 22. That is, the output signal STV_OUT outputted from the timing controller 21 is the start signal STV. Meanwhile, the voltage detecting circuit 212 outputs the reset signal Reset having the high level (i.e., the voltage level is H) to control the second multiplexer 218 to output the first clock signal CPV1 to the gate driver 22. That is, the output signal CPV_OUT outputted from the timing controller 21 is the first clock signal CPV1. At this time, the gate driver 22 outputs the gate signal to the pixel array 23 to display the image normally according to the normal start signal STV and the clock signal CPV1.
When the flat display 20 is shut down, for example, the voltage detecting circuit 212 outputs the reset signal Reset having the low level (i.e., the voltage level is L) to control the first multiplexer 216 to output the operating voltage VDD or the constant high level voltage to the gate driver 22 when the operating voltage VDD is lowered to 70% (i.e., 0.7V0). That is, the output signal STV_OUT outputted from the timing controller 21 is converted into the operating voltage VDD or the constant high level voltage. Meanwhile, the voltage detecting circuit 212 outputs the reset signal Reset having the low level (i.e., the voltage level is L) to control the second multiplexer 218 to output the second clock signal CPV2 to the gate driver 22. That is, the output signal CPV_OUT outputted from the timing controller 21 is converted into the second clock signal CPV2.
At this time, the gate driver 22 quickly outputs the gate signal having a high level voltage Vgh according to the received operating voltage VDD or the constant high level voltage and the clock signal CPV2 with the obvious higher frequency. Thus, the thin film transistors in all the scan rows of the pixel array 23 are quickly turned on so that the effect of eliminating the shutdown residual image can be achieved.
Second Embodiment
FIG. 3 is a block diagram showing a flat display 30 according to a second embodiment of the invention. Referring to FIG. 3, the flat display 30, such as a LCD, includes a gate driver 32, a source driver (not shown in FIG. 3), a pixel array 33, a voltage detecting circuit 312, a timing controller 314, a first multiplexer 316 and a second multiplexer 318. The voltage detecting circuit 312, the timing controller 314, the first multiplexer 316 and the second multiplexer 318 may be disposed on a printed circuit board 31. The voltage detecting circuit 312 detects a variation of an operating voltage VDD and thus outputs a reset signal Reset. The timing controller 314 outputs a start signal STV and a first clock signal CPV1 for making the gate driver 32 operate normally. The first multiplexer 316 is controlled by the reset signal Reset to select the start signal STV or a constant voltage as an output signal STV_OUT, wherein the constant voltage and the start signal STV have opposite levels. For example, when the start signal STV is the low level voltage, the constant voltage is the operating voltage VDD or the high level voltage generated by other circuits on the printed circuit board 31.
The second multiplexer 318 is controlled by the reset signal Reset to select the first clock signal CPV1 or a second clock signal CPV2 as an output signal CPV_OUT, wherein the second clock signal CPV2 has a frequency obviously higher than a frequency of the first clock signal CPV1. The second clock signal CPV2 is generated by other circuits on the printed circuit board 31 or an oscillator in the timing controller 314. The gate driver 32 is coupled to the first multiplexer 316 and the second multiplexer 318, and outputs a gate signal to turn on each scan row of the pixel array 33 according to the output signals STV_OUT and CPV_OUT.
Similar to the first embodiment, as shown in FIG. 2B, when the flat display 30 operates normally, the voltage detecting circuit 312 outputs the reset signal Reset having the high level to control the first multiplexer 316 to output the start signal STV to the gate driver 32 according to the existence of the operating voltage VDD (=V0), and to control the second multiplexer 318 to output the first clock signal CPV1 to the gate driver 32 so that the gate driver 32 outputs the normal gate signal to the pixel array 33 to display the normal image. When the flat display 30 is shut down and when the operating voltage VDD is lowered to 70% (i.e., 0.7V0), the voltage detecting circuit 312 outputs the reset signal Reset having the low level to control the first multiplexer 316 to output the operating voltage VDD or the constant high level voltage to the gate driver 32, and to control the second multiplexer 318 to output the second clock signal CPV2 to the gate driver 32. Thus, the gate driver 32 outputs the gate signal having a high level voltage Vgh according to the operating voltage VDD or the constant high level voltage and the clock signal CPV2 having the obvious higher frequency. Consequently, the thin film transistors in all the scan rows of the pixel array 33 are quickly turned on so that the effect of eliminating the shutdown residual image can be achieved.
The flat display according to each embodiment of the invention eliminates the shutdown residual image according to the timing control of the circuit in the timing controller or other circuits in the flat display. Thus, the thin film transistors in all the scan rows of the pixel array can be quickly turned on and the residual image can be quickly eliminated during the shutdown without adding the reset circuit and adding the scan-row-fully-open pin XAO to the gate driver.
While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Patent Application
20080062072
