Patent Application
20240337764
The present disclosure relates to the field of flat panel detection technology, and particularly relates to a flat panel detector and a detecting apparatus.
With the continuous development of flat panel detection technology in recent years, manufacturers and researchers have brought the flat panel X-ray detector (FPXD) from laboratory to clinical use, and due to the advantages of high sensitivity, wide dynamic range, low distortion of digital images, and the like, the flat panel X-ray detector is widely applied to the fields of medical radiation imaging, industrial flaw detection, security inspection, and the like. The flat panel X-ray detector includes an array substrate, where the array substrate includes an X-ray conversion layer and detecting units, the X-ray conversion layer may be made of a scintillator material, and each detecting unit includes a thin film transistor and a photodiode. When the array substrate is irradiated by X rays, the X rays are converted into visible light by the X-ray conversion layer, then the visible light is converted into electric signals by the photodiodes in the detecting units, and the electric signals are processed to obtain desired image information.
The inventor finds that the conventional flat panel X-ray detector has a problem of high noise, and therefore, providing a flat panel X-ray detector with low noise is an urgent problem to be solved.
The present disclosure is directed to solve at least one of the problems of the prior art and to provide a flat panel detector.
The present disclosure provides a flat panel detector, which includes a base substrate, and a plurality of scanning lines, a plurality of data lines, a plurality of bias signal lines and a plurality of detecting units arranged in an array, which are disposed on the base substrate; each of the plurality of detecting units includes a switch sub-circuit and a photosensitive device; control terminals of switch sub-circuits in detecting units located in a same row are connected with a same scanning line; first terminals of switch sub-circuits in detecting units located in a same column are connected with a same data line; in each detecting unit, a second terminal of the switch sub-circuit is connected with a first terminal of the photosensitive device; second terminals of photosensitive devices of the detecting units located in the same column are connected with a same bias signal line, where the plurality of bias signal lines are divided into a plurality of signal line groups, the bias signal lines in different signal line groups are insulated from each other and are connected with different driving chips.
In some implementations, each of the bias signal lines includes a first end and a second end that are oppositely disposed in a column direction, first ends of the bias signal lines in a same signal line group are connected with each other by a first short-circuiting bar, and second ends of the bias signal lines are connected with each other by a second short-circuiting bar; each first short-circuiting bar is connected with one of the driving chips, and/or each second short-circuiting bar is connected with one of the driving chips.
In some implementations, each of the bias signal lines includes a first end and a second end that are oppositely disposed in a column direction, first ends of the bias signal lines of one of two adjacent signal line groups are connected with each other by a first short-circuiting bar, and second ends of the bias signal lines of the other of the two adjacent signal line groups are connected with each other by a second short-circuiting bar, and each first short-circuiting bar is connected with one of the driving chips, and each second short-circuiting bar is connected with one of the driving chips.
In some implementations, each of the plurality of bias signal lines includes a first signal sub-line and a second signal sub-line arranged side by side in a column direction, and the photosensitive devices connected to the first signal sub-line and the second signal sub-line are different;
for any signal line group, ends of first signal sub-lines away from second signal sub-lines are connected with each other by a first short-circuiting bar, and ends of the second signal sub-lines away from the first signal sub-lines are connected with each other by a second short-circuiting bar; each first short-circuiting bar is connected with one of the driving chips, and each second short-circuiting bar is connected with one of the driving chips.
In some implementations, the switch sub-circuit includes a thin film transistor, a first electrode of the thin film transistor is connected with a data line, a second electrode of the thin film transistor is connected with a photosensitive device, and a control electrode of the thin film transistor is connected with a scanning line; the thin film transistor is configured to write an electric signal generated by the photosensitive device into the data line under control of a control signal of the scanning line.
In some implementations, the thin film transistor includes an amorphous silicon thin film transistor or a metal oxide thin film transistor.
In some implementations, a photoelectric conversion layer is provided on a side of the detecting unit away from the base substrate, and the photoelectric conversion layer is configured to convert an external electric signal into an optical signal.
In some implementations, the photosensitive device includes a photodiode; a first electrode of the photodiode is connected with the thin film transistor, and a second electrode of the photodiode is connected with the bias signal line; the photodiode is configured to convert the optical signal received into an electric signal under an action of a bias voltage of the bias signal line, and input the electric signal to the second electrode of the thin film transistor.
In some implementations, the photodiode includes a PIN type photodiode.
On the other hand, the present disclosure further provides a detecting apparatus, which includes the above flat panel detector.
In order to enable those skilled in the art better understand the technical solutions of the present disclosure, the following detailed description is given with reference to the accompanying drawings and specific implementations.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second”, and the like in this disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the term “a”, “an”, “the”, or the like does not denote a limitation of quantity, but rather denotes the presence of at least one. The term “comprising/including”, “comprises/includes”, or the like means that the element or item preceding the term includes the element or item listed after the term and its equivalent, but does not exclude other elements or items. The term “connected/coupled”, “connecting/coupling”, or the like is not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and since a source and a drain of each transistor used are symmetrical, there is no difference in functions of the source and the drain. In addition, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are adopted for explanation, when the N-type transistors are used, a first electrode is a drain electrode of the N-type transistor, a second electrode is a source electrode of the N-type transistor, and when the high level is input to a gate electrode, the source and drain electrodes are conducted, which is opposite for the P-type transistor. It is contemplated that implementation with P-type transistors will be readily apparent to one skilled in the art without creative effort, and thus, are within the scope of embodiments of the present disclosure.
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The gate 14 of the thin film transistor 11 is disposed on the base substrate 1, the gate insulating layer 15 is disposed on a side of the base substrate 1 and the gate 14 of the thin film transistor 11 away from the base substrate 1, the active layer 16 is disposed on a side of the gate insulating layer 15 away from the base substrate 1, the source and the drain are formed on a first metal layer 17, the first metal layer 17 being disposed on a side of the gate insulating layer 15 and the active layer 16 away from the base substrate 1. A first insulating layer 22 is disposed on a side of the first metal layer 17 away from the base substrate 1, and a first conductive layer 19 is disposed on a side of the first insulating layer 22 away from the base substrate 1, and penetrates through the first insulating layer 22 to be connected with the drain of the thin film transistor 11. The first conductive layer 19 includes the cathode of the photodiode 13. The semiconductor layer 21 of the photodiode 13 is disposed on a side of the first conductive layer 19 away from the base substrate 1, the semiconductor layer 21 includes an N-type semiconductor layer 21, an intrinsic semiconductor layer 21, and a P-type semiconductor layer 21, and the N-type semiconductor layer 21 of the photodiode 13 is connected to the first conductive layer 19. A second conductive layer 20 is disposed on a side of the cathode of the photodiode 13 away from the base substrate 1, the second conductive layer 20 including the anode of the photodiode 13. A second insulating layer 23 is disposed on a side of the first conductive layer 19, the first insulating layer 22 and the second conductive layer 20 away from the base substrate 1, and the planarization layer 24 and the scintillation layer 25 are sequentially disposed on a side of the second insulating layer 23 away from the base substrate 1.
In this example, the gate 14, the gate insulating layer 15, the active layer 16, and the first metal layer 17 constitute the structure of the above-described thin film transistor 11; the active layer 16 is used to form a conductive channel of the thin film transistor 11, and the first metal layer 17 is used to constitute the source and the drain of the thin film transistor 11. The first insulating layer 22 is used to protect the active layer 16 and the source and the drain of the thin film transistor 11. The first conductive layer 19 is used to form the cathode of the photodiode 13, and the first conductive layer 19 is used to electrically connect the drain of the thin film transistor 11 with the cathode of the photodiode 13. The second conductive layer 20 includes the anode of the photodiode 13, and the second conductive layer 20 is used to output an electric signal of the photodiode 13. The second insulating layer 23 is used to protect the thin film transistor 11 and the photodiode 13, and the planarization layer 24 is used to planarize the structures of the thin film transistor 11 and the photodiode 13 and to facilitate the arrangement of the scintillator layer 25. The scintillation layer 25 is used to convert X-rays projected onto a surface of the flat panel detector into visible light.
In this example, a method for manufacturing the thin film transistor 11 and the photodiode 13 in the detecting unit 2 may include the following steps S11 to S17.
At step S11, the gate 14, the gate insulating layer 15, and the active layer 16 of the thin film transistor 11 and the first metal layer 17 are sequentially formed on the base substrate through a patterning process.
In the present embodiment, the base substrate may be made of a transparent material such as glass, and may be pre-cleaned. Specifically, first, a gate metal film layer is formed on the base substrate by a sputtering method, a thermal evaporation method, a plasma enhanced chemical vapor deposition (PECVD) method, a low pressure chemical vapor deposition (LPCVD) method, an atmospheric pressure chemical vapor deposition (APCVD) method, or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method. Then, a pattern of the gate 14 is formed by using a halftone mask (HTM) or a graytone mask (GTM) through a patterning process (which includes film formation, exposure, development, wet etching or dry etching). The gate 14 may be made of a metal or a metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, copper, or other conductive materials.
Next, the gate insulating layer 15 is formed on the gate 14 by using the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, the electron cyclotron resonance chemical vapor deposition method, or the sputtering method. Then, an amorphous silicon film is deposited on the gate insulating layer 15 by the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, or the like, and the amorphous silicon film is crystallized and subjected to a patterning process to form a pattern of the active layer 16.
Finally, the first metal layer 17 is formed on the gate and the gate insulating layer by the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, the electron cyclotron resonance chemical vapor deposition method, or the sputtering method, and the first metal layer 17 is subjected to a single patterning process to form a pattern including the source and the drain of the thin film transistor 11.
At step S12, the first insulating layer 22 is formed through a patterning process, and a first via hole 18 is formed to penetrate the first insulating layer 22 at a position of the first insulating layer 22 corresponding to the drain.
Specifically, in this step, a passivation film layer may be deposited by the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, or the electron cyclotron resonance chemical vapor deposition method, and the passivation film layer is subjected to a patterning process including masking, dry etching and the like to form the first via hole 18. The first insulating layer 22 is an inorganic insulating layer formed of silicon nitride (SiNx), an inorganic insulating layer formed of silicon oxide (SiO2), or a composite film layer in which at least one inorganic insulating layer made of SiNx and at least one inorganic insulating layer made of SiO2 are stacked.
At step S13, a pattern including the cathode of the photodiode 13 is formed through a patterning process, and the pattern is connected to the drain of the thin film transistor 11 through the first via hole 18.
Similar to the formation process of the source and the drain of the thin film transistor 11, in this step, the first conductive layer 19 may be deposited on the first insulating layer 22 by the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, the electron cyclotron resonance chemical vapor deposition method, or the sputtering method, and the first conductive layer 19 may be subjected to a patterning process, including masking, wet etching and the like, to form a pattern of the cathode of the photodiode 13.
The first conductive layer 19 may be made of a conductive material such as a metal or a metal alloy, for example, molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper.
At step S14, a semiconductor material layer is deposited on the first conductive layer 19, and a patterning process is performed on the semiconductor material layer to form a pattern including the semiconductor layer 21 of the photodiode 13.
In the present embodiment, the base substrate of the flat panel detector includes a photodiode region, and the semiconductor layer 21 is located at a position, corresponding to the photodiode region, on the base substrate. The semiconductor material layer may specifically include an N-type semiconductor material layer, an I-type semiconductor material layer, and a P-type semiconductor material layer. The semiconductor material layer is deposited on an etching block material layer by the plasma enhanced chemical vapor deposition method or the low pressure chemical vapor deposition method.
A portion of the semiconductor material layer outside the photodiode region is removed by a dry etching process such as a plasma etching (PE), a reactive ion etching (RIE), an enhanced capacitive coupled plasma etching (ECCP), and an inductively coupled plasma etching (ICP) to form the semiconductor layer 21.
At step S15, a pattern including the anode of the photodiode 13 is formed through a patterning process, the anode of the photodiode 13 being disposed on a side of the semiconductor layer 21 away from the base substrate 1, and being connected with the semiconductor layer 21.
In this step, the second conductive layer 20 may be deposited on the semiconductor layer 21 by the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, the electron cyclotron resonance chemical vapor deposition method, or the sputtering method, and the second conductive layer 20 is subjected to a patterning process such as masking and wet etching to form a pattern of the anode of the photodiode 13. A material of the second conductive layer 20 may be a conductive material such as a metal or a metal alloy, for example, molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper.
At step S16, the second insulating layer 23 is formed on the first insulating layer 22 and the photodiode 13, where the forming process and material of the second insulating layer 23 may be similar to those of the first insulating layer 22, and therefore are not described herein again.
At step S17, the planarization layer 24 is formed on the second insulating layer 23.
A material of the planarization layer 24 includes resin, and a thickness thereof is relatively large so as to play a planarizing function on the base substrate of the flat panel detector. Specifically, similar to the formation of the first insulating layer 22, in this step, the planarization layer 24 may be deposited by the plasma enhanced chemical vapor deposition method, the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, or the electron cyclotron resonance chemical vapor deposition method.
The material of the planarization layer 24 may include an organic insulating material, for example, a resin material such as polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane. As another example, the organic insulating material includes an elastic material, such as urethane, and thermoplastic polyurethane (TPU).
So far, the manufacturing of the thin film transistor 11 and the photodiode 13 on the base substrate of the flat panel detector is completed.
As shown in
A working principle of the flat panel detector is as follows: X-rays are modulated by a human body on their way, the modulated X-rays are converted into visible light by the scintillation layer 25, the photodiode 13 absorbs the visible light and converts it into charge carriers, which are stored in a storage capacitor or a self capacitor of the photodiode 13 to form a charge image, the plurality of rows of thin film transistors 11 are sequentially turned on by a scan driving circuit, and charge images of a same row of thin film transistors are simultaneously readout and output to the data lines 4. The charge images output from all the thin film transistors 11 are processed to generate a desired detection image.
In practical applications, the inventors found that, since the bias signal lines 6 disposed in the second direction on the exemplary base substrate 1 are short-circuited with the ring-shaped bias signal line 6 disposed in the edge area of the detecting units 2, and therefore the bias signal lines 6 on the base substrate 1 are connected as a whole (that is, connected with each other). In a case where one of the driving chips 3 connected to the bias signal lines 6 is interfered and thus there is a deviation in the bias signal output from the driving chip, all the detecting units 2 on the base substrate 1 are affected since the bias signal lines 6 are connected as whole, thereby generating a large noise. Meanwhile, since the bias signal lines 6 are connected as a whole, the driving chip 3 susceptible to interference and the bias signal lines 6 cannot be specifically adjusted.
In view of the problems in the prior art, the inventor improves the prior art.
In a first aspect, as shown in
In the present embodiment, since the plurality of bias signal lines are divided into the plurality of signal line groups, the bias signal lines in different signal line groups are insulated from each other, and different signal line groups connect with different driving chips 3, in a case a certain driving chip 3 is interfered and there is a deviation in the bias signal output from the certain driving chip 3, only the bias signal of the signal line group connected with the certain driving chip 3 is affected, only the detecting units 2 connected with this signal line group are affected, and the noise is reduced. Furthermore, since each independent driving chip 3 is connected with the signal line group which is insulated from any other signal line group, the driving load of the driving chip 3 is relatively small, and when the bias signal of the signal line group is affected by external interference, the bias signal of the signal line group can be quickly restored to be normal, and the noise is reduced. Moreover, specific optimization adjustment can be performed on certain driving chips 3 or signal line groups, so that a grayscale image, obtained after an output operation signal is processed, is more uniform.
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In this way, the number of the driving chips 3 required to be provided is increased. That is, in a case where the total number of the bias signal lines 6 is constant, since each bias signal line 6 includes the first signal sub-line 61 and the second signal sub-line 62, the number of signal line groups into which the bias signal lines 6 can be divided is increased, and the number of the driving chips 3 connected to the signal line groups is increased. Therefore, the driving load of each driving chip 3 is reduced, and when the bias signal in the signal line group is interfered by external interference, the bias signal of the signal line group can be quickly restored to normal, and the noise is reduced. Since an area of the detecting units 2 covered by the bias signal lines 6 connected with each driving chip 3 is reduced, the area controlled by each driving chip 3 is finer, which is beneficial to specific optimization adjustment of certain driving chips 3 or signal line groups, so that the grayscale image obtained after an output electric signal is processed is more uniform.
In some implementations, the bias signal line 6 and the data line 4 may be disposed on the same side of the detecting unit 2, may be disposed on two sides of the detecting unit 2, respectively, or may be disposed to run through the detecting unit 2. In a case where the bias signal line 6 and the data line 4 are disposed on the same side of the detecting unit 2, orthographic projections of the bias signal line 6 and the data line 4 on the base substrate 1 are at least partially overlapped, so that the aperture ratio of the detecting unit 2 can be increased, and the detection capability of the detecting unit 2 can be improved; in a case where the bias signal line 6 runs through the detecting unit 2, the orthographic projection of the bias signal line 6 on the base substrate 1 is at least partially overlapped with an orthographic projection of the photosensitive device 12 on the base substrate 1, so that a contact efficiency between the bias signal line 6 and the photosensitive device 12 can be improved, and the conduction efficiency of the detecting unit 2 can be improved; in a case where the bias signal line 6 and the data line 4 are disposed at both sides of the detecting unit 2, respectively, the wiring arrangement of the flat panel detector described above is facilitated.
In some implementations, the thin film transistor 11 may include an amorphous silicon thin film transistor or a metal oxide thin film transistor 11. In some implementations, the thin film transistor 11 in the embodiment of the present disclosure is the amorphous silicon thin film transistor, so that the structure of the detecting unit 2 is simple and easy to manufacture.
In some embodiments, the photodiode 13 includes a PIN photodiode. The PIN photodiode has the advantages of having mature preparation process and being easy to manufacture.
In some implementations, a photoelectric conversion layer is disposed on a side of the detecting unit 2 away from the base substrate 1; the photoelectric conversion layer is configured to convert an external electric signal into an optical signal. For example, the photoelectric conversion layer may be a scintillator layer, and in such implementations, a material constituting the scintillator layer is a material capable of converting X-rays into visible light, such as CsI: Tl and Gd2O2S:Tb, and CsI:Na, CaWO4, CdWO4, Nal:TI, BaFCI:Eu2+, BaSO4:Eu2+, BaFBr:Eu2+, LaOBr:Tb3+, LaOBr:Tm3+, La2O2S:Tb3+, YTaO4, YTaO4:Nb, ZnS:Ag, ZnSiO4:Mn2+, Lil:Eu2+, and CeF3 are also possible. The visible light obtained by converting the X-rays by a scintillation crystal contained in the scintillator layer may have a peak value of a wavelength in a range from 530 nm to 580 nm, and a spectral range from 350 nm to 700 nm. Such light has short delay effect, and can be attenuated to below 1% of irradiation brightness of the X-rays within 1 ms after the X-rays disappear.
In a second aspect, the present disclosure provides a detecting apparatus including the flat panel detector. In the embodiment of the present disclosure, the flat panel detector may be an X-ray flat panel detector, and the detecting apparatus includes, but is not limited to, an X-ray diagnostic imaging system (including a C-arm, DSA (digital subtraction angiography), DRF (digital radiography & floroscopy), oral CBCT (oral cone-beam computed tomography), and the like), a radiotherapy apparatus, an X-ray industrial nondestructive inspection detection, a safety inspection, a pet medical diagnosis, and the like.
It will be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the present disclosure, and such modifications and improvements are also considered to be within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110896697.5 | Aug 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/109893 | 8/3/2022 | WO |
