These and/or other features and aspects of the invention will become apparent and are more readily appreciated from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings of which:
The embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those having skill in the art.
A lower substrate 10 includes a pixel area 20 and a non-pixel area 30. In the pixel area 20, a plurality of segment electrodes is formed in case of a super twisted nematic liquid crystal display (STN-LCD), or a plurality of pixel electrodes and a plurality of thin film transistors (TFTs) for controlling the operations of the respective pixels are arranged in case of a thin film transistor-liquid crystal display (TFT-LCD).
The non-pixel area 30 includes a peripheral region of the pixel area 20, e.g., an area outside of (or surrounding) the pixel area 20, and includes wirings 12 and 14 coupled with electrodes 72, 74 in the pixel area 20, a driving circuit 60 coupled with the electrodes in the pixel area 20 through the wirings 12 and 14, a shield wiring 70 arranged along the edge (or periphery), and a pad unit 16 coupled with the driving circuit 60 and the shield wiring 70. The driving circuit 60 is arranged on the substrate while manufacturing the elements, or manufactured as a driving circuit chip (i.e., a drive IC) to be mounted on the substrate via a tape automated bonding (TAB) or chip on a glass (COG) method. In
An upper substrate 40 is made of transparent glass or any other suitable material, and includes a plurality of common electrodes arranged in the region opposite to (i.e., facing) the pixel area 20.
The upper substrate 40 is arranged on the top of the lower substrate 10 so that the above-mentioned electrodes cross with each other. A sealed space is formed between the lower substrate 10 of the pixel area 20 and the upper substrate 40 using a sealing material 80 interposed between the lower and upper substrates 10 and 40. Here, the common electrodes of the upper substrate 40 are electrically coupled with the wirings of the lower substrate 10.
A plurality of pixels is defined by electrodes arranged in a matrix array on the lower and upper substrates 10 and 40, and a liquid crystal layer 50 is injected into the sealed space between the substrates.
The pad unit 16 of the flat panel display device configured as above is electrically coupled with a flexible printed circuit (FPC) 65 in the form of film. Signals from the outside are provided to the flat panel display device through the pad unit 16. The signals including power supply voltage, control signal, data, etc., are input to the pad unit 16 electrically connected with the driving circuit 60, and the pad unit 16 coupled with the shield wiring 70 is electrically connected to ground.
When a signal is input to the driving circuit 60 in a state where the shield wiring 70 is connected to ground through the FPC 65, the driving circuit 60 generates scanning signals and data signals to transmit the signals to the corresponding scan lines 12 and data lines 14, respectively. Accordingly, light corresponding to the data signals is emitted by a liquid crystal array of pixels selected by the scanning signals.
The flat panel display device in accordance with an exemplary embodiment of the present invention includes the shield wiring 70 arranged along the edge (or periphery) of the lower substrate 10. At least one side (or at least one end) of the shield wiring 70 is electrically connected to ground. In the described embodiment, the shield wiring 70 is formed to at least partly surround (e.g., formed along three of the four sides) the wirings 12 and 14 and the driving circuit 60. The shield wiring 70 may be formed with a material that has a resistance value lower than those of the wirings 12 and 14 or the same material as the wirings 12 and 14. In the described embodiment, the shield wiring 70 is formed wider than the wirings 12 and 14 so as to have a lower resistance value. By way of example, the shield wiring 70 may be formed of indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), potassium tin oxide (PTO), antimony tin oxide (ATO), antimony zinc oxide (AZO), In2O3, SnO2, ZnO, CdO, Cd2SnO4, Cd2InO4, In4Sn3O12, etc., and be fabricated at the same time as the wirings 12 and 14 during the manufacturing process or be made during a separate manufacturing process. In other embodiments, the shield wiring 70 may be formed with metals, such as molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), etc., or their alloys, or in a stacked structure including two or more of these metals and/or other suitable materials,
Accordingly, if an electrostatic discharge is applied to the surface or the side of the display panel, the electrostatic discharge is dissipated to the outside ground through the shield wiring 70 having a resistance value lower than those of the electrodes or the wirings 12 and 14, thus substantially preventing the driving circuit from being damaged.
The flat panel display device manufactured in accordance with the first exemplary embodiment of the present invention was tested in contact and non-contact modes in full compliance with International Electrotechnical Commission (IEC) 1000-4-2 standard. The electrostatic discharges of ±8 kV were applied to the flat panel display device of the first exemplary embodiment of the present invention ten times in the contact mode and the electrostatic discharges of ±15 kV were applied ten times in the non-contact mode. During the test, no defect caused by the electrostatic discharges was found in the display panel or the driving circuit.
A lower substrate 100 is composed of a pixel area 114 and a non-pixel area 116. In the pixel area 114, scan lines 122 and data lines 124 are arranged to cross each other and the organic light emitting diodes 120 are located at crossing regions of the scan lines 122 and the data lines 124 in a matrix array to configure pixels.
The non-pixel area 116 is a peripheral region of the pixel area 114, e.g., an area outside of (or surrounding) the pixel area 114, and includes the scan lines 122, the data lines 124, that are extended from the scan lines 122 and the data lines 124 of the pixel area 114, respectively, a power voltage supply line, which is not depicted in
The scan driving unit 130 and the data driving unit 140 may be formed on the lower substrate 100 of the non-pixel area 116 during the process of manufacturing the organic light emitting diodes 120, or manufactured as a driving circuit chip (i.e., a drive IC) and mounted on the substrate 100 to be coupled with the scan lines 122 and the data lines 124 via a tape automated bonding (TAB), a chip on glass (COG) or a wire bonding method.
In a passive matrix type display device, the organic light emitting diodes 120 are coupled between the scan lines 122 and the data lines 124 in a matrix array, whereas, in an active matrix type display device, the organic light emitting diodes 120 are connected between the scan lines 122 and data lines 124 in a matrix array, and thin film transistors (TFTs) for controlling the operations of the organic light emitting diodes 120 and capacitors for maintaining the signal are further included.
A buffer layer 101 is formed on the lower substrate 100, and a semiconductor layer 102 providing an active layer is formed on the buffer layer 101. The semiconductor layer 102 provides a source area, a drain area and a channel area for a thin film transistor. A gate insulating film 103 is formed on the overall top surface including the semiconductor layer 102, and a gate electrode 104 is formed on the gate insulating film 103 on the top of the semiconductor layer 102. An interlayer insulating film 105 is formed on the overall top surface including the gate electrode 104, and contact holes are formed via the interlayer insulating film 105 and the gate insulating film 103 to expose specific parts of the semiconductor layer 102. A source electrode 106a and a drain electrode 106b connected with the semiconductor layer 102 through the contact holes are provided on the interlayer insulating film 105, and a planarization layer 107 is formed on the overall top surface including the source and drain electrodes 106a and 106b. A via hole is established via the planarization layer 107 to expose the source electrode 106a or the drain electrode 106b, and an anode electrode 108 coupled with the source electrode 106a or the drain electrode 106b through the via hole is provided on the planarization layer 107. Moreover, a pixel defining film 109 for exposing the anode electrode 108 in the light emitting region is formed on the planarization layer 107, and an organic thin film layer 110 and a cathode electrode 111 are provided on the exposed anode electrode 108. The organic thin film layer 110 may be formed having a structure where a hole transfer layer, an organic emission layer and an electron transfer layer are stacked, in which a hole injection layer and an electron injection layer may be further included.
In the organic light emitting diode 120 configured as above, when suitable voltages (e.g., predetermined voltages) are applied to the anode electrode 108 and the cathode electrode 111, holes injected from the anode electrode 108 and electrons injected from the cathode electrode 111 are coupled with each other in the organic thin film layer 110, thus emitting light by the energy difference generated during the coupling process.
A sealed space is formed between the lower substrate 100 of the pixel area 114 and the upper substrate 200 using a sealing material, which is not depicted in
The pad unit 126 of the flat panel display device in accordance with an exemplary embodiment of the present invention is electrically coupled with a flexible printed circuit (FPC) 127 in the form of film, through which signals including power supply voltage, control signal, data, etc., are input from the outside. In one embodiment, the pad unit 126 (i.e., one of the contacts/terminals of the pad unit 126) coupled with the shield wiring 170 is electrically connected to ground.
When signals are input to the scan driving unit 130 and the data driving unit 140 in a state where the shield wiring 170 is connected to ground through the FPC 127, the scan driving unit 130 and the data driving unit 140 generate scanning signals and data signals to transmit the signals to the corresponding scan line 122 and data line 124, respectively. Accordingly, light corresponding to the data signals are emitted by the organic light emitting diodes 120 selected by the scanning signals.
The flat panel display device in accordance with an exemplary embodiment of the present invention includes the shield wiring 170 arranged along the edge (or periphery) of the lower substrate 100 and at least one side (or at least one end) of the shield wiring 170 is connected to ground. Here, the shield wiring 170 is formed to at least partly surround (e.g., formed along three of the four sides) the scan lines 122, the data lines 124, the scan driving unit 130 and the data driving unit 140. The shield wiring 170 may be formed with a material that has a resistance value lower than those of the scan line 122 and the data line 124 or the same material as the scan line 122 and the data line 124. In the described embodiment, the shield wiring 170 is formed wider than the scan line 122 and the data line 124 so as to have a lower resistance value. For example, the shield wiring 170 may be formed with metals, such as molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), etc., or their alloys, or in a stacked structure including two or more of these metals and/or other suitable materials, and be fabricated at the same time as the scan lines 122 and the data lines 124 during the manufacturing process or be made during a separate manufacturing process.
Accordingly, if an electrostatic discharge is applied to the surface or the side of the display panel, the electrostatic discharge is dissipated to the outside ground through the shield wiring 170 having a resistance value lower than those of the scan line 122 and the data line 124, thus substantially preventing the driving circuit from being damaged.
As described in detail above, the present invention forms the shield wiring along the edge (or periphery) of the substrate and connects at least one side (or at least one end) of the shield wiring to ground. Accordingly, the electrostatic discharge is dissipated to the outside ground through the shield wiring having a resistance value lower than those of the electrodes or the wirings, thus preventing the display panel and the driving circuit from being damaged, to improve the durability. Moreover, the present invention does not require an additional element or a protection circuit for preventing electrostatic discharges, thus reducing the manufacturing cost as well as the volume of the device. Further, while the embodiments of the present invention are described primarily in reference to LCD and/or OLED displays, the principles of the present invention can be applied to any other suitable display devices.
As above, exemplary embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims and their equivalents.
Number | Date | Country | Kind |
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10-2006-0087396 | Sep 2006 | KR | national |