Claims
- 1. A process for fabricating a flat panel display, wherein said flat panel display comprises a faceplate and a baseplate, said process comprising the steps of:forming a first portion of a capacitor on an inner surface of said faceplate; forming a second portion of a capacitor on an inner surface of said baseplate; energizing said first and second portions of said capacitor using opposite polarity voltages to create an attractive force between said faceplate and baseplate and draw said first and second portions together; and attaching said baseplate and faceplate to each other while said attractive force is present.
- 2. The process for fabricating a flat panel display of claim 1, wherein said attaching step further comprises forming a seal between said faceplate and baseplate.
- 3. The process for fabricating a flat panel display of claim 1, further comprising the step of de-energizing said first and second portions of said capacitor to remove the attractive force between the faceplate and baseplate.
- 4. The process for fabricating a flat panel display of claim 1, wherein the first portion comprises a first metal plate and a dielectric material and the second portion comprises a second metal plate.
- 5. The process for fabricating a flat panel display of claim 1, wherein the second portion comprises a first metal plate and a dielectric material and the first portion comprises a second metal plate.
- 6. The process for fabricating a flat panel display of claim 1, wherein the first portion comprises a dielectric material and a first metal plate, and the second portion comprises a dielectric material and a second metal plate.
- 7. A process for fabricating a flat panel display, wherein said flat panel display comprises a faceplate and a baseplate, said process comprising the steps of:forming a plurality of interdigitated conductors on said baseplate; energizing a first plurality of said conductors to a first polarity voltage; energizing a second plurality of said conductors to a second polarity voltage; placing said faceplate in proximity to said baseplate while said conductors are energized; and attaching said baseplate and faceplate to each other while said first and second plurality of conductors are energized to said first and second polarity voltages, respectively.
- 8. The process for fabricating a flat panel display of claim 7, wherein said attaching step further comprises forming a seal between said faceplate and baseplate.
- 9. The process for fabricating a flat panel display of claim 7, further comprising the steps of de-energizing said first and second plurality of conductors.
- 10. A process for fabricating a flat panel display, wherein said flat panel display comprises a faceplate and a baseplate, said process comprising the steps of:forming a plurality of interdigitated conductors on said faceplate; energizing a first plurality of said conductors to a first polarity voltage; energizing a second plurality of said conductors to a second polarity voltage; placing said baseplate in proximity to said faceplate while said conductors are energized; and attaching said baseplate and faceplate to each other while said first and second plurality of conductors are energized to said first and second polarity voltage, respectively.
- 11. The process for fabricating a flat panel display of claim 10, wherein said attaching step further comprises forming a seal between said faceplate and baseplate.
- 12. The process for fabricating a flat panel display of claim 10, further comprising the steps of de-energizing said first and second plurality of conductors.
- 13. A process for fabricating a flat panel display, wherein said flat panel display comprises a faceplate having a pixel matrix and a baseplate having a cathode member, said process comprising the steps of:forming a first portion of at least one capacitor on said faceplate, wherein said first portion of said at least one capacitor is aligned with said pixel matrix; forming a second portion of said at least one capacitor on said baseplate, wherein said second portion of said at least one capacitor is aligned with said cathode member; energizing said first and second portions of said at least one capacitor using opposite polarity voltages to create an attractive force between said first and second portions of said at least one capacitor which aligns and temporarily attaches said first and second portions of said at least one capacitor with each other; and attaching said baseplate and faceplate to each other while said first and second portions of said at least one capacitor are aligned and attached to each other.
- 14. The process for fabricating a flat panel display of claim 13, wherein during said energizing step said pixel matrix and said cathode member are automatically aligned with each other.
- 15. The process for fabricating a flat panel display of claim 13, further comprising the step of de-energizing said first and second portions of said at least one capacitor to remove the attractive force between the faceplate and baseplate.
- 16. A process for fabricating a flat panel display which includes a faceplate and a baseplate, comprises:forming a first portion of at least two capacitors on opposite corners of said faceplate; and forming a second portion of at least two capacitors on opposite corners of said baseplate.
- 17. The process for fabricating a flat panel display of claim 16, further comprisesattaching said baseplate and faceplate to each other while said first and second portions of said at least two capacitors are aligned and attached to each other.
- 18. The process for fabricating a flat panel display of claim 17, wherein said attaching step further comprises forming a seal on one of said faceplate and said baseplate.
- 19. The process for fabricating a flat panel display of claim 16, further comprising the step of applying an electric field between respective portions of said capacitors.
- 20. A process for fabricating a flat panel display, wherein said flat panel display comprises a faceplate and a baseplate, said process comprising the steps of:aligning corresponding locations on the faceplate and the baseplate by creating an electric field between said faceplate and said baseplate to at least temporarily attract said faceplate to said baseplate at said corresponding location; and attaching said baseplate and faceplate to each other while said electric field is present, wherein said locations comprise portions of a capacitor.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of U.S. patent application Ser. No. 09/170,705, filed Oct. 13, 1998 now U.S. Pat. No. 6,392,334.
US Referenced Citations (13)
Non-Patent Literature Citations (2)
Entry |
Shen and Konh, “Force on Dielectric Material”, Applied Electromagnetism, 2nd Ed., pp. 327-331 (No date). |
Lee Branst, Floyd Pothoven, “The Challenge of Flat Panel Displan Sealing”, Jan. 1996, Semiconductor International, pp. 109-112. |