Patent Application
20070057977
1. Field of the Invention
The present invention relates to protection against electrostatic discharge. More specifically, the present invention discloses a structure for protection of flat panel displays from damages due to electrostatic discharge.
2. Description of the Prior Art
Traditionally, electrostatic damage protection circuitry for flat panel displays focus on protection during the manufacturing process. However, electrostatic discharge (ESD) damage can result in high scrap and failure rates, during the final stages of manufacturing and during use respectively.
Please refer to
However, despite the protection that this provides, the flat panel displays are still frequently damaged by electrostatic discharge. Flat panel displays are typically very expensive, and such damage is costly to manufacturers and users.
There are numerous levels of screen resolution. The resolution is determined by the number of pixels that a display contains. For example, VGA has 640 columns and 480 rows, SVGA has 800 columns and 600 rows, XGA has 1024 columns and 768 rows, SXGA has 1280 columns and 1024 rows, SXGA Plus has 1400 columns and 1050 rows, UXGA has 1600 columns and 1200 rows, and WUXGA has 1920 columns and 1200 rows. Currently, a typical driver IC is capable of driving 480 signal lines. However, other driver ICs may have lesser or greater capabilities. Therefore, in order to provide a resolution of WUXGA, at least 12 standard source driver ICs, each capable of driving 480 lines, are required.
Please refer to Table 1, which shows the active area voltages for given input voltages for the prior art flat panel display as shown in
In the test producing the results shown in Table 1, the driver IC chips (more specifically, the source driver IC chips 61 and gate driver IC chips 62 shown in
The input voltage used in the test was a 1 ms pulse. The active area voltage was measured at the input of the active area loading.
Of particular note is the worst case situation of the 1920 pin input where the active area voltage is 85% to 97% of the input voltage. In this instance, the maximum distance between coupling points is 1920 signal lines.
The higher the active area voltage shown in Table 1, the more likely it is that the display will be damaged, and hence the greater the need for better protection against ESD.
Therefore there is need for improvement in electrostatic damage protection which prevents damage to display panels or circuitry from electrostatic discharge.
To achieve these and other advantages and in order to overcome the disadvantages of the conventional method in accordance with the purpose of the invention as embodied and broadly described herein, the present invention provides an electrostatic discharge protection device comprising a plurality of common voltage points arranged among the signal lines of a driver integrated circuit chip and between driver ICs, thereby reducing the maximum electrical distance between a signal line and a common voltage point.
The present invention further provides a method for protecting flat panel displays from electrostatic damage, by providing a plurality of common voltage input points for each driver integrated circuit chip.
The present invention provides a flat panel display electrostatic discharge protection circuit comprising a driver integrated circuit used in the flat panel display through a plurality of signal lines. The plurality of signal lines comprise a first compensation line arranged on one of two edge sides of the plurality of signal lines and a second compensation line arranged between two edge sides of the plurality of signal lines. The first compensation lines and the second compensation line couple to a shorting bar circuit for providing a common voltage. A plurality of first protection circuits are provided between the shorting bar circuit and the driver integrated circuit. The plurality of first protection circuits comprise a pair of voltage control elements connected in parallel in inverse polarity. The voltage control elements are selected from diodes, transistors and resistors. The shorting bar further connects to a second protection circuit for anti-electrostatic discharge. Furthermore, the distance between the first compensation line and the second compensation line is less than or equal to the distance between two of the first compensation lines.
In the present invention, a plurality of Vcommon or common voltage input pads are provided on both sides of the driver integrated circuits and in the middle of the outer lead bonding (OLB) pads connecting the signal lines to the driver integrated circuits. This substantially increases the electrostatic discharge protection level.
The present invention further allows providing more than one Vcommon pad situated at different places between signal lines. For example, two Vcommon pads could be provided at positions of ⅓ and 2/3 of the driver IC width instead of one Vcommon pad at 1/2 of the driver IC width.
These and other objectives of the present invention will become obvious to those of ordinary skill in the art after reading the following detailed description of preferred embodiments.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Analysis of electrostatic discharge damage to flat panel displays shows that ESD resistance is unrelated to diode dimensions. Also, the resistance and capacitance of the fan-out line, the common line, and the signal line can not account for the ESD difference. To reduce the voltage, it is necessary to reduce the maximum electrical distance between the signal lines and the common voltage Vcommon.
Please refer to
The second fanout RC loading circuit 12 is coupled to an active area RC loading circuit 13. Between the second fanout RC loading circuit 12 and the active area RC loading circuit 13 is a measuring point 15 at which test measurements of voltages were taken during testing.
The voltage control elements 14 are coupled to Vcom by one of two common shorting bars 2e,2o. The odd signal lines 10o are coupled to the odd common shorting bar 2o, while the even signal lines 10e are coupled to the even common shorting bar 2e. In addition, the even common shorting bar 2e is further coupled at each end to a pair of voltage control elements 3e for electrostatic discharge issue. The odd common shorting bar 2o is also further coupled at each end to a pair of voltage control elements 3o for anti-electrostatic discharge. The voltage control elements 3e, 3o are coupled to Vcom through a common voltage coupling point 1.
The voltage control elements 3e, 3o and 14 are illustrated in
Please refer to
In
In this embodiment, a first driver integrated circuit and a second driver integrated circuit disposed next to the first driver integrated circuit are coupled with the display panel. A first common voltage coupling point is arranged between the first driver integrated circuit and the second driver integrated circuit. A second common voltage coupling point is arranged within each of the first and second driver integrated circuits. A common voltage line is coupled to the first and the second common voltage coupling points. A plurality of protection circuits are coupled between the common voltage line and each of the first and second driver integrated circuits. The first common voltage coupling point is coupled to the first driver integrated circuit and the second driver integrated circuit. In this embodiment, the distance between the first and the second common voltage coupling point of the first driver integrated circuit is equal to the distance between the first and the second common voltage coupling point of the second driver integrated circuit.
Refer to
In
In this embodiment, two second common voltage coupling points 2 are provided for each driver IC 61, which further minimizes the distance between common voltage coupling points.
In other words, a distance between the first common voltage coupling point 1 and the neighbouring second common voltage coupling point 2 is the same as that of two neighbouring second common voltage coupling points 2.
Alternate embodiments may use larger numbers of second common voltage coupling points 2 per driver IC chip, typically arranged to minimize the maximum distance between any signal line and the common voltage line, thereby further reducing the potential for damage due to ESD from excessive active area voltage.
For example, an embodiment with K second common voltage coupling points 2 per chip and a the plurality of first common voltage line coupling points 1 located at each end of the edge of the display and on both sides of each driver IC chip will have ((K+1)*M)+1 common voltage coupling points 1,2 for the signal lines of the source driver IC chips 61 and ((K+1)*N)+1 common voltage coupling points 1,2 for the signal lines of the gate driver IC chips 62.
Thus, if two common voltage coupling points are provided between the OLB pads connecting to the driver IC, the width of the circuitry illustrated in
Obviously, the spacing of the Vcom pads does not have to be equal and the size of the Vcom pads can be smaller, larger, or substantially the same size as the OLB pads.
Refer to
The flat panel display in this embodiment comprises one second common voltage coupling point 2 per chip and a pair of first common voltage coupling points 1 at each end of the edge of the display.
In
And for example, an embodiment with K second common voltage coupling points 2 per chip and a pair of first common voltage coupling points 1 at each end of the edge of the display will have at least (K*M)+2 common voltage coupling points 1,2 for the signal lines of the source driver IC chips 61 and (K*N)+2 common voltage coupling points 1,2 for the signal lines of the gate driver IC chips 62.
Furthermore, if three second common voltage coupling points are provided to each of the driver ICs, the preferred width between the pair of first common voltage coupling points is divided equally into 3M+1 parts for any two common voltage coupling points. In other word, the distance between the first common voltage coupling point 1 and the neighbouring second common voltage coupling point 2 could be less than or equal to that of two neighbouring second common voltage coupling points 2 of two neighbouring driver ICs or within one driver IC.
Please refer to Table 2, which shows the active area voltages at given input voltages for a flat panel display using the ESD protection method and circuitry of the present invention according to the layout of
In the test producing the results shown in Table 2, the driver IC chips (more specifically, the source driver IC chips 61 and gate driver IC chips 62 shown in
The input voltage used in the test was a 1 ms pulse. The active area voltage was measured at the input of the active area loading.
The active area voltage for a flat panel display using the ESD protection method and circuitry of the present invention is lower in all cases than the active area voltage for a prior art flat panel display; and at 2000 input volts, is less than one fourth the voltage of the prior art display. The worst case, in panels with 2040 signal line pin input at 2000 volts, is only about 52% of the worst case of the prior art, at 1920 pins input at 2000 volts. This significantly reduces the risk of damage due to ESD.
In the worst case mentioned above, the maximum distance between coupling points or common voltage points is the space of 240 signal lines since there is one Vcommon pad to the left of the first signal line of each driver IC, one Vcommon pad to the right of the last or 480th signal line and one in the middle approximately next to the 240th signal line. This shortened distance dramatically improves the ESD protection of the display.
Alternatively, additional common voltage points can be added. For example, a plurality of common voltage point can be provided between the signal lines, such as three or four points to further decrease the maximum distance between points.
Comparing other values between tables 1 and 2, it is easy to see the dramatic improvement that the present invention provides in protecting against ESD damage.
Refer to
As shown in
As shown in
Furthermore, the ESD protection circuit connected to the common voltage pads can comprise diodes, resistors, capacitors, transistors, or other electronic devices configured to provide ESD protection.
The method and device of the present invention are useful in flat panel displays made with thin film transistor liquid crystal displays (TFT LCD), organic light emitting diodes (OLED), and similar displays using driver IC chips to address pixels in two dimensions.
The electrostatic damage protection device and method of the present invention thus provide a substantial improvement over the prior art by dramatically lowering the peak voltages of electrostatic discharges during manufacturing and use of the flat panel display, thereby lowering failure rates and providing longer service life.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the invention and its equivalent.
