Flexible architecture for processing of large numbers and method therefor

Abstract

A method of implementing large number multiplication and exponentiation is provided upon a general purpose microprocessor. These large number multiplication and exponentiation processes being common to cryptography standards such as RSA and AES that typically employ numbers with 512-bits, 1024-bits, and 2048-bits. According to the invention the method establishes the size of the large number processes according to value stored within a control register, this control register and other registers storing data are configured according to this value and accessed as N-bit registers (i.e. as 1024-bit registers for 1024-bit encryption. Additionally, the multiplication and exponentiation processes are handled according to the size of an arithmetic primitive, which is established according to the hardware configuration upon which the process is operating. As such the invention allows for an encryption process to adjust both to the configuration of the host microprocessor and supporting hardware/firmware and dynamically according to degree of security determined from the value stored within the control register.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which similar reference numbers designate similar items:

FIG. 1 shows a simplified block diagram of an encryption processor for implementing a single encryption process;

FIG. 2 shows a simplified block diagram of an encryption processor for implementing a plurality of encryption processes, each encryption process supported by a different processing core;

FIG. 3 shows a simplified block diagram of a processor for implementing a plurality of security processes within a single core according to an embodiment of the invention; and,

FIG. 4A is a first simplified flow diagram of a method providing flexibility in encryption process for use with the encryption processor of FIG. 3 according to an embodiment of the invention.

FIG. 4B is a second simplified flow diagram of a method providing flexibility in encryption process for use with the encryption processor of FIG. 3 according to an embodiment of the invention . . .

FIG. 5 is an exemplary deployment scenario of an embodiment of the invention within two different computer systems, one a desktop computer, the other a cellular telephone.

FIG. 6 is an exemplary flow diagram of an embodiment of the invention configuring execution of a large number multiplicand program according to the configuration of the hardware platform.

Claims

1. A method comprising: providing a control register, the control register for storing a value, the value associated with a size of a large number;providing a multiplicand program, the multiplicand program providing a process according to a predetermined standard and comprising at least a multiplication operation applied to a large number of a predetermined size, the predetermined size being determined at least in dependence of the value read from the control register by the multiplicand program.

2. A method according to claim 1 wherein, the predetermined standard is at least one of an encryption process, a decryption process, the Advanced Encryption Standard, and RSA cryptography.

3. A method according to claim 1 comprising; storing at least one of the large number and the result of the multiplication process in a process register, the process register being one of a plurality of process registers;accessing at least one of the control register and the at least one of the plurality of process registers as N-bit values, the N-bit value being determined in dependence upon the value stored within the control register.

4. A method according to claim 3 comprising; providing a register sub-system, the register sub-system automatically adjusting an access mechanism to ensure at least one of the control register and the plurality of process registers are the correct size for storing N-bit values.

5. A method according to claim 1 comprising; providing a processor, the processor for executing the multiplicand program, the processor performing the at least a multiplication operation according to predetermined size of an arithmetic logic unit of the processor.

6. A method according to claim 5 wherein, the multiplicand program executes independent of the arithmetic logic unit of the processor.

7. A method according to claim 5 wherein, the multiplicand program automatically adjusts in dependence upon the arithmetic logic unit.

8. A method according to claim 5 wherein, the predetermined size of the arithmetic logic unit of the processor is determined in dependence upon a configuration of hardware electrically connected to the processor, the hardware comprising at least a memory circuit.

9. A method according to claim 3 comprising; providing a processor, the processor for executing the multiplicand program, the processor performing the at least a multiplication operation according to predetermined size of an arithmetic logic unit of the processor.

10. A method according to claim 9 wherein, the multiplicand program executes independent of the arithmetic logic unit of the processor.

11. A method according to claim 9 wherein, the multiplicand program automatically adjusts in dependence upon the arithmetic logic unit.

12. A method according to claim 1 wherein, the value stored within the control register is established by a process other than the multiplicand program.

13. A method according to claim 3 wherein, the N-bit number is determined by raising base 2 to a predetermined power, the predetermined power being the value stored in the control register.

14. A method according to claim 1 wherein, the value stored within the control register is at least one of fixed during execution of the multiplicand program and dynamically assigned during execution of the multiplicand program.

15. A method according to claim 1 comprising; providing a processor, the processor for executing the multiplicand program, the processor performing the at least a multiplication operation according to a predetermined size of an arithmetic logic unit of the processor.

16. A method according to claim 15 wherein, the multiplicand program at least one of executes independent of the arithmetic logic unit of the processor and automatically adjusts in dependence upon the arithmetic logic unit.

17. A method according to claim 15 wherein, the predetermined size of the arithmetic logic unit of the processor is determined in dependence upon at least one of the processor and a memory connected to the processor.

18. A circuit comprising: a control register, the control register for storing a value, the value associated with a size of a large number;a memory, the memory for storing a multiplicand program, the multiplicand program providing a process according to a predetermined standard and comprising at least a multiplication operation applied to a large number of a predetermined size, the predetermined size being determined at least in dependence of the value read from the control register by the multiplicand program.

19. A circuit according to claim 18 wherein, the predetermined standard is at least one of an encryption process, a decryption process, the Advanced Encryption Standard, and RSA cryptography.

20. A circuit according to claim 18 comprising; a process register, the process register being one of a plurality of process registers for storing at least one of the large number and the result of the multiplication process.

21. A circuit according to claim 20 wherein, access of at least one of the control register and the at least one of the plurality of process registers comprises accessing the register as an N-bit value, the N-bit value being determined in dependence upon the value stored within the control register.

22. A circuit according to claim 21 comprising; a register sub-system, the register sub-system automatically adjusting an access mechanism of at least one of the control register and the plurality of process registers to provide registers of the correct size for storing N-bit values.

23. A circuit according to claim 18 comprising; a processor, the processor executing the multiplicand program and performing the at least a multiplication operation according to a predetermined size of an arithmetic logic unit of the processor.

24. A circuit according to claim 23 wherein, the multiplicand program executes independent of the arithmetic logic unit of the processor.

25. A circuit according to claim 23 wherein, the multiplicand program automatically adjusts in dependence upon the arithmetic logic unit.

26. A circuit according to claim 23 wherein, the predetermined size of the arithmetic logic unit of the processor is determined in dependence upon at least one of the processor and a memory connected to the processor.

27. A circuit according to claim 20 comprising; a processor, the processor executing the multiplicand program and performing the at least a multiplication operation according to a predetermined size of an arithmetic logic unit of the processor.

28. A circuit according to claim 27 wherein, the multiplicand program executes independent of the arithmetic logic unit of the processor.

29. A circuit according to claim 27 wherein, the multiplicand program automatically adjusts in dependence upon the arithmetic logic unit.

30. A circuit according to claim 18 wherein, the value stored within the control register is established by a process other than the multiplicand program.

31. A circuit according to claim 21 wherein, the N-bit number is determined by raising base 2 to a predetermined power, the predetermined power being the value stored in the control register.

32. A circuit according to claim 18 wherein, the value stored within the control register is at least one of fixed during execution of the multiplicand program and dynamically assigned during execution of the multiplicand program.

33. A circuit according to claim 19 comprising; a processor, the processor for executing the multiplicand program and performing the at least a multiplication operation according to predetermined size of an arithmetic logic unit of the processor.

34. A processor comprising: an integrated circuit comprising: a processor core comprising hardware for implementing a plurality of commands, each command addressable by an instruction, the plurality of commands including a first plurality of large number processing operations including an operation common to a plurality of encryption processing processes, and a second plurality of processing operations including an operation common to general purpose microprocessors; and,a program controller for retrieving of instruction data and for executing a series of instructions in response to the instruction data, the series of instructions for resulting in security processing, the instruction data reprogrammable for supporting different security processes and modifications to security processes.

35. A processor according to claim 34 comprising a memory store for storing of the instruction data therein.

36. A processor according to claim 35 wherein the integrated circuit comprises the memory store for storing of the instruction data therein.

37. A processor according to claim 36 wherein the processor forms a dedicated encryption processor for performing on data provided thereto one or more of a known set of encryption processes supported by the processor.

38. A processor according to claim 37 wherein some of the known set of encryption processes supported by the processor are supported in a sub optimal fashion that is partially optimized over a general purpose processor implementation of same.

39. A processor according to claim 34 wherein the first plurality of large number processing operations includes: large number multiplication, large number shifting and large number Boolean operations.

40. A method of encryption processing comprising: providing a processor having a core for supporting a first plurality of large number processing operations including an operation common to encryption processing, a second plurality of processing operations including an operation common to general purpose microprocessors, and program execution;providing a first transform for use in transforming of data from a first form to a second form;re-characterizing the transform as a second transform for performing a same transformation, the second transform utilizing operations from the first plurality of large number processing operations; and,providing micro code instruction data for performing the second transform.

41. A method according to claim 40 wherein the first transform includes a first known set of processing operations having N operations supported by the processor and wherein the second transform includes second set of processing operations having M operations wherein M is substantially less than N.

42. A method according to claim 41 wherein the M operations execute in less time than the N operations execute.

43. A method according to claim 42 wherein the M operations includes a large number processing operation from the first plurality of large number processing operations.

44. A method according to claim 40 wherein the first transform includes a first known set of processing operations including a first operation and wherein the second transform includes second set of processing operations for performing the first operation, the set of processing operations having more than one operation and including the operation common to encryption processing.

45. A method according to claim 40 wherein the first transform is other than a transform for which the processor was specifically designed.

46. A method according to claim 45 wherein the first plurality of large number processing operations includes a complicated large number processing operation common to several different encryption processing methods.

47. A method according to claim 45 wherein the first plurality of large number processing operations includes a plurality of large number processing operation each common to several different encryption processing methods.

48. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device a design for an integrated circuit is provided, comprising: a processor core comprising hardware for implementing a plurality of commands, each command addressable by an instruction, the plurality of commands including a first plurality of large number processing operations including an operation common to a plurality of encryption processing processes, and a second plurality of processing operations including an operation common to general purpose microprocessors; and,a program controller for retrieving of instruction data and for executing a series of instructions in response to the instruction data, the series of instructions for resulting in security processing, the instruction data reprogrammable for supporting different security processes and modifications to security processes.

49. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device a method of performing large number multiplications is provided, comprising: providing a control register, the control register for storing a value, the value associated with a size of a large number;providing a multiplicand program, the multiplicand program providing a process according to a predetermined standard, the process comprising at least a multiplication operation applied to a large number of a predetermined size, the predetermined size being determined at least in dependence of the value read from the control register by the multiplicand program.

50. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device according to the method of claim 49 further comprising: storing at least one of the large number and the result of the multiplication process in a process register, the process register being one of a plurality of process registers;accessing at least one of the control register and the at least one of the plurality of process registers as N-bit values, the N-bit value being determined in dependence upon the value stored within the control register.

51. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device according to the method of claim 49 further comprising: providing a processor, the processor for executing the multiplicand program, the processor performing the at least a multiplication operation according to predetermined size of an arithmetic logic unit of the processor.