FLEXIBLE DC CONVERTER FEATURING MULTI-PORT DC POWER FLOW CONTROL AND CONTROL METHOD THEREOF

Abstract

A flexible DC converter comprises a MMC and a DCPFC embedded within the flexible DC converter. The flexible DC converter features modularity and a flexible number of ports, enabling bidirectional control of DC power flow of two or more lines, addressing the issue of insufficient degrees of freedom in DC power flow control in meshed DC systems. The DCPFC is directly embedded in the flexible DC converter, allowing for energy balance without the need for external power sources and high-voltage isolation devices, with a wide range of power flow regulation. The control method can manage both internal and external energy balance of the device. Additionally, a main circuit parameter designing method can serve as a basis for selecting circuit components for the device. A fault protection strategy and an active fault current suppression method can enhance the reliability of the device under complex extreme conditions.

Description

BACKGROUND OF THE INVENTION

1. Technical Field

The disclosure relates to the technical field of Voltage Source Converter based High Voltage Direct Current (VSC-HVDC) transmission and distribution and power electronics, in particular to a Modular Multilevel Converter (MMC) featuring multi-port direct current (DC) power flow control for a high-voltage DC power transmission network and a control method thereof.

2. Description of Related Art

VSC-HVDC technology features independent controllability of active and reactive power, no need for reactive power compensation, the ability to supply power to passive networks, and consistent voltage polarity during power flow reversal. This enhances the flexibility of system operation control. The VSC-HVDC transmission and distribution system has evolved from the initial “point-to-point” structure with a single sending end and a single receiving end, to a multi-terminal flexible DC system structure with multiple power supplies and multiple power reception points. In the future, it is expected to develop into more complex ring-mesh topologies. The mesh flexible DC system can further enhance the flexibility of operation control, system redundancy, and power supply reliability, facilitating the integration of various types of wide-area power sources. This allows for efficient transmission and optimal distribution of electrical energy over large areas, meeting the current demand for large-scale development of new energy with multi-terminal grid connection, multiple power reception points, and wide-area interconnection. It can effectively alleviate voltage stability issues caused by new energy power fluctuations and frequency stability issues in large interconnected AC grids.

In DC systems with a mesh structure, multiple loops exist between some controllable nodes, which enhances the flexibility of configuration and control, as well as power supply reliability. However, when the number of transmission lines is greater than or equal to the number of controllable nodes, it becomes impossible to fully control the DC line power flow solely by using converter control. This can lead to issues such as transmission section congestion, line overloading, and excessive line losses.

BRIEF SUMMARY OF THE INVENTION

This section aims to outline certain aspects of the embodiments of the present disclosure and to briefly introduce some preferred embodiments. Simplifications or omissions may be made in this section and the abstract and title of the application to avoid obscuring the purpose of these elements. Such simplifications or omissions should not be interpreted as limiting the scope of the present disclosure.

In light of the aforementioned existing issues, the present disclosure is proposed.

Therefore, the disclosure provides a flexible DC converter featuring multi-port DC power flow control and a control method thereof, which can solve issues such as transmission section congestion, line overloading, and excessive line losses.

To solve the above technical problems, the disclosure provides the following technical scheme. A flexible DC converter featuring multi-port DC power flow control comprises:

• • a MMC; and
  • a DC power flow controller (DCPFC) embedded within the MMC.

As a preferable scheme of the flexible DC converter featuring multi-port DC power flow control provided by the disclosure, the DCPFC comprises two or more DC power flow control units, the number of the DC power flow control units is equal to the number of ports of the DCPFC, and each DC power flow control unit is capable of adjusting the DC power flow on a connected DC line.

As a preferable scheme of the flexible DC converter featuring multi-port DC power flow control provided by the disclosure, the DC power flow control unit consists of a three-phase star-connected submodule chain and an arm inductor, and a three-phase neutral point resulting from the connection of the submodule chain and the inductor serves as a DC power flow regulation port.

As a preferable scheme of the flexible DC converter featuring multi-port DC power flow control provided by the disclosure, the MMC is a medium- or high-voltage, three-phase voltage source converter with a modular multilevel structure, capable of AC-DC power conversion, facilitating the interconnection of medium- and high-voltage AC power grids with DC systems.

As a preferable scheme of the flexible DC converter featuring multi-port DC power flow control provided by the disclosure, the embedded DCPFC is symmetrically installed on both upper and lower arms of the MMC, or installed on either the upper arm or the lower arm of the MMC.

As a preferable scheme of the flexible DC converter featuring multi-port DC power flow control provided by the disclosure, the submodule chain is a unipolar submodule chain, a bipolar submodule chain, or a hybrid submodule chain comprising both unipolar and bipolar submodules.

The disclosure also provides the following technical scheme. A control method of the embedded multi-port DCPFC comprises DC power flow control loops on multiple lines, energy balance control loops between the MMC and the DCPFC, and internal energy balance control loops within the DCPFC, wherein

when the embedded multi-port DCPFC connects two or more DC lines, the sum of power on all output lines equals the total power of the MMC; if the embedded multi-port DCPFC connects a total of N DC output lines, it is possible to perform active control on the power flow of N−1 lines, while the DC power flow on the remaining line equals the total power flow minus the sum of the power flow on the other lines.

As a preferable scheme of the control method of the embedded multi-port DCPFC provided by the disclosure, for the DC power flow control loops on multiple lines,

• • a line power flow control loop calculates a difference between voltage reference values of other lines and a reference circuit voltage to determine DC components of voltages of each DC power flow control unit, and the mathematical equation is as follows:

$\{\begin{array}{c}{U}_{\mathrm{p1a},dc}=U_{o1}-U_d\\ ⋮\\ U_{\mathrm{pka},dc}=U_{\mathrm{ok}}-U_d\\ ⋮\\ U_{\mathrm{pNa},dc}=U_{oN}-U_d\end{array}$

where U_d is a rated voltage of a DC system, which is also equal to a reference line voltage; Up1a, U_pka and U_pNa are the DC components of the voltages of the DC power flow control units connected to the first line, the kth line, and the Nth line respectively; and U_ol, U_ok and U_oN are DC voltage reference values of the first line, the kth line, and the Nth line respectively.

As a preferable scheme of the control method of the embedded multi-port DCPFC provided by the disclosure, for the energy balance control loops between the MMC and the DCPFC,

• • by superimposing energy balancing control voltages on arms of the DC flow power control units and arms of the modular multilevel converter, AC coupled energy is formed to compensate for accumulated DC energy, and the mathematical equation for the overall input and output energy of the DCPFC is as follows:

$\{\begin{array}{c}{P}_{\mathrm{DCPFC}\_\mathrm{out}}=\sum _{i=1}^N\left(U_{\mathrm{pia},dc}-\frac{1}{N}\sum _{l=1}^N{U}_{\mathrm{pla},dc}\right)I_{oi}\\ P_{\mathrm{DCPFC}\_\mathrm{in}}=\sum _{j=a,b,c}{i}_{\mathrm{jp},ac}\left(\frac{1}{N}\sum _{i=1}^N{U}_{\mathrm{pij},ac}\right)+\left(\frac{1}{N}\sum _{i=1}^N{U}_{\mathrm{pia},dc}\right)I_d\end{array}$

where P_{DCPFC_out} is the total output energy of the multi-port DCPFC, P_{DCPFC_in} is the total input energy of the multi-port DCPFC, U_pia,dc and U_pia,ac are DC and AC components of a voltage of the DC power flow control unit connected to the i^th line respectively, I_oi is a DC current of the i^th line, Id is the sum of DC currents of all lines, and i_jp,ac is an AC component of an upper arm current in phase j of the MMC.

As a preferable scheme of the control method of the embedded multi-port DCPFC provided by the disclosure, for the internal energy balance control loops within the DCPFC,

• • the mathematical equation for the energy relationship within the DCPFC is as follows:

$\frac{\Delta p_1}{3}+\underset{\_}{\Delta p_{c1a}}=\dots =\frac{\Delta p_k}{3}+\underset{\_}{\Delta p_{\mathrm{cka}}}=\dots =\frac{\Delta p_N}{3}+\underset{\_}{\Delta p_{\mathrm{cNa}}},\sum _{i=1}^N\underset{\_}{\Delta p_{cia}}=0$

where Δp1, Δp_k and Δp_N are DC energy of the first, k^th and N^th DC power flow control units respectively, and Δp_c1a, Δp_cka and Δp_cNa are AC coupled energy of the first, k^th and N^th DC power flow control units respectively.

The disclosure also provides the following technical scheme. A main circuit parameter designing method for the embedded multi-port DCPFC comprises the design of the number of submodules of the DC power flow control unit and the MMC, the design of the capacitance of submodules of the DC power flow control unit and the MMC, the design of the arm inductance of the DCPFC, and the design of power devices of submodules of the DC power flow control unit and the MMC.

As a preferable scheme of the main circuit parameter designing method for the embedded multi-port DCPFC provided by the disclosure,

• • the DCPFC is installed asymmetrically, embedded at an end of the upper arm of the MMC; and
  • the DCPFC uses bipolar full-bridge submodules, and the MMC employs unipolar half-bridge submodules.

As a preferable scheme of the main circuit parameter designing method for the embedded multi-port DCPFC provided by the disclosure,

• • for the design of the number of submodules of the DC power flow control unit and the MMC,
  • the mathematical equation for selecting the number of submodules of the DCPFC is as follows:

$N_{\mathrm{PFC}}\ge \frac{\epsilon U_d}{2U_{\mathrm{CPFC}}}+\frac{1}{U_{\mathrm{CPFC}}}\sqrt{{\left(2\epsilon E\frac{\Delta P_{1,2}\cos \left(\phi -\delta \right)}{P}\right)}^2+{\left(\frac{\omega L_{\mathrm{PFC}}}{6E}·\frac{P}{\Delta P_{1,2}\cos \left(\phi -\delta \right)}\right)}^2}\ge \frac{\epsilon U_d}{2U_{\mathrm{CPFC}}}$

where N_PFC is the number of submodules in a submodule chain in the DCPFC, U_CPFC is a rated voltage of the submodules in the DCPFC, U_d is a rated voltage of a DC grid, ε is a ratio of a maximum regulating voltage of the DCPFC to the rated voltage of the DC grid, ΔP_1,2 is a maximum difference of DC power flow of two DC lines, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC; and

• • the mathematical equation for selecting the number of submodules of the MMC is as follows:

$\{\begin{array}{c}\begin{array}{c}{N}_{\mathrm{MMC}\_p}\ge \left[\frac{1}{2}-\frac{\epsilon \Delta P_{1,2}}{4P}\right]\frac{U_d}{U_C}+\\ \frac{1}{U_C}\sqrt{E^2+{\left[\epsilon \frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P}\right]}^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\end{array}\\ N_{\mathrm{MMC}\_n}\ge \left[\frac{1}{2}+\frac{\epsilon \Delta P_{1,2}}{4P}\right]\frac{U_d}{U_C}+\frac{1}{U_C}\sqrt{E^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\end{array}$

where N_MMC,p and N_MMC,n are the number of submodules of the upper arm and lower arm of the MMC respectively, U_C is a rated voltage of the submodules of the MMC, U_d is a rated voltage of a DC grid, ε is a ratio of a maximum regulating voltage of the DCPFC to the rated voltage of the DC grid, ΔP_1,2 is a maximum difference of DC power flow of two DC lines, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC.

As a preferable scheme of the main circuit parameter designing method for the embedded multi-port DCPFC provided by the disclosure,

• • for the design of the capacitance of submodules of the DC power flow control unit and the MMC,
  • the mathematical equation for selecting the capacitance value of submodules of the DCPFC is as follows:

$\{\begin{array}{c}{C}_{\mathrm{PFC}}\ge \frac{1}{r_1}·\frac{1}{N_{\mathrm{PFC}}{U}_{\mathrm{CPFC}}}\sqrt{{\epsilon }^2{\left[\frac{1.6}{11\omega \cos \left(\phi -\delta \right)}+\frac{2P\cos \left(\phi -\delta \right)}{11\omega }\right]}^2+{\left[\frac{L_{\mathrm{PFC}}{P}^2}{16E^2}\right]}^2}\\ C_{\mathrm{PFC}}\ge \frac{1}{r_2}·\frac{1}{N_{\mathrm{PFC}}{U}_{\mathrm{CPFC}}}\sqrt{{\left[\frac{L_{\mathrm{PFC}}{P}^2\left[2\cos \left(\phi -\delta \right)-1.8\right]}{259E^2\cos \left(\phi -\delta \right)}\right]}^2+{\epsilon }^2{\left[\frac{\left[2\cos \left(\phi -\delta \right)-1.8\right]P}{86\omega }\right]}^2}\end{array}$

where CPFC is the capacitance of the submodules of the DCPFC, NPFC is the number of submodules in a submodule chain in the DCPFC, UCPFC is a rated voltage of the submodules in the DCPFC, r₁ and r₂ are fundamental frequency and double frequency fluctuation rates of a submodule capacitor voltage respectively, ε is a ratio of a maximum regulating voltage of the DCPFC to a rated voltage of a DC grid, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC; and

• • the mathematical equation for selecting the capacitance value of modular multilevel submodules is as follows:

$\{\begin{array}{c}{C}_0\ge \frac{1}{{\epsilon }_1}·❘\frac{3P}{10\omega N_{\mathrm{MMC}}^2{U}_C^2\cos \left(\phi -\delta \right)}❘\\ C_0\ge \frac{1}{{\epsilon }_2}·❘\frac{P}{12\omega N_{\mathrm{MMC}}^2{U}_C^2\cos \left(\phi -\delta \right)}❘\end{array}$

where C₀ is the capacitance of the submodules of the MMC, N_MMC is the number of submodules in one arm of the MMC, U_C is a rated voltage of submodule capacitors of the MMC, ε₁ and ε₂ are fundamental frequency and double frequency fluctuation rates of a submodule capacitor voltage of the MMC respectively, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, and δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage.

As a preferable scheme of the main circuit parameter designing method for the embedded multi-port DCPFC provided by the disclosure, for the design of the arm inductance of the DCPFC,

• • the mathematical equation for selecting the arm inductance of the DCPFC
  • is as follows:

$\{\begin{array}{c}\mathrm{AC}\mathrm{negative}\mathrm{sequence}\mathrm{current}\mathrm{constraint}:\\ L_{\mathrm{PFC}}\ge \frac{2}{{\omega }_0}\sin \left(2\mathrm{arc}\sin \left(\frac{1.5\%}{\eta }\right)\right)-4L_T-2L_0\\ \mathrm{Internal}\mathrm{energy}\mathrm{balance}\mathrm{constraint}\mathrm{for}\mathrm{DC}\\ \mathrm{power}\mathrm{flow}\mathrm{control}\mathrm{device}:\\ L_{PFC}\le \frac{3N_{\mathrm{PFC}}{U}_{\mathrm{CPFC}}}{4I_d{\omega }_0}\\ \mathrm{Short}-\mathrm{circuit}\mathrm{fault}\mathrm{current}\mathrm{suppression}\mathrm{limit}:\\ L_{\mathrm{PFC}}\ge \frac{\left(2+\epsilon \right)U_d}{\lambda }-12L_{\mathrm{dc}}-4L_0\\ \mathrm{Resonant}\mathrm{frequency}\mathrm{limit}\mathrm{for}\mathrm{phase}\mathrm{unit}:\\ {\omega }_{\mathrm{res}}=\sqrt{\frac{N_{\mathrm{MMC}}^2+N_{\mathrm{PFC}}^2}{\left(4L_0+L_{\mathrm{PFC}}\right)\left(N_{\mathrm{MMC}}+N_{\mathrm{PFC}}\right)C_0}}\approx {\omega }_0\end{array}$

where L_PFC is the arm inductance of the DCPFC, ω₀ is angular frequency at the fundamental frequency, ω_res is resonant angular frequency of the series resonance formed between the submodule chain and arm inductance within a phase unit of an integrated system of the DCPFC and the MMC, L_T is an inductance value of a connected transformer, L₀ is an arm inductance value of the MMC, L_dc is an inductance value of a smoothing reactor of a DC system, N_PFC is the number of submodules in a submodule chain of the DCPFC, U_CPFC is a rated voltage of submodules in the DCPFC, U_d is a rated voltage of a DC grid, I_d is a rated current of the DC grid, ε is a ratio of a maximum regulating voltage of the DCPFC to the rated voltage of the DC grid, λ is an upper limit of a transient current change rate under short-circuit faults, η is a per-unit value of a negative sequence current amplitude, C₀ is the capacitance of submodules of the MMC, and N_MMC is the number of submodules in one arm of the MMC.

As a preferable scheme of the main circuit parameter designing method for the embedded multi-port DCPFC provided by the disclosure,

• • for the design of power devices of submodules of the DC power flow control unit and the MMC,
  • the mathematical equation for calculating the voltage and current stresses of the power devices of the DC power flow control unit is as follows:

$\{\text{⁠}\begin{array}{c}{A}_{\mathrm{PFC}\_U}=\frac{\epsilon U_d}{4N_{\mathrm{PFC}}}+\frac{1}{2U_d{N}_{\mathrm{PFC}}}\sqrt{{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P}\right)}^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{3}\right)}^2}\\ A_{\mathrm{PFC}\_\mathrm{Ures}}=\frac{\epsilon U_d}{4N_{\mathrm{PFC}}}+\frac{1}{4U_d{N}_{\mathrm{PFC}}}\sqrt{2{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P}\right)}^2+2{\left(\frac{\omega L_{\mathrm{PFC}}P}{3}\right)}^2}\end{array}$ $\{\begin{array}{c}{A}_{\mathrm{PFC}\_I}=\frac{\max \left\{P_1,P_2\right\}}{3U_d}+P\sqrt{{\left(\frac{1}{6E\cos \left(\phi -\delta \right)}\right)}^2+{\left(\frac{1}{3U_d}\right)}^2}\\ A_{\mathrm{PFC}\_\mathrm{Ires}}=\frac{\max \left\{P_1,P_2\right\}}{3U_d}+\frac{P\sqrt{2{\left(\frac{1}{6E\cos \left(\phi -\delta \right)}\right)}^2+2{\left(\frac{1}{3U_d}\right)}^2}}{2}\end{array}$

where A_{PFC_U} and A_{PFC_Ures} are peak and effective values of a maximum voltage withstood by a single power electronic device in an arm submodule of the DCPFC respectively, A_{PFC_I} and A_{PFC_Ires} are peak and effective values of a maximum current withstood by a single power electronic device in the arm submodule of the DCPFC respectively, P₁ and P₂ are the DC power flow of two DC lines, ΔP_1,2 is a maximum difference between the DC power flow of the two DC lines, ε is a ratio of a maximum regulating voltage of the DCPFC to a rated voltage of a DC grid, U_d is the rated voltage of the DC grid, N_PFC is the number of submodules in a submodule chain of the DCPFC, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC; and

• • the mathematical equation for calculating the voltage and current stresses of the power devices of the MMC is as follows:

$\{\begin{array}{c}{A}_{\mathrm{MMC}\_U}=\frac{1}{2N_{\mathrm{MMC}}}\left\{\begin{array}{c}\left[\frac{1}{2}+\frac{\Delta P_{1,2}}{2{\mathrm{EU}}_d\cos \left(\phi -\delta \right)}\right]U_d+\\ \sqrt{E^2+{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P{U}_d}\right)}^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\end{array}\right\}\\ A_{\mathrm{MMC}\_\mathrm{Ures}}=\frac{1}{2N_{\mathrm{MMC}}}\left\{\frac{\begin{array}{c}\left[\frac{1}{2}+\frac{\Delta P_{1,2}}{2{\mathrm{EU}}_d\cos \left(\phi -\delta \right)}\right]U_d+\\ \sqrt{2E^2+2{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P{U}_d}\right)}^2+2{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\end{array}}{2}\right\}\end{array}$ $\{\begin{array}{c}{A}_{\mathrm{MMC}\_I}=\frac{P}{3U_d}+\frac{P}{3E\cos \left(\phi -\delta \right)}\\ A_{\mathrm{MMC}\_\mathrm{Ires}}=\frac{P}{3U_d}+\frac{\sqrt{2}P}{6E\cos \left(\phi -\delta \right)}\end{array}$

where A_{MMC_U} and A_{MMC_Ures} are peak and effective values of a maximum voltage withstood by a single power electronic device in an arm submodule of the MMC respectively, A_{MMC_I} and A_{MMC_Ires} are peak and effective values of a maximum current withstood by a single power electronic device in the arm submodule of the MMC respectively, ΔP_1,2 is a maximum difference between the DC power flow of two DC lines, U_d is a rated voltage of a DC grid, N_MMC is the number of submodules in one arm of the MMC, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC.

The disclosure also provides the following technical scheme. A protection method for the embedded multi-port DCPFC under DC short-circuit faults comprises the protection of the DCPFC under DC short-circuit faults, and the active restriction of fault currents under DC short-circuit faults.

As a preferable scheme of the protection method for the embedded multi-port DCPFC under DC short-circuit faults provided by the disclosure,

• • the protection of the DCPFC under DC short-circuit faults comprises:
  • controlling the submodules within the DCPFC to operate in a specific switching state, or installing a protection device on the submodules within the DCPFC;
  • the specific switching state of the submodule refers to the condition where a submodule capacitor is bypassed and currents flow solely through a switching device, and the protection device consists of a load shedding circuit or a thyristor bypass switch; and
  • the switching device of the submodule withstands fault currents, and by operating the submodule in the specific switching state, the fault currents are prevented from flowing into the submodule capacitor, thus achieving fault protection.

As a preferable scheme of the protection method for the embedded multi-port DCPFC under DC short-circuit faults provided by the disclosure,

• • the protection device is a load shedding circuit connected in parallel with the submodule capacitor,
  • the load shedding circuit is formed by a combination of diodes, resistors, and switching devices in series and parallel, which dissipates the energy of the fault currents to prevent overvoltage across the submodule capacitor, thereby achieving fault protection.

As a preferable scheme of the protection method for the embedded multi-port DCPFC under DC short-circuit faults provided by the disclosure,

• • the protection device is a distributed or centralized thyristor bypass switch, the thyristor bypass switch consists of anti-parallel thyristors, a resistor-capacitor circuit, and static resistors connected in parallel, the distributed thyristor bypass switches are installed within each submodule, and the centralized thyristor bypass switches are connected in parallel with the submodule chains; and the submodules are bypassed through the fast action of the bidirectional thyristors, preventing the fault currents from flowing through the submodules, thus achieving fault protection.

As a preferable scheme of the protection method for the embedded multi-port DCPFC under DC short-circuit faults provided by the disclosure,

• • the active restriction of fault currents under DC short-circuit faults comprises:
  • controlling the submodules within the DCPFC to operate in a specific switching state, or installing a protection device on the submodules within the DCPFC;
  • the specific switching state of the submodule refers to the condition where the submodule is locked or positively engaged, the protection device consists of a load shedding circuit and a fault current limiter, the load shedding circuit is formed by a combination of diodes, resistors, and switching devices arranged in series and parallel, and the fault current limiter is formed by a combination of resistors, inductors, and surge arresters arranged in series and parallel; and
  • the submodule capacitor withstands a certain fault voltage, the switching device of the submodule endures the fault currents, and by operating the submodule in a specific switching state, the submodule is integrated into the circuit with a negative voltage, effectively suppressing the fault currents.

As a preferable scheme of the protection method for the embedded multi-port DCPFC under DC short-circuit faults provided by the disclosure,

• • the protection device is a load shedding circuit connected in parallel with the submodule capacitor, enabling active suppression of step-down fault currents; the protection device is a distributed or centralized fault current limiter, which is composed of thyristor bypass switches, resistors, inductors, and surge arresters connected in series, the distributed fault current limiters are installed within each submodule, and the centralized fault current limiters are connected in parallel with the submodule chains; and by means of the fault current limiter, the rise of fault currents is restricted, assisting a DC grid in suppressing and clearing faults.

Compared with existing flexible interconnection devices, the disclosure has the following beneficial effects.

1. The existing self-balancing series voltage regulation type DCPFC has a relatively complex control system, with limited power flow regulation capability and control flexibility. The external balancing DCPFC currently in use must withstand system-level voltages and insulation, which increases the cost and construction difficulty of the device. In contrast, the proposed multi-port DCPFC, embedded in the MMC, achieves energy balance through coordinated control with the main MMC, eliminating the need for external power sources and isolation transformers. Additionally, the arm of the device is composed of submodules, offering advantages such as modularity, multi-port capability, easy expansion, broad adjustment range, strong regulation ability, suitability for high-voltage systems, and bidirectional controllable power flow.

2. The multi-port DCPFC in this disclosure features a modular design, allowing for rapid and cost-effective expansion of output ports by adjusting the number of DC power flow control units.

3. The main circuit parameter designing method for the DCPFC and the MMC takes into account the impact of embedding the DCPFC on the MMC, providing a fast, effective, and reliable parameter calculation method and selection basis.

4. The protection method for the embedded multi-port DCPFC under DC short-circuit faults not only ensures the safe and stable operation of the DCPFC under extreme DC fault conditions but also effectively suppresses fault currents, assisting a DC grid in suppressing and clearing faults.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solution in the embodiments of the present disclosure more clearly, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can be obtained according to these drawings without paying creative labor.

FIG. 1 is a schematic diagram of a topological structure of an embedded multi-port DCPFC and a MMC in which the multi-port DCPFC is embedded according to the disclosure;

FIG. 2 is a schematic diagram of a topological structure of an embedded multi-port DCPFC and a MMC in which the multi-port DCPFC is embedded according to the disclosure;

FIG. 3 illustrates a topological diagram of a DC power flow control unit within an embedded multi-port DCPFC, as well as a typical topology example of a unipolar submodule and a bipolar submodule within the embedded multi-port DCPFC according to the disclosure;

FIG. 4 is a typical application scenario diagram of an embedded multi-port DCPFC according to the disclosure;

FIG. 5 is a schematic diagram of a protection method and device for an embedded multi-port DCPFC under DC short-circuit faults according to the disclosure;

FIG. 6 is a schematic diagram of a topological structure of an embedded multi-port DCPFC and a MMC in which the multi-port DCPFC is embedded according to Embodiment 1;

FIG. 7 is a block diagram of a control method of an embedded multi-port DCPFC and a MMC according to Embodiment 1;

FIG. 8 presents simulation waveform graphs for two operating conditions and four stages in Embodiment 1, including the voltage and current waveform graphs of each port, the voltage difference waveform graphs between ports, and the internal submodule capacitor voltage waveform graphs of the MMC and the DCPFC;

FIG. 9 is a schematic diagram of a DC short-circuit fault in Embodiment 2;

FIG. 10 illustrates waveform graphs of submodule capacitor voltages and fault currents of a DCPFC after incorporating a fault protection strategy during a fault in Embodiment 2; and

FIG. 11 illustrates waveform graphs of fault currents and submodule capacitor voltages of a DCPFC after incorporating an active current limitation strategy during a fault in Embodiment 2.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make the purposes, features and advantages of the disclosure clearer, the embodiments of the disclosure will be described in more detail below in combination with attached drawings. Obviously, the described embodiments are only part of the embodiments of the disclosure, not all of them. Based on the embodiments of the disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative labor shall belong to the scope of protection of the disclosure.

In the following description, specific details are set forth in order to fully understand the disclosure. However, the disclosure can be implemented in many other ways different from those described here, and those skilled in the art can make similar extension without violating the connotation of the disclosure. Therefore, the disclosure is not limited by the specific embodiments disclosed below.

Further, “one embodiment” or “embodiment” here refers to a specific feature, structure or characteristic which can be included in at least one implementation of the disclosure. The appearances of “in one embodiment” in different places of this specification do not all refer to the same embodiment, nor are they separate or selective embodiments mutually exclusive of other embodiments.

The present disclosure will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present disclosure in detail, for the sake of clarity, the cross-sectional view representing the device structure is partially enlarged not to scale, and the said schematic diagram is merely illustrative and should not limit the scope of protection of the present disclosure herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

In the description of the disclosure, it should be noted that directional or positional relationships indicated by the terms such as “upper”, “lower”, “inner” and “outer” are based on the directional or positional relationships shown in the drawings, which are only for the convenience of describing the disclosure and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation or be constructed and operated in a specific orientation, so they cannot be understood as limiting the disclosure. In addition, the terms “first”, “second” and “third” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

In the description of the disclosure, the terms “install” and “connect” should be understood in a broad sense unless otherwise specified and defined. For example, it may be fixed connection, detachable connection or integrated connection; it may be mechanical connection or electric connection; and it may be direct connection, indirect connection through intermediate media, or internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the disclosure may be understood according to specific situations.

Embodiment 1

Referring to FIGS. 1-6, a first embodiment of the disclosure provides a flexible DC converter featuring multi-port DC power flow control and a control method thereof. The flexible DC converter comprises:

• • a MMC; and
  • a DCPFC embedded within the MMC.

Further, the DCPFC comprises two or more DC power flow control units, the number of the DC power flow control units is equal to the number of ports of the DCPFC, and each DC power flow control unit is capable of adjusting the DC power flow on a connected DC line;

• • the DC power flow control unit consists of a three-phase star-connected submodule chain and an arm inductor, and a three-phase neutral point resulting from the connection of the submodule chain and the inductor serves as a DC power flow regulation port; and
  • the MMC is a medium- or high-voltage, three-phase voltage source converter with a modular multilevel structure, capable of AC-DC power conversion, facilitating the interconnection of medium- and high-voltage AC power grids with DC systems.

Further, the MMC is a modular multilevel converter with medium to high voltage rating.

Further, as shown in FIGS. 1 and 2, the embedded DCPFC is symmetrically installed on both upper and lower arms of the MMC, or installed on either the upper arm or the lower arm of the MMC.

Further, as shown in FIG. 3, the submodule chain is a unipolar submodule chain, a bipolar submodule chain, or a hybrid submodule chain comprising both unipolar and bipolar submodules.

The disclosure also provides a control method of the embedded multi-port DCPFC, which comprises DC power flow control loops on multiple lines, energy balance control loops between the MMC and the DCPFC, and internal energy balance control loops within the DCPFC, wherein

• • when the embedded multi-port DCPFC connects two or more DC lines, the sum of power on all output lines equals the total power of the MMC; if the embedded multi-port DCPFC connects a total of N DC output lines, it is possible to perform active control on the power flow of N−1 lines, while the DC power flow on the remaining line equals the total power flow minus the sum of the power flow on the other lines.

Further, the control objective of the line power flow control loop is to ensure that the DC voltage of N output lines equals a reference value.

It should be noted that N represents the total number of lines connected to the embedded multi-port DCPFC. The line power flow control loop first selects a line with the relatively lowest voltage as a reference line based on output line voltage reference values provided by an external system.

Additionally, the DC component of the voltage in the internal submodule chain of the DC power flow control unit connected to the reference line is set to zero. The line power flow control loop calculates a difference between voltage reference values of other lines and a reference circuit voltage to determine DC components of voltages of each DC power flow control unit, and the mathematical equation is as follows:

$\{\begin{array}{c}{U}_{p1a,\mathrm{dc}}=U_{o1}-U_d\\ U_{pka,dc}=U_{ok}-U_d\\ U_{\mathrm{pNa},\mathrm{dc}}=U_{\mathrm{oN}}-U_d\end{array}$

where U_d is a rated voltage of a DC system, which is also equal to a reference line voltage; U_p1a, U_pka and U_pNa are the DC components of the voltages of the DC power flow control units connected to the first line, the k^th line, and the N^th line respectively; and U_ol, U_ok and U_oN are DC voltage reference values of the first line, the k^th line, and the N^th line respectively.

Further, the control objective of the energy balance control loop between the MMC and the DCPFC is to maintain an average voltage of all submodule capacitors within the DCPFC at a reference value.

It should be noted that during the process of controlling DC power flow, the DCPFC interacts with a DC system, leading to the exchange of DC energy. The accumulation of DC energy causes the voltage of the internal submodule capacitors in the DCPFC to lose stability. The energy balance control loops between the MMC and the DCPFC superimpose energy balancing control voltages on arms of the DC flow power control units and arms of the modular multilevel converter, thus forming AC coupled energy. The mathematical equation for the overall input and output energy of the DCPFC is as follows:

$\{\begin{array}{c}{P}_{\mathrm{DCPFC}\_\mathrm{out}}=\sum _{i=1}^N\left(U_{pia,dc}-\frac{1}{N}\sum _{l=1}^N{U}_{\mathrm{pla},\mathrm{dc}}\right)I_{oi}\\ P_{\mathrm{DCPFC}\_\mathrm{in}}=\sum _{j=a,b,c}{i}_{\mathrm{jp},ac}\left(\frac{1}{N}\sum _{i=1}^N{U}_{\mathrm{pij},\mathrm{ac}}\right)+\left(\frac{1}{N}\sum _{i=1}^N{U}_{\mathrm{pia},\mathrm{dc}}\right)I_d\end{array}$

where P_{DCPFC_out} is the total output energy of the multi-port DCPFC, P_{DCPFC_in} is the total input energy of the multi-port DCPFC, U_pia,dc and U_pia,ac are DC and AC components of a voltage of the DC power flow control unit connected to the i^th line respectively, I_oi is a DC current of the i^th line, I_d is the sum of DC currents of all lines, and i_jp,ac is an AC component of an upper arm current in phase j of the MMC.

Further, to ensure the stable operation of the DCPFC, the output power of a power flow regulation port of the DCPFC must balance with the input power of an energy balance port, as described by the following mathematical equation.

P_{DCPFC_out}=P_{DCPFC_in}

It should be noted that a proportional-integral controller is used to control the amplitude and phase angle of the energy balance control voltage of the DCPFC and the MMC. The input is the difference between the average voltage of all submodules within the DCPFC and a reference value, and the output is reference values of the amplitude and phase angle of the energy balance control voltage.

Further, to ensure that the phase angle of the energy balance control voltage always equals the phase angle of the arm current of the MMC, it is sufficient to control the magnitude of the energy balance control voltage, ensuring that the magnitudes of the three-phase energy balance control voltages are equal. The equation for the proportional-integral controller is as follows:

$U_{\mathrm{PFC},\mathrm{ac}}^{*}=k_p\left(U_c^{*}-\frac{1}{N}\sum _{i=1,2,\dots ,N}{U}_{C,i}\right)+\int k_i\left(U_c^{*}-\frac{1}{N}\sum _{i=1,2,\dots ,N}{U}_{C,i}\right)\mathrm{dt}$

where k_p is the gain coefficient of the proportional part of the proportional-integral controller, k_i is the gain coefficient of the integral part of the proportional-integral controller, U_C* is the reference value of the voltage of the internal submodule capacitors in the DC power flow control units, U_C,i is the average voltage of the internal submodule capacitors in the k^th DC power flow control unit, and U_PFC* is the reference value of the magnitude of the energy balance control voltage between the DCPFC and the MMC. N denotes the total number of lines connected to the embedded multi-port DCPFC.

Further, the control objective of the internal energy balance control loop of the DCPFC is to maintain consistent internal submodule capacitor voltages of each DC power flow control unit.

It should be noted that the line power flow control loop results in differing DC voltages for the DC power flow control units, creating DC energy deviation that lead to inconsistencies in internal submodule capacitor voltages of each DC power flow control unit. Therefore, the internal energy balance control loop of the DCPFC actively injects AC circulating currents between the DC power flow control units, using AC coupled energy to compensate for the DC energy deviation and maintain stable submodule voltages and energy balance. The calculation formula for the DC energy of each DC power flow control unit is as follows:

$\Delta p_k=\left(U_{\mathrm{pka},\mathrm{dc}}-\underset{\_}{\frac{1}{N}\sum _{i=1}^N{U}_{\mathrm{pia},\mathrm{dc}}}\right)I_{ok},k=1,2\dots N$

where Δp_k is the DC energy of the k^th DC power flow control unit, U_pka,dc and U_pia,dc are DC components of voltages of the DC power flow control units connected to the k^th and i^th lines respectively, I_ok is the DC current of the k^th line, and N denotes the total number of lines connected to the embedded multi-port DCPFC.

Further, each DC power flow control unit injects AC voltages under the control of the internal energy balance control loop of the DCPFC, and the mathematical equation is as follows:

$\Delta u_{cka}=x_k\sin \left(\omega t-{\beta }_k\right),k=1,2\dots N$

where Δu_cka is the positive sequence circulating voltage additionally superimposed in the a-phase modulation voltage of the k^th DC power flow control unit, x_i and β_i are the amplitude and phase angle of the fundamental frequency positive sequence circulating voltage respectively, and ω is angular frequency.

It should be noted that the actively injected AC voltage causes AC coupled energy to be generated inside the DCPFC, and the mathematical equation of the average value of the AC coupled energy in the fundamental frequency period is as follows:

$\stackrel{\_}{\Delta p_{cka}}=\stackrel{\_}{\Delta i_{cka}{u}_{pka,ac}}=\frac{U_{\mathrm{PFC},\mathrm{ac}}}{\omega {\mathrm{NL}}_{\mathrm{PFC}}}\left[\text{⁠}\left(N-1\right)x_k\cos \left({\delta }_{\mathrm{PFC}}+\frac{\pi }{2}-{\beta }_k\right)-\sum _{\underset{i\ne k}{i=1}}^N{x}_i\cos \left({\delta }_{\mathrm{PFC}}+\frac{\pi }{2}-{\beta }_i\right)\right],k=1,2\dots N$

where Δp_cka is the AC coupled energy of the k^th DC power flow control unit, L_PFC is the arm inductance value in the DC power flow control unit, U_PFC,ac and δ_PFC are the amplitude and phase angle of the energy balance control voltage between the MMC and the DCPFC respectively, x_k and x_i are the circulating voltage amplitude of the k^th and i^th DC power flow control units respectively, and β_k and β_i are the circulating voltage phase angles of the k^th and i^th DC power flow control units respectively.

Further, to realize the energy balance between the DC power flow control units, the internal energy balance control loop of the DCPFC compensates the DC energy deviation with the AC coupled energy by controlling the amplitude and phase angle of circulating voltage, that is, the sum of AC coupled energy and DC energy deviation is zero. Additionally, the sum of AC coupled energy of all the DC power flow control units is also zero. The mathematical equation for the energy relationship within the DCPFC is as follows:

$\frac{\Delta p_1}{3}+\underset{\_}{\Delta p_{c1a}}=\cdots =\frac{\Delta p_k}{3}+\underset{\_}{\Delta p_{cka}}=\cdots =\frac{\Delta p_N}{3}+\underset{\_}{\Delta p_{\mathrm{cNa}}},\sum _{i=1}^N\underset{\_}{\Delta p_{cia}}=0$

where Δp₁, Δp_k and Δp_N are DC energy of the first, k^th and N^th DC power flow control units respectively, and Δp_c1a, Δp_cka and Δp_cNa are AC coupled energy of the first, k^th and N^th DC power flow control units respectively.

It should be noted that a proportional-integral controller is used to control the amplitude and phase angle of circulating voltage of the DC power flow control units. The input is the difference between the internal submodule voltage of each DC power flow control unit and the average value of submodule voltages of all the DC power flow control units, and the output is reference values of the amplitude and phase angle of circulating voltage of the corresponding DC power flow control unit.

Further, if the reference values of circulating voltage phase angles of all the DC power flow control units are equal and only the amplitude of circulating voltage is controlled, the equation of the proportional-integral controller is as follows:

$x_k^{*}=k_p\left(U_{C,k}-\frac{1}{N}\sum _{i=1,2,\dots ,N}{U}_{C,i}\right)+\int k_i\left(U_{C,k}-\frac{1}{N}\sum _{i=1,2,\dots ,N}{U}_{C,i}\right)\mathrm{dt}$

where k_p is the gain coefficient of the proportional part of the proportional-integral controller, k_i is the gain coefficient of the integral part of the proportional-integral controller, U_C,k and U_C,i are the average voltages of the internal submodule capacitors in the k^th and i^th DC power flow control units respectively, x_k is the reference value of the circulating voltage amplitude of the k^th DC power flow control unit, and N denotes the total number of lines connected to the embedded multi-port DCPFC.

The disclosure also provides a main circuit parameter designing method for the embedded multi-port DCPFC, which comprises the design of the number of submodules of the DC power flow control unit and the MMC, the design of the capacitance of submodules of the DC power flow control unit and the MMC, the design of the arm inductance of the DCPFC, and the design of power devices of submodules of the DC power flow control unit and the MMC.

It should be noted that the DCPFC is installed asymmetrically, embedded at an end of the upper arm of the MMC.

It should also be noted that the DCPFC uses bipolar full-bridge submodules, and the MMC employs unipolar half-bridge submodules.

It should also be noted that the multi-port DCPFC is connected with two DC lines.

Further, the objective of the design of the number of submodules of the DC power flow control unit and the MMC is to select an appropriate number of submodules for the DCPFC and the arms of the MMC, so as to avoid the problems of over-modulation and insufficient DC power flow control range. When the external parameters of the system are determined, according to the designing method for the number of submodules of the DC power flow control unit, the lower limit of the number of submodules of the DC power flow control unit and the lower limit of the number of submodules of the MMC can be quickly calculated.

The mathematical equation for selecting the number of submodules of the DCPFC is as follows:

$N_{\mathrm{PFC}}\ge \frac{\epsilon U_d}{2U_{\mathrm{CPFC}}}+\frac{1}{U_{\mathrm{CPFC}}}\sqrt{{\left(2\epsilon E\frac{\Delta P_{1,2}\cos \left(\phi -\delta \right)}{P}\right)}^2+{\left(\frac{\omega L_{\mathrm{PFC}}}{6E}·\frac{P}{\Delta P_{1,2}\cos \left(\phi -\delta \right)}\right)}^2}\ge \frac{\epsilon U_d}{2U_{\mathrm{CPFC}}}$

where N_PFC is the number of submodules in a submodule chain in the DCPFC, U_CPFC is a rated voltage of the submodules in the DCPFC, U_d is a rated voltage of a DC grid, ε is a ratio of a maximum regulating voltage of the DCPFC to the rated voltage of the DC grid, ΔP_1,2 is a maximum difference of DC power flow of two DC lines, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC; and

• • the mathematical equation for selecting the number of submodules of the MMC is as follows:

$\{\begin{array}{c}{N}_{\mathrm{MMC}\_p}\ge \left[\frac{1}{2}-\frac{\epsilon \Delta P_{1,2}}{4P}\right]\frac{U_d}{U_C}+\frac{1}{U_C}\sqrt{E^2+{\left[\epsilon \frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P}\right]}^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\\ N_{\mathrm{MMC}\_n}\ge \left[\frac{1}{2}+\frac{\epsilon \Delta P_{1,2}}{4P}\right]\frac{U_d}{U_C}+\frac{1}{U_C}\sqrt{E^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\end{array}$

where N_MMC,p and N_MMC,n are the number of submodules of the upper arm and lower arm of the MMC respectively, U_C is a rated voltage of the submodules of the MMC, U_d is a rated voltage of a DC grid, ε is a ratio of a maximum regulating voltage of the DCPFC to the rated voltage of the DC grid, ΔP_1,2 is a maximum difference of DC power flow of two DC lines, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC.

Further, the objective of the design of the capacitance of submodules of the DC power flow control unit and the MMC is to select appropriate submodule capacitance for the DCPFC and the arms of the MMC, so as to control the voltage ripple in a reasonable range. Due to the influence of the DC power flow control unit on the MMC, the capacitance parameter designing method is different from that of traditional MMCs. When the external parameters of the system are determined, according to the designing method for the capacitance of submodules of the DC power flow control unit, the lower limit of the capacitance value of submodules of the DC power flow control unit and the lower limit of the capacitance value of submodules of the MMC can be quickly calculated.

The mathematical equation for selecting the capacitance value of submodules of the DCPFC is as follows:

$\{\begin{array}{c}{C}_{\mathrm{PFC}}\ge \frac{1}{r_1}·\frac{1}{N_{\mathrm{PFC}}{U}_{\mathrm{CPFC}}}\sqrt{{{\epsilon }^2\left[\frac{1.6}{11\omega \cos \left(\phi -\delta \right)}+\frac{2P\cos \left(\phi -\delta \right)}{11\omega }\right]}^2+{\left[\frac{L_{\mathrm{PFC}}{P}^2}{16E^2}\right]}^2}\\ C_{\mathrm{PFC}}\ge \frac{1}{r_2}·\frac{1}{N_{\mathrm{PFC}}{U}_{\mathrm{CPFC}}}\sqrt{{\left[\frac{L_{\mathrm{PFC}}{P}^2\left[2\cos \left(\phi -\delta \right)-1.8\right]}{259E^2\cos \left(\phi -\delta \right)}\right]}^2+{{\epsilon }^2\left[\frac{\left[2\cos \left(\phi -\delta \right)-1.8\right]P}{86\omega }\right]}^2}\end{array}$

where CPFC is the capacitance of the submodules of the DCPFC, N_PFC is the number of submodules in a submodule chain in the DCPFC, U_CPFC is a rated voltage of the submodules in the DCPFC, r₁ and r₂ are fundamental frequency and double frequency fluctuation rates of a submodule capacitor voltage respectively, ε is a ratio of a maximum regulating voltage of the DCPFC to a rated voltage of a DC grid, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC; and

• • the mathematical equation for selecting the capacitance value of modular multilevel submodules is as follows:

$\{\begin{array}{c}{C}_0\ge \frac{1}{{\epsilon }_1}·❘\frac{3P}{10\omega N_{\mathrm{MMC}}^2{U}_C^2\cos \left(\phi -\delta \right)}❘\\ C_0\ge \frac{1}{{\epsilon }_2}·❘\frac{P}{12\omega N_{\mathrm{MMC}}^2{U}_C^2\cos \left(\phi -\delta \right)}❘\end{array}$

where C₀ is the capacitance of the submodules of the MMC, N_MMC is the number of submodules in one arm of the MMC, U_C is a rated voltage of submodule capacitors of the MMC, ε₁ and ε₂ are fundamental frequency and double frequency fluctuation rates of a submodule capacitor voltage of the MMC respectively, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, and δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage.

Further, the objective of the design of the arm inductance of the DCPFC is to select an appropriate arm inductance value for the DCPFC, so as to meet the capacity requirements of power transmission, reduce negative sequence currents, suppress short-circuit fault currents, and form the resonant angular frequency of series resonance between submodule chains and arm inductance within phase units of appropriate size. When the external parameters of the system are determined, according to the designing method for the arm inductance of the DCPFC, the value range of the arm inductance of the DCPFC can be quickly calculated.

The mathematical equation for selecting the arm inductance of the DCPFC is as follows:

$\{\begin{array}{c}\mathrm{AC}\mathrm{negative}\mathrm{sequence}\mathrm{current}\mathrm{constraint}:\\ L_{\mathrm{PFC}}\ge \frac{2}{{\omega }_0}\sin \left(2\mathrm{arc}\sin \left(\frac{1.5\%}{\eta }\right)\right)-4L_T-2L_0\\ \mathrm{Internal}\mathrm{energy}\mathrm{balance}\mathrm{constraint}\mathrm{for}\mathrm{DCPFC}\mathrm{device}:\\ L_{\mathrm{PFC}}\le \frac{3N_{\mathrm{PFC}}{U}_{\mathrm{CPFC}}}{4I_d{\omega }_0}\\ \mathrm{Short}-\mathrm{circuit}\mathrm{fault}\mathrm{current}\mathrm{suppression}\mathrm{limit}:\\ L_{\mathrm{PFC}}\ge \frac{\left(2+\epsilon \right)U_d}{\lambda }-12L_{dc}-4L_0\\ \mathrm{Resonant}\mathrm{frequency}\mathrm{limit}\mathrm{for}\mathrm{phase}\mathrm{unit}:\\ {\omega }_{\mathrm{res}}=\sqrt{\frac{N_{\mathrm{MMC}}^2+N_{\mathrm{PFC}}^2}{\left(4L_0+L_{\mathrm{PFC}}\right)\left(N_{\mathrm{MMC}}+N_{\mathrm{PFC}}\right)C_0}}\approx {\omega }_0\end{array}$

where L_PFC is the arm inductance of the DCPFC, ω₀ is angular frequency at the fundamental frequency, ω_res is resonant angular frequency of the series resonance formed between the submodule chain and arm inductance within a phase unit of an integrated system of the DCPFC and the MMC, L_T is an inductance value of a connected transformer, L₀ is an arm inductance value of the MMC, L_dc is an inductance value of a smoothing reactor of a DC system, N_PFC is the number of submodules in a submodule chain of the DCPFC, U_CPFC is a rated voltage of submodules in the DCPFC, U_d is a rated voltage of a DC grid, I_d is a rated current of the DC grid, ε is a ratio of a maximum regulating voltage of the DCPFC to the rated voltage of the DC grid, λ is an upper limit of a transient current change rate under short-circuit faults, η is a per-unit value of a negative sequence current amplitude, C₀ is the capacitance of submodules of the MMC, and N_MMC is the number of submodules in one arm of the MMC.

Further, the objective of the design of power devices of submodules of the DC power flow control unit and the MMC is to select appropriate power electronic devices for submodules of the DCPFC and the MMC. When the external parameters of the system are determined, according to the designing method for the power devices of submodules of the DC power flow control unit and the MMC, the voltage and current stresses of the power electronic devices can be determined.

The mathematical equation for calculating the voltage and current stresses of the power devices of the DC power flow control unit is as follows:

$\{\begin{array}{c}\begin{array}{c}{A}_{\mathrm{PFC}\_U}=\frac{\epsilon U_d}{4N_{\mathrm{PFC}}}+\\ \frac{1}{2U_d{N}_{\mathrm{PFC}}}\sqrt{{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P}\right)}^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{3}\right)}^2}\end{array}\\ \begin{array}{c}{A}_{\mathrm{PFC}\_\mathrm{Ures}}=\frac{\epsilon U_d}{4N_{\mathrm{PFcC}}}+\\ \frac{1}{4U_d{N}_{\mathrm{PFC}}}\sqrt{2{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{P}\right)}^2+2{\left(\frac{\omega L_{\mathrm{PFC}}P}{3}\right)}^2}\end{array}\end{array}$ $\{\begin{array}{c}{A}_{\mathrm{PFC}\_I}=\frac{\max \left\{P_1,P_2\right\}}{3U_d}+P\sqrt{{\left(\frac{1}{6E\cos \left(\phi -\delta \right)}\right)}^2+{\left(\frac{1}{3U_d}\right)}^2}\\ A_{\mathrm{PFC}\_\mathrm{Ires}}=\frac{\max \left\{P_1,P_2\right\}}{3U_d}+\frac{P\sqrt{2{\left(\frac{1}{6E\cos \left(\phi -\delta \right)}\right)}^2+2{\left(\frac{1}{3U_d}\right)}^2}}{2}\end{array}$

where A_{PFC_U} and A_{PFC_Ures} are peak and effective values of a maximum voltage withstood by a single power electronic device in an arm submodule of the DCPFC respectively, A_{PFC_I} and A_{PFC_Ires} are peak and effective values of a maximum current withstood by a single power electronic device in the arm submodule of the DCPFC respectively, P₁ and P₂ are the DC power flow of two DC lines, ΔP_1,2 is a maximum difference between the DC power flow of the two DC lines, ε is a ratio of a maximum regulating voltage of the DCPFC to a rated voltage of a DC grid, U_d is the rated voltage of the DC grid, N_PFC is the number of submodules in a submodule chain of the DCPFC, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC; and

It should be noted that the current and voltage stresses of the upper and lower arms of the MMC in which the DCPFC is embedded differ from those in traditional operating modes.

Further, the mathematical equation for calculating the voltage and current stresses of the power devices of the MMC is as follows:

$\{\begin{array}{c}{A}_{{\mathrm{MMC}}_U}=\frac{1}{2N_{\mathrm{MMC}}}\left\{\left[\frac{1}{2}+\frac{\Delta P_{1,2}}{2{\mathrm{EU}}_d\cos \left(\phi -\delta \right)}\right]U_d+\sqrt{E^2+{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{{\mathrm{PU}}_d}\right)}^2+{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}\right\}\\ A_{\mathrm{MMC}\_\mathrm{Ures}}=\frac{1}{2N_{\mathrm{MMC}}}\left\{\frac{\left[\frac{1}{2}+\frac{\Delta P_{1,2}}{2{\mathrm{EU}}_d\cos \left(\phi -\delta \right)}\right]U_d+\sqrt{E^2+2{\left(\frac{\Delta P_{1,2}E\cos \left(\phi -\delta \right)}{{\mathrm{PU}}_d}\right)}^2+2{\left(\frac{\omega L_{\mathrm{PFC}}P}{12E\cos \left(\phi -\delta \right)}\right)}^2}}{2}\right\}\end{array}$ $\{\begin{array}{c}{A}_{\mathrm{MMC}\_I}=\frac{P}{3U_d}+\frac{P}{3E\cos \left(\phi -\delta \right)}\\ A_{\mathrm{MMC}\_\mathrm{Ires}}=\frac{P}{3U_d}+\frac{\sqrt{2}P}{6E\cos \left(\phi -\delta \right)}\end{array}$

where A_{MMC_U} and A_{MMC_Ures} are peak and effective values of a maximum voltage withstood by a single power electronic device in an arm submodule of the MMC respectively, A_{MMC_I} and A_{MMC_Ires} are peak and effective values of a maximum current withstood by a single power electronic device in the arm submodule of the MMC respectively, ΔP_1,2 is a maximum difference between the DC power flow of two DC lines, U_d is a rated voltage of a DC grid, N_MMC is the number of submodules in one arm of the MMC, P is the total power of the MMC, φ is a phase angle of an AC current of the MMC, δ is a phase angle difference between a fundamental AC component of an arm voltage of the MMC and a grid voltage, E is an amplitude of the fundamental AC component of the arm voltage of the MMC, ω is angular frequency, and L_PFC is the arm inductance of the DCPFC.

The disclosure also provides a protection method for the embedded multi-port DCPFC under DC short-circuit faults, which comprises the protection of the DCPFC under DC short-circuit faults, and the active restriction of fault currents under DC short-circuit faults.

Further, the protection of the DCPFC under DC short-circuit faults comprises: controlling the submodules within the DCPFC to operate in a specific switching state, or installing a protection device on the submodules within the DCPFC.

Further, the specific switching state of the submodule refers to the condition where a submodule capacitor is bypassed and currents flow solely through a switching device, and the protection device consists of a load shedding circuit or a thyristor bypass switch; and

• • it should be noted that if the switching device of the submodule can withstand fault currents, by operating the submodule in the specific switching state, as shown in FIG. 5(a), the fault currents are prevented from flowing into the submodule capacitor, thus achieving fault protection.

It should be noted that the purpose of this method is to prevent damage to the DCPFC due to overvoltage on the submodule capacitors or overcurrent on the submodule switching devices during DC short-circuit faults.

Further, the protection device is a load shedding circuit connected in parallel with the submodule capacitor, as shown in FIG. 5(b), the load shedding circuit is formed by a combination of diodes, resistors, and switching devices in series and parallel, which dissipates the energy of the fault currents to prevent overvoltage across the submodule capacitor, thereby achieving fault protection.

It should be noted that the protection device is a distributed or centralized thyristor bypass switch, and the thyristor bypass switch consists of anti-parallel thyristors, a resistor-capacitor circuit, and static resistors connected in parallel; as shown in FIG. 5(c), the distributed thyristor bypass switches are installed within each submodule; as shown in FIG. 5(d), the centralized thyristor bypass switches are connected in parallel with the submodule chains; and the submodules are bypassed through the fast action of the bidirectional thyristors, preventing the fault currents from flowing through the submodules, thus achieving fault protection.

Further, the active restriction of fault currents under DC short-circuit faults of the DCPFC comprises: controlling the submodules within the DCPFC to operate in a specific switching state, or installing a protection device on the submodules within the DCPFC.

It should be noted that the specific switching state of the submodule refers to the condition where the submodule is locked or positively engaged, the protection device consists of a load shedding circuit and a fault current limiter, the load shedding circuit is formed by a combination of diodes, resistors, and switching devices arranged in series and parallel, and the fault current limiter is formed by a combination of resistors, inductors, and surge arresters arranged in series and parallel.

Further, if the submodule capacitor can withstand a certain fault voltage and the switching device of the submodule can endure the fault currents, by operating the submodule in a specific switching state, as shown in FIG. 5(e), the submodule is integrated into the circuit with a negative voltage, effectively suppressing the fault currents.

It should be noted that the purpose of this method is to utilize the DCPFC to assist a DC grid in suppressing and clearing faults.

It should be noted that the protection device is a load shedding circuit connected in parallel with the submodule capacitor, as shown in FIG. 5(f), enabling active suppression of step-down fault currents.

It should be noted that the protection device is a distributed or centralized fault current limiter, which is composed of thyristor bypass switches, resistors, inductors, and surge arresters connected in series; as shown in FIG. 5(g), the distributed fault current limiters are installed within each submodule; as shown in FIG. 5(h), the centralized fault current limiters are connected in parallel with the submodule chains; and by means of the fault current limiter, the rise of fault currents is restricted, assisting a DC grid in suppressing and clearing faults.

In Embodiment 1, the installation scene and the specific topology of a DCPFC are shown in FIGS. 4 and 6. The disclosure uses a multi-port DCPFC embedded in a MMC to realize the power flow control of three DC lines. The MMC is a MMC. The multi-port DCPFC is installed asymmetrically, embedded at an end of an upper arm of the MMC. The multi-port DCPFC comprises three DC power flow control modules, each DC power flow control module comprises three-phase star-connected arms, and each arm consists of a bipolar full-bridge submodule chain and an arm inductor. By adjusting the amplitude and phase of the DC voltage and AC voltage on the DC power flow control module, energy balance can be achieved between the DCPFC and the MMC, as well as internal energy balance within the multi-port DCPFC. Additionally, active control of the DC power flow on three output lines can be realized.

For the system illustrated in FIG. 6, which is based on the multi-port DCPFC, the DC voltage of the multi-port DCPFC is adjusted through DC power flow control loops, thereby altering the DC voltage of the output lines and achieving control of the DC power flow. The energy balance between the DCPFC and the MMC, as well as the internal energy balance of the multi-port flexible AC interconnection device, is controlled through energy balance control loops between the MMC and the DCPFC, and internal energy balance control loops of the DCPFC, ensuring stable capacitor voltages across all submodules of the multi-port DCPFC.

Embodiment 2

Referring to FIGS. 7-11, the submodule topology of the multi-port DCPFC is consistent with Embodiment 1; however, the number of lines connected to the DCPFC is changed to two. In this embodiment, the multi-port DCPFC is controlled through active restriction of fault currents under DC short-circuit faults. When a DC short-circuit fault occurs, both the fault protection method for the DCPFC under DC short-circuit faults and the active fault current restriction method are applied to suppress the rise in submodule capacitor voltages of the DCPFC and to control the increase in fault currents, ensuring stable operation of the device under complex extreme conditions and assisting the DC grid in suppressing and clearing faults.

In this embodiment, the principles for achieving multi-line DC power flow control, energy balance between the multi-port DCPFC and the MMC, as well as internal energy balance of the multi-port DCPFC, are the same as those in the previous embodiment, which will not be repeated here.

The following provides further explanation of the application of the structures and methods in the two aforementioned embodiments, combined with specific simulation examples.

Based on the previous embodiments, MATLAB/Simulink software is used for system simulation and validation, with simulation parameters as shown in Table 1.

TABLE 1
Simulation parameters
	Parameter	Numerical value
	Rated capacity of MMC	1500	MVA
	DC rated voltage	500	kV
	AC rated voltage	260	kV
	Submodule capacitance of MMC	15	mF
	Number of submodules of arm of MMC	233
	Submodule bus voltage of MMC	2300	V
	Arm inductance of MMC	8	mH
	Number of DC power flow control units	3
	Number of submodules of arm of DCPFC	10
	Submodule capacitance of DCPFC	15	mF
	Submodule capacitor voltage of DCPFC	2300	V
	Arm inductance of DCPFC	1.4	mH
	Line resistance R1	5.0Ω
	Line resistance R2	2.0Ω
	Line resistance R3	3.0Ω
	Line inductance L1	192	mH
	Line inductance L2	174	mH
	Line inductance L3	184	mH

Simulation Example 1

Embodiment 1 features a multi-port DCPFC embedded within a MMC, with its installation position in a DC system illustrated in FIG. 4. The specific topology of the DCPFC and the MMC is shown in FIG. 7, and the control method for Embodiment 1 is depicted in FIG. 8. The multi-port DCPFC is connected to three DC lines and controls the DC power flow by adjusting the DC voltage of output ports, corresponding to DC power flow control loops. The DCPFC is embedded into the MMC to achieve overall energy balance through coordinated control, corresponding to energy balance control loops between the MMC and the DCPFC. Inside the DCPFC, energy balance among the submodules is achieved by injecting fundamental frequency circulating current, corresponding to internal energy balance control loops of the DCPFC.

To verify the power flow control capability of the multi-port DCPFC, the stability of energy balance control within the device, and the rationality of the main circuit parameter design, simulations are conducted based on two operating conditions set according to the power direction of the MMC. Each operating condition is divided into two stages: the power flow distribution during uncontrolled power flow and controlled power flow. The specific operating conditions are designed as follows:

Condition 1 (Rectification Mode):

Stage One (Natural Flow): The rectification power of the MMC is 1500 MW. In this case, the DCPFC is inactive, so the DC line power flow is distributed naturally according to line impedance. Since the resistances of the three DC lines are different, the currents in the three DC lines are not consistent, as shown in FIG. 8(c) within the interval [0˜3 s];

Stage Two (Controlled Flow): By utilizing DC voltage differences at each port of the DCPFC, port voltages and port voltage differences are shown in FIGS. 8(a) and 8(e). This control ensures that the currents in the DC lines connected to the three DC ports are consistent, as illustrated in FIG. 8(c) within the interval [3˜6 s]. The internal submodule capacitor voltage waveform graphs of the MMC and the DCPFC for Condition 1 are shown in FIG. 8(g).

Condition 2 (Inversion Mode):

Stage One (Natural Flow): The inversion power of the MMC is 1500 MW. In this case, the DCPFC is inactive, so the DC line power flow is distributed naturally according to line impedance. Since the resistances of the three DC lines are different, the currents in the connected DC lines are not consistent, as shown in FIG. 8(d) within the interval [0˜3 s];

Stage Two (Controlled Flow): By utilizing DC voltage differences at each port of the DCPFC, port voltages and port voltage differences are shown in FIGS. 8(b) and 8(f). This control ensures that the currents in the DC lines connected to the three DC ports are consistent, as illustrated in FIG. 8(d) within the interval [3˜6 s]. The internal submodule capacitor voltage waveform graphs of the MMC and the DCPFC for Condition 2 are shown in FIG. 8(h).

FIG. 8 presents the simulation results for Condition 1 and Condition 2 in Embodiment 1, consisting of eight waveform graphs. Shown from left to right and top to bottom are: the DC voltage waveform graphs of the line ports for Condition 1 and Condition 2, the DC current waveform graphs of the line ports for Condition 1 and Condition 2, the DC voltage difference waveform graphs of the line ports for Condition 1 and Condition 2, and the internal submodule capacitor voltage waveform graphs of the MMC and the DCPFC for Condition 1 and Condition 2.

The simulation waveform results indicate that, under different DC current directions, the embedded multi-port DCPFC can effectively regulate the power flow in multiple DC lines and possesses the capability for bidirectional power flow control. The energy balance control loops between the MMC and the DCPFC, as well as the internal energy balance control loops of the DCPFC, can effectively maintain the energy balance of the submodules of the device. Additionally, the main circuit parameter designing method can effectively select the electrical parameters of the main circuit.

Simulation Example 2

The multi-port DCPFC in Embodiment 2 is connected to two lines, as shown in FIG. 9. The control strategy during steady-state operation remains consistent with Embodiment 1, as illustrated in FIG. 7. The difference is that Embodiment 2 incorporates a current suppression strategy for DC short-circuit faults.

In the simulation, it is assumed that a bipolar short circuit occurs at DC port 1 of the multi-port DCPFC, as shown in FIG. 9.

Condition 1 (Fault Protection of the DCPFC):

1.5 ms after the fault occurs, fault location is completed, and the submodules of the DCPFC are bypassed to prevent fault currents from entering submodule capacitors, thus achieving fault protection.

Condition 2 (Active Fault Current Suppression):

1.5 ms after the fault occurs, the active current limiting strategy is executed, that is, to position the bipolar submodule in the forward position to create a reverse voltage, mitigating the surge of fault currents and facilitating system fault ride-through.

FIGS. 10 and 11 present the simulation results for Condition 1 and Condition 2. FIG. 10 comprises four waveform graphs. Shown from left to right and top to bottom are: submodule capacitor voltages of two DC power flow control units with and without the fault protection strategy, and submodule switching device currents of two DC power flow control units with and without the fault protection strategy. FIG. 11 comprises four waveform graphs. Shown from left to right and top to bottom are: a comparison waveform graph of fault currents before and after adding the fault current limiting strategy to the MMC, a comparison waveform graph of fault currents at two ports before and after adding the fault current limiting strategy to the multi-port DCPFC, a comparison waveform graph of submodule capacitor voltages before and after adding the fault current limiting strategy to the MMC, and a comparison waveform graph of submodule capacitor voltages before and after adding the fault current limiting strategy to the multi-port DCPFC.

The simulation waveform results indicate that the fault protection strategy of the embedded multi-port DCPFC can effectively prevent fault currents from entering the submodule capacitors, thus avoiding overvoltage in the submodule capacitors. The protection method for the embedded multi-port DCPFC under DC short-circuit faults can effectively suppress the fault currents of the DCPFC, while also providing a certain level of suppression for the fault currents of the MMC.

It is important to note that the configuration and arrangement of the present application shown in various exemplary embodiments are merely exemplary. Although only a few embodiments have been described in detail in this disclosure, those who refer to this disclosure will easily understand that many modifications are possible (for example, changes in the dimensions, scales, structures, shapes and proportions of various elements, as well as parameter values (e.g., temperature, pressure, etc.), installation arrangement, use of materials, color and orientation) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, an element shown as being integrally formed may be composed of multiple parts or elements, the position of the elements may be inverted or otherwise changed, and the nature or number or position of discrete elements may be modified or changed. Therefore, all such modifications are intended to be included within the scope of the present disclosure. The order or sequence of any process or method steps may be changed or reordered according to alternative embodiments. In the claims, any “means-plus-function” clause is intended to cover the structure described herein that performs the stated function, not just structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

Additionally, to provide a concise description of the exemplary embodiments, not all features of the actual embodiments may be described (i.e., those features that are not relevant to the best mode of carrying out the disclosure currently under consideration or those features that are not related to the implementation of the disclosure).

It should be understood that during the development of any actual embodiment, as in any engineering or design project, a multitude of specific implementation decisions may be made. Such development efforts can be complex and time-consuming; however, for those skilled in the art benefiting from this disclosure, it is expected that such development efforts will involve routine work in design, manufacturing, and production without requiring excessive experimentation.

It should be noted that the above embodiments are provided to illustrate the technical scheme of the present disclosure and are not intended to limit them. Although the present disclosure has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical scheme of the present disclosure without departing from the spirit and scope of the technical scheme of the disclosure, all of which should be included within the scope of the claims of the present disclosure.

It should be noted that the above embodiments are provided to illustrate the technical scheme of the present disclosure and are not intended to limit them. Although the present disclosure has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical scheme of the present disclosure without departing from the spirit and scope of the technical scheme of the disclosure, all of which should be included within the scope of the claims of the present disclosure.

It should be understood by those skilled in the art that the embodiments of the application can be provided as methods, systems, or computer program products. Therefore, the application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the application may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk memory, CD-ROM, optical memory, etc.) having computer usable program code embodied therein. The schemes in the embodiments of the application can be implemented in various computer languages, such as object-oriented programming language Java and interpreted scripting language JavaScript.

The application is described with reference to flowcharts and/or block diagrams of methods, equipment (systems), and computer program products according to the embodiments of the application. It should be understood that each flow and/or block in the flowchart and/or block diagram, and combinations of flows and/or blocks in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing equipment to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a device for implementing the functions specified in one or more flows in the flowcharts and/or one or more blocks in the block diagrams.

These computer program instructions may also be stored in a computer-readable memory which can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device which implements the functions specified in one or more flows in the flowcharts and/or one or more blocks in the block diagrams.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus such that a series of operational steps are performed on the computer or other programmable apparatus to produce a computer implemented process, such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one or more flows in the flowcharts/or one or more blocks in the block diagrams.

Although the preferred embodiments of the application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the application.

Obviously, various modifications and variations can be made to this application by those skilled in the art without departing from the spirit and scope of this application. Thus, the application is also intended to comprise such modifications and variations if they fall within the scope of the claims of the application and their equivalents.

Claims

1. A flexible direct current (DC) converter featuring multi-port DC power flow control, comprising: a modular multilevel converter (MMC); anda DC power flow controller (DCPFC) embedded within the MMC.

2. The flexible DC converter according to claim 1, wherein the DCPFC comprises two or more DC power flow control units, a number of the DC power flow control units is equal to a number of ports of the DCPFC, and each DC power flow control unit is capable of adjusting a DC power flow on a connected DC line.

3. The flexible DC converter according to claim 2, wherein each of the DC power flow control units consists of a three-phase star-connected submodule chain and an arm inductor, and a three-phase neutral point resulting from a connection of the submodule chain and the inductor serves as a DC power flow regulation port.

4. The flexible DC converter according to claim 3, wherein the MMC is a medium- or high-voltage, three-phase voltage source converter with a modular multilevel structure, capable of alternating current (AC)-DC power conversion, facilitating interconnection of medium- and high-voltage AC power grids with DC systems.

5. The flexible DC converter according to claim 4, wherein the embedded DCPFC is symmetrically installed on both upper and lower arms of the MMC, or installed on either an upper arm or a lower arm of the MMC.

6. The flexible DC converter according to claim 5, wherein the submodule chain is a unipolar submodule chain, a bipolar submodule chain, or a hybrid submodule chain comprising both unipolar and bipolar submodules.

7. A control method of the embedded DCPFC according to claim 1, comprising DC power flow control loops on multiple lines, energy balance control loops between the MMC and the DCPFC, and internal energy balance control loops within the DCPFC, wherein when the embedded DCPFC connects two or more DC lines, a sum of power on all output lines equals a total power of the MMC; when the embedded DCPFC connects a total of N DC output lines, active control is performed on the power flow of N−1 lines, while DC power flow on the remaining line equals the total power flow minus a sum of the power flow on the N−1 lines.

8. The control method according to claim 7, wherein for the DC power flow control loops on multiple lines, a line power flow control loop calculates a difference between voltage reference values of other lines and a reference circuit voltage to determine DC components of voltages of each DC power flow control unit, and mathematical equations are as follows:

9. The control method according to claim 8, wherein for the energy balance control loops between the MMC and the DCPFC, by superimposing energy balancing control voltages on arms of the DC flow power control units and arms of the modular multilevel converter, AC coupled energy is formed to compensate for accumulated DC energy, and mathematical equations for the overall input and output energy of the DCPFC are as follows:

10. The control method according to claim 9, wherein for the internal energy balance control loops within the DCPFC, a mathematical equation for the energy relationship within the DCPFC is as follows:

11. A main circuit parameter designing method for the embedded DCPFC according to claim 1, comprising design of a number of submodules of the DC power flow control unit and a number of the MMC, design of capacitance of the submodules of the DC power flow control unit and the MMC, design of arm inductance of the DCPFC, and design of power devices of the submodules of the DC power flow control unit and the MMC.

12. The main circuit parameter designing method according to claim 11, wherein the DCPFC is installed asymmetrically, embedded at an end of an upper arm of the MMC; and the DCPFC uses bipolar full-bridge submodules, and the MMC employs unipolar half-bridge submodules.

13. The main circuit parameter designing method according to claim 12, wherein for the design of the number of submodules of the DC power flow control unit and the MMC, a mathematical equation for selecting the number of submodules of the DCPFC is as follows:

14. The main circuit parameter designing method according to claim 13, wherein for the design of the capacitance of submodules of the DC power flow control unit and the MMC, mathematical equations for selecting the capacitance value of submodules of the DCPFC are as follows:

15. The main circuit parameter designing method according to claim 14, wherein for the design of the arm inductance of the DCPFC, mathematical equations for selecting the arm inductance of the DCPFC are as follows:

16. The main circuit parameter designing method according to claim 15, wherein for the design of power devices of submodules of the DC power flow control unit and the MMC, mathematical equation for calculating voltage and current stresses of the power devices of the DC power flow control unit are as follows:

17. A protection method for the embedded DCPFC according to claim 1 under DC short-circuit faults, comprising protection of the DCPFC under DC short-circuit faults, and active restriction of fault currents under DC short-circuit faults.

18. The protection method according to claim 17, wherein the protection of the DCPFC under DC short-circuit faults comprises: controlling the submodules within the DCPFC to operate in a specific switching state, or installing a protection device on the submodules within the DCPFC;wherein the specific switching state of the submodule refers to a condition where a submodule capacitor is bypassed and currents flow solely through a switching device, and the protection device consists of a load shedding circuit or a thyristor bypass switch; andthe switching device of the submodule withstands fault currents, and by operating the submodule in the specific switching state, the fault currents are prevented from flowing into the submodule capacitor, thus achieving fault protection.

19. The protection method according to claim 18, wherein the protection device is a load shedding circuit connected in parallel with the submodule capacitor, and the load shedding circuit is formed by a combination of diodes, resistors, and switching devices in series and parallel, which dissipates the energy of the fault currents to prevent overvoltage across the submodule capacitor, thereby achieving fault protection.

20. The protection method according to claim 19, wherein the protection device is a distributed or centralized thyristor bypass switch, the thyristor bypass switch consists of anti-parallel thyristors, a resistor-capacitor circuit, and static resistors connected in parallel, the distributed thyristor bypass switches are installed within each submodule, and the centralized thyristor bypass switches are connected in parallel with the submodule chains; and the submodules are bypassed through the fast action of the bidirectional thyristors, preventing the fault currents from flowing through the submodules, thus achieving fault protection.

21. The protection method according to claim 17, wherein the active restriction of fault currents under DC short-circuit faults comprises: controlling the submodules within the DCPFC to operate in a specific switching state, or installing a protection device on the submodules within the DCPFC;wherein the specific switching state of the submodule refers to a condition where the submodule is locked or positively engaged, the protection device consists of a load shedding circuit and a fault current limiter, the load shedding circuit is formed by a combination of diodes, resistors, and switching devices arranged in series and parallel, and the fault current limiter is formed by a combination of resistors, inductors, and surge arresters arranged in series and parallel; andthe submodule capacitor withstands a certain fault voltage, the switching device of the submodule endures the fault currents, and by operating the submodule in a specific switching state, the submodule is integrated into the circuit with a negative voltage, effectively suppressing the fault currents.

22. The protection method according to claim 21, wherein the protection device is a load shedding circuit connected in parallel with the submodule capacitor, enabling active suppression of step-down fault currents; the protection device is a distributed or centralized fault current limiter, which is composed of thyristor bypass switches, resistors, inductors, and surge arresters connected in series, the distributed fault current limiters are installed within each submodule, and the centralized fault current limiters are connected in parallel with the submodule chains; and by means of the fault current limiter, the rise of fault currents is restricted, assisting a DC grid in suppressing and clearing faults.