Claims
- 1. A method for storing and accessing data comprising:
receiving a stream of incoming data; producing a single stream of internal data, each internal datum comprising one or more data contained in said stream of incoming data; storing said internal data in a single-address-space memory store; accessing said single-address-space memory store to produce accessed internal data; producing outgoing data from said accessed internal data; and outputting said outgoing data on two or more output ports, including for each of said accessed data serializing said one or more data contained therein to produce serialized data and outputting said serialized data onto one of said one or two or more output ports.
- 2. The method of claim 1 wherein said storing includes generating addresses, each address being generated concurrently with production of an internal datum.
- 3. The method of claim 1 wherein a data width of said incoming data is different from a data width of said outgoing data.
- 4. The method of claim 1 wherein said internal data are stored in said single-address-space memory store in FIFO (first-in-first-out) fashion.
- 5. The method of claim 1 wherein said producing outgoing data includes combining data contained in two or more of said accessed internal data.
- 6. The method of claim 1 wherein said producing outgoing data includes outputting only some of the data contained in each accessed internal datum over one of said output ports.
- 7. A method for storing and accessing data comprising:
receiving a plurality of incoming data streams; delaying an ith input stream by (n−1) units of time for every value of i from 1 to N, where N is the number of said incoming data streams, to produce delayed input data streams; producing a single stream of internal data, said stream of internal data comprising plural data lanes, said producing including shifting corresponding data in each of said delayed input data streams to one of said data lanes so that each said data lane comprises a stream of corresponding data from each of said internal data streams; storing said internal data in a first memory store; accessing said first memory store to produce one or more accessed internal data; and producing an outgoing data stream of outgoing data.
- 8. The method of claim 7 wherein each outgoing datum comprises data contained in one or more of said accessed internal data.
- 9. The method of claim 7 wherein those of said internal data which are produced from the same incoming data stream are stored in FIFO (first-in-first-out) fashion.
- 10. The method of claim 7 wherein said first memory store is addressed by a single address space.
- 11. The method of claim 7 further including detecting flag information contained in said incoming data streams and in response thereto producing a stream of tags, each tag corresponding to one of said internal data.
- 12. The method of claim 11 wherein said tags are stored in said first memory store.
- 13. The method of claim 11 wherein said tags are stored in a second memory store.
- 14. The method of claim 13 wherein said first and said second memory stores are addressed in the same address space.
- 15. The method of claim 7 wherein each of said internal words has a width that is an integral multiple of the smallest data width of said incoming data streams.
- 16. The method of claim 7 wherein each of said internal words has a width that is a power-of-two multiple of the smallest data width of said incoming data streams.
- 17. A method for buffering data comprising:
providing a first memory store having a single address space associated therewith; receiving a plurality of data streams, each data stream having a data width; merging said data streams to produce a single stream of internal words, including combining one or more data from a data stream to produce an internal word, each of said internal words having a first data width being at least as wide as the widest of said data streams; and storing all of said internal words in said first memory store, said merging including shifting corresponding data in each of said data streams to a form one or more internal data lanes, each internal word comprising data from each of said data lanes.
- 18. The method of claim 17 wherein said storing includes producing an address at a rate equal to production of said internal words.
- 19. The method of claim 17 wherein those of said internal words that are produced from the same data stream are stored in FIFO (first-in-first-out) order.
- 20. The method of claim 17 further including detecting flag information contained in said data streams and in response thereto producing a stream of tags, each tag corresponding to one of said internal data.
- 21. The method of claim 20 further including storing said tags in said first memory store.
- 22. The method of claim 20 further including storing said tags in a second memory store.
- 23. The method of claim 22 wherein said first and said second memory stores are addressed in the same address space.
- 24. The method of claim 17 wherein each of said internal words has a width that is an integral multiple of the smallest data width of said incoming data streams.
- 25. The method of claim 17 wherein each of said internal words has a width that is a power-of-two multiple of the smallest data width of said incoming data streams.
- 26. A data buffer comprising:
a first input port for receiving first incoming data; at least a second input port for receiving second incoming data; an input unit operative to produce a single stream of internal data comprising a first plurality of internal data and a second plurality of internal data, said first plurality of internal data comprising said first incoming data, said second plurality of internal data comprising said second incoming data; a memory store coupled to receive said single stream of internal data for storage therein; an output unit coupled to said memory store, said output unit operative to produce first outgoing data comprising said first plurality of internal data read from said memory store, said output unit operative to produce second outgoing data comprising second internal data read from said memory store; a first output port for outputting said first outgoing data; a second output port for outputting said second outgoing data; and an address generation unit operatively coupled to said memory store to store and retrieve said internal data, said input unit and said address generation unit being synchronized to a plurality of time slots, said input unit configured to produce an internal datum during each said time slots, said address generation unit configured to produce a write address and a read address during each of said time slots.
- 27. The data buffer of claim 26 wherein said address generation unit produces addresses belonging to a single address space.
- 28. The data buffer of claim 26 wherein said address generation unit is configured to: (i) store and access said internal data in first-in-first-out (FIFO) fashion; (ii) store and access said first internal data in a first FIFO data structure; and (iii) store and access said second internal data in a second FIFO data structure.
- 29. The data buffer of claim 26 wherein said first incoming data have a data width that is an integral multiple of a data width of said second incoming data.
- 30. The data buffer of claim 29 wherein said integral multiple is a power of two.
- 31. The data buffer of claim 26 wherein said input unit is further operative to produce a plurality of tags based on flag information contained in said incoming data, each tag corresponding to one of said internal data.
- 32. The data buffer of claim 31 further including a second memory store coupled to receive said tags.
- 33. The data buffer of claim 31 wherein said tags are stored in and accessed from said memory store.
- 34. A data buffer comprising:
a plurality of data inputs, each data input for receiving a plurality of incoming data; input logic coupled to said data inputs and configured to produce a single stream of internal words from said incoming data, each internal word associated with one of said data inputs and comprising one or more of said incoming data received therefrom; a memory store coupled to said input logic to store said internal words; an address generator coupled to said memory store, said address generator effective for producing an address from a single address space; output logic coupled to said memory store and configured to access said memory store to produce a plurality of accessed internal words and to produce a plurality of outgoing data therefrom.
- 35. The data buffer of claim 34 further including an input sequence controller and an output sequence controller operative with said address generator to address said memory store such that each of said data inputs has an associated first-in-first-out (FIFO) data structure and internal words associated with a data input are stored in its associated FIFO.
- 36. The data buffer of claim 34 wherein said input logic is further configured to identify flag information contained in said incoming data and to produce a plurality of tags therefrom, each of said tags corresponding to one of said internal words.
- 37. The data buffer of claim 36 further including a second memory store coupled to receive said tags.
- 38. A data buffer comprising:
an input port for receiving a data stream of input data; a memory coupled to receive said input data; and an output unit coupled to receive data from said memory store, said output unit having a first output port and a second output port, said output unit configured to produce first outgoing data for said first output port and second outgoing data for said second output port, said first outgoing data comprising one or more data read from said memory store, said second outgoing data comprising one or more data read from said memory store.
- 39. The data buffer of claim 38 wherein said input data are combined to produce internal words of equal width, said internal words being stored in said memory store.
- 40. The data buffer of claim 38 wherein said memory store is addressed by a single address space.
- 41. The data buffer of claim 38 wherein said first output data has a data width different from that of said second output data.
- 42. The data buffer of claim 41 wherein data widths of said first output data and said second output data are different from that of said input data.
- 43. The data buffer of claim 38 wherein said memory store is accessed in first-in-first-out manner.
- 44. A data buffer comprising:
a plurality of input ports for inputting plural data streams; an input unit coupled to receive said data streams and operative to produce a single stream of internal data, said internal data comprising one or more data contained in one of said data streams; a memory store coupled to store said internal data; an output unit coupled to receive internal data from said memory store and to output outgoing data; and an address generator operative to produce addresses for storing and reading out said internal data such that internal data produced by data from a first data stream are stored in first-in-first-out (FIFO) order, said outgoing data comprising one or more of said internal data.
- 45. The data buffer of claim 44 wherein said input unit is further operative to produce plural tags from flag information contained in said data streams.
- 46. The data buffer of claim 45 further including a second memory for storing said tags.
- 47. The data buffer of claim 45 wherein said tags are stored in said memory store.
- 48. A data buffer comprising:
means for receiving a plurality of data streams; means for merging said data streams to produce a single stream of internal data, each internal datum comprising one or more incoming data from one of said data streams; memory means for storing said internal data; means for reading out one or more internal data from said memory means; and means for outputting outgoing data, each outgoing datum comprising said one or more incoming data contained in one or more of said internal data.
- 49. The data buffer of claim 48 wherein said means for outputting includes means for outputting said outgoing data on a plurality of output ports.
- 50. The data buffer of claim 48 wherein said memory means has a single address space.
- 51. The data buffer of claim 48 wherein said means for reading includes an address generator which produces an address from a single address space.
- 52. The data buffer of claim 48 wherein said means for reading includes an address generator which produces an address concurrently with each of said internal data.
- 53. The data buffer of claim 48 further including means for detecting flag information contained in said incoming data streams and for producing a stream of tags from said flag information, each tag corresponding to one of said internal data.
- 54. The data buffer of claim 53 wherein said tags are stored in said memory means.
- 55. The data buffer of claim 53 wherein said tags are stored in a second memory means.
- 56. The data buffer of claim 55 wherein said means for reading includes an address generator for producing an address from a single address space, said address being used to address said memory means and said second memory means.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to co-pending and co-owned U.S. application Ser. No. __/____, entitled “Multi-Stream Merge Network For Data Width Conversion and Multiplexing,” filed Year 2001 (Docket No. 502P36US, Reference No. PMC-2000295) and is herein incorporated by reference for all purposes.