Patent Grant
9602210
The technology of the present disclosure relates generally to an optical fiber-based distributed antenna system (DAS), and more particularly to a flexible head-end chassis that includes a plurality of module slots each configured to flexibly receive either a radio interface module (RIM) or an optical interface module (OIM), and provide automatic identification and interconnection of the received RIM or OIM in the optical-fiber based DAS.
Wireless communication is rapidly growing, with ever-increasing demands for high-speed mobile data communication. As an example, local area wireless services (e.g., so-called “wireless fidelity” or “WiFi” systems) and wide area wireless services are being deployed in many different types of areas (e.g., coffee shops, airports, libraries, etc.). Distributed communications or antenna systems communicate with wireless devices called “clients,” “client devices,” or “wireless client devices,” which must reside within the wireless range or “cell coverage area” in order to communicate with an access point device. Distributed antenna systems are particularly useful to be deployed inside buildings or other indoor environments where client devices may not otherwise be able to effectively receive radio-frequency (RF) signals from a source, such as a base station for example. Example applications where distributed antenna systems can be used to provide or enhance coverage for wireless services include public safety, cellular telephony, wireless local access networks (LANs), location tracking, and medical telemetry inside buildings and over campuses.
One approach to deploying a distributed antenna system involves the use of RF antenna coverage areas, also referred to as “antenna coverage areas.” Antenna coverage areas can be formed by remotely distributed antenna units, also referred to as remote units (RUs). The remote units each contain or are configured to couple to one or more antennas configured to support the desired frequency(ies) to provide the antenna coverage areas. Antenna coverage areas can have a radius in the range from a few meters up to twenty meters as an example. Combining a number of remote units creates an array of antenna coverage areas. Because the antenna coverage areas each cover small areas, there typically may be only a few users (clients) per antenna coverage area. This arrangement generates a uniform high quality signal enabling high throughput supporting the required capacity for the wireless system users.
As an example,
Optical fiber can also be employed in the DAS 12 in
With continuing reference to
With continuing reference to
No admission is made that any reference cited herein constitutes prior art. Applicant expressly reserves the right to challenge the accuracy and pertinency of any cited documents.
Embodiments disclosed herein include flexible head-end chassis supporting automatic identification and interconnection of radio interface modules (RIMs) and optical interface modules (OIMs) in an optical fiber-based distributed antenna system (DAS). Related methods and DASs are also disclosed. The flexible head-end chassis is provided as part of head-end equipment in an optical fiber-based DAS. In one embodiment, the flexible head-end chassis includes a plurality of module slots. Each of the module slots is configured to receive either a RIM or an OIM. The flexible head-end chassis includes a backplane configured to be interconnected with a RIM or OIM fully inserted into a module slot of the flexible head-end chassis. When a RIM or OIM is inserted into a module slot of the flexible head-end chassis and interconnected to the backplane, a chassis control system identifies the inserted RIM or OIM to determine which type of module is inserted in the module slot. Based on the identification of the inserted RIM or OIM, the chassis control system interconnects the inserted RIM or OIM to related signal routing circuitry (e.g., combiners and splitters) in the head-end equipment needed for the RIM or OIM to be capable of receiving downlink communications signals and uplink communications signals for processing and distribution in the optical fiber-based DAS. In this manner, the optical fiber-based DAS can easily be configured or reconfigured with different numbers and combinations of RIMs and OIMs, as needed or desired, for the optical fiber-based DAS to support the desired communications services and/or number of remote units.
One embodiment of the disclosure relates to a head-end chassis for an optical fiber-based DAS. The head-end chassis comprises a housing. The head-end chassis also comprises a plurality of module slots disposed in the housing. Each module slot among the plurality of module slots is configured to receive a connected module comprised of a radio interface module (RIM) or an optical interface module (OIM). The head-end chassis also comprises a backplane disposed in the housing. The backplane comprises a plurality of backplane interconnects each associated with a module slot among the plurality of module slots, each backplane interconnect among the plurality of backplane interconnects configured to interconnect with the connected module inserted into the module slot associated with the backplane interconnect. Each backplane interconnect among the plurality of backplane interconnects comprises a backplane downlink input configured to receive an electrical downlink communications signal from a RIM, a backplane downlink output configured to provide an electrical split downlink communications signal to an OIM, a backplane uplink input configured to receive an electrical uplink communications signal from an OIM, and a backplane uplink output configured to provide an electrical split uplink communications signal to a RIM. The backplane also comprises a plurality of combiner downlink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner downlink inputs is configured to receive a plurality of electrical downlink communications signals from a plurality of RIMs, combine the received plurality of electrical downlink communications signals into an electrical combined downlink communications signal, and provide the electrical combined downlink communications signal on a combiner downlink output. The backplane also comprises a downlink splitter comprising a splitter downlink input. The splitter downlink input is configured to receive the electrical combined downlink communications signal from the combiner downlink output, split the received electrical combined downlink communications signal into a plurality of electrical split downlink communications signals, and provide the plurality of electrical split downlink communications signals on a plurality of splitter downlink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The backplane also comprises an uplink combiner comprising a plurality of combiner uplink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner uplink inputs is configured to receive a plurality of electrical uplink communications signals from at least one OIM, combine the received plurality of electrical uplink communications signals into an electrical combined uplink communications signal, and provide the electrical combined uplink communications signal on a combiner uplink output. The backplane also comprises an uplink splitter comprising a splitter uplink input. The splitter uplink input is configured to receive the electrical combined uplink communications signal from the combiner uplink output, split the received electrical combined uplink communications signal into a plurality of electrical split uplink communications signals, and provide the plurality of electrical split uplink communications signals on a plurality of splitter uplink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects.
The backplane also comprises a plurality of downlink switches each configured to selectively couple, in response to a downlink switch selector, either the backplane downlink input of a backplane interconnect connected to a RIM, to a corresponding combiner downlink input among the plurality of combiner downlink inputs to provide the electrical downlink communications signal from the RIM to the downlink combiner; or the backplane downlink output of the backplane interconnect connected to an OIM, to a corresponding splitter downlink output among the plurality of splitter downlink outputs to provide the electrical split downlink communications signal to the OIM. The backplane also comprises a plurality of uplink switches each configured to selectively couple, in response to an uplink switch selector, either the backplane uplink output of a backplane interconnect connected to the RIM, to a corresponding splitter uplink output among the plurality of splitter uplink outputs to provide the electrical split uplink communications signal to the RIM; or the backplane uplink input of the backplane interconnect connected to the OIM, to a corresponding combiner uplink input among the plurality of combiner uplink inputs to provide the electrical uplink communications signal from the OIM to the uplink combiner.
Another embodiment of the disclosure relates to a method for interconnecting a connected module in a head-end chassis with head-end equipment in an optical fiber-based DAS. The method comprises detecting a connection of a connected module comprised of a RIM or an OIM, to a backplane interconnect of a module slot among a plurality of module slots in a head-end chassis. The method also comprises determining if the connected module in the module slot is a RIM or an OIM. If the connected module in the module slot is determined to be a RIM, the method comprises coupling the backplane interconnect connected to the RIM to a downlink combiner. The downlink combiner is configured to receive an electrical downlink communications signal from the RIM, combine the received electrical downlink communications signal into an electrical combined downlink communications signal and provide the electrical combined downlink communications signal to a downlink splitter. The method also comprises coupling the backplane interconnect connected to the RIM to an uplink splitter. The uplink splitter is configured to receive an electrical combined uplink communications signal from an uplink combiner, split the electrical combined uplink communications signal into the plurality of electrical split uplink communications signals, and provide the electrical split uplink communications signal to the RIM. If the connected module in the module slot is determined to be an OIM, the method comprises coupling the backplane interconnect connected to the OIM to a downlink splitter. The downlink splitter is configured to receive the electrical combined downlink communications signal from the downlink combiner, split the received electrical combined downlink communications signal into an electrical split downlink communications signal, and provide the electrical split downlink communications signal to the OIM. The method also comprises coupling the backplane interconnect connected to the OIM to an uplink combiner. The uplink combiner is configured to receive an electrical uplink communications signal from the OIM, combine the received electrical uplink communications signal into the electrical combiner uplink communications signal, and provide the electrical combined uplink communications signal to the uplink splitter.
Another embodiment of the disclosure relates to an optical fiber-based DAS. The optical fiber-based DAS comprises a central unit. The central unit comprises a plurality of RIMs each configured to receive an electrical downlink communications signal and receive an electrical split uplink communications signal from at least one OIM. The central unit also comprises a plurality of OIMs. Each OIM is configured to receive an electrical split downlink communications signal, convert the received electrical split downlink communications signal into an optical split downlink communications signal, distribute the optical split downlink communications signal to a plurality of remote units, receive a plurality of optical uplink communications signals from the plurality of remote units, and convert the received plurality of optical uplink communications signals to a plurality of electrical uplink communications signals. Each of the plurality of remote units is configured to receive the optical split downlink communications signal from the central unit, convert the received optical split downlink communications signal into an electrical split downlink communications signal, distribute the electrical split downlink communications signal to at least one client device, receive an electrical uplink communications signal from the at least one client device, convert the received electrical uplink communications signal into an optical uplink communications signal, and distribute the optical uplink communications signal to the central unit.
The central unit further comprises a head-end chassis. The head-end chassis comprises a housing. The head-end chassis also comprises a plurality of module slots disposed in the housing. Each module slot among the plurality of module slots configured to receive a connected module comprised of a RIM among the plurality of RIMs or an OIM among the plurality of OIMs. The head-end chassis further comprises a backplane disposed in the housing. The backplane comprises a plurality of backplane interconnects each associated with a module slot among the plurality of module slots. Each backplane interconnect among the plurality of backplane interconnects is configured to interconnect with the connected module inserted into the module slot associated with the backplane interconnect. Each backplane interconnect among the plurality of backplane interconnects comprises a backplane downlink input configured to receive the electrical downlink communications signal from a RIM among the plurality of RIMs, a backplane downlink output configured to provide an electrical split downlink communications signal to an OIM among the plurality of OIMs, a backplane uplink input configured to receive an electrical uplink communications signal from the OIM, and a backplane uplink output configured to provide an electrical split uplink communications signal to the RIM. The head-end chassis also comprises a downlink combiner comprising a plurality of combiner downlink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner downlink inputs is configured to receive a plurality of electrical downlink communications signals from the plurality of RIMs, combine the received plurality of electrical downlink communications signals into an electrical combined downlink communications signal, and provide the electrical combined downlink communications signal on a combiner downlink output. The head-end chassis also comprises a downlink splitter comprising a splitter downlink input. The splitter downlink input is configured to receive the electrical combined downlink communications signal from the combiner downlink output, split the received electrical combined downlink communications signal into a plurality of electrical split downlink communications signals, and provide the plurality of electrical split downlink communications signals on a plurality of splitter downlink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The head-end chassis also comprises an uplink combiner comprising a plurality of combiner uplink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner uplink inputs is configured to receive a plurality of electrical uplink communications signals from the plurality of OIMs, combine the received plurality of electrical uplink communications signals into an electrical combined uplink communications signal, and provide the electrical combined uplink communications signal on a combiner uplink output. The head-end chassis also comprises an uplink splitter comprising a splitter uplink input. The splitter uplink input is configured to receive the electrical combined uplink communications signal from the combiner uplink output, split the received electrical combined uplink communications signal into a plurality of electrical split uplink communications signals, and provide the plurality of electrical split uplink communications signals on a plurality of splitter uplink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects.
The head-end chassis also comprises a plurality of downlink switches each configured to selectively couple, in response to a downlink switch selector, either the backplane downlink input of a backplane interconnect connected to a RIM, to a corresponding combiner downlink input among the plurality of combiner downlink inputs to provide the electrical downlink communications signal from the RIM to the downlink combiner; or the backplane downlink output of the backplane interconnect connected to an OIM, to a corresponding splitter downlink output among the plurality of splitter downlink outputs to provide the electrical split downlink communications signal to the OIM. The head-end chassis also comprises a plurality of uplink switches each configured to selectively couple, in response to an uplink switch selector, either the backplane uplink output of a backplane interconnect connected to the RIM, to a corresponding splitter uplink output among the plurality of splitter uplink outputs to provide the electrical split uplink communications signal to the RIM; or the backplane uplink input of the backplane interconnect connected to the OIM, to a corresponding combiner uplink input among the plurality of combiner uplink inputs to provide the electrical uplink communications signal from the OIM to the uplink combiner.
Additional features and advantages will be set forth in the detailed description which follows, and in part, will be readily apparent to those skilled in the art from the description or recognized by practicing the embodiments as described in the written description and claims hereof, as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understand the nature and character of the claims.
The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description serve to explain the principles and operation of the various embodiments.
Various embodiments will be further clarified by the following examples.
Embodiments disclosed herein include flexible head-end chassis supporting automatic identification and interconnection of radio interface modules (RIMs) and optical interface modules (OIMs) in an optical fiber-based distributed antenna system (DAS). Related methods and DASs are also disclosed. The flexible head-end chassis is provided as part of head-end equipment in an optical fiber-based DAS. In one embodiment, the flexible head-end chassis includes a plurality of module slots (e.g., circuit board card slots). Each of the module slots is configured to receive either a RIM or an OIM. The flexible head-end chassis includes a backplane configured to be interconnected with a RIM or OIM fully inserted into a module slot of the flexible head-end chassis. When a RIM or OIM is inserted into a module slot of the flexible head-end chassis and interconnected to the backplane, a chassis control system identifies the inserted RIM or OIM to determine which type of module is inserted in the module slot. Based on the identification of the inserted RIM or OIM, the chassis control system interconnects the inserted RIM or OIM to related signal routing circuitry (e.g., combiners and splitters) in the head-end equipment needed for the RIM or OIM to be capable of receiving downlink communications signals and uplink communications signals for processing and distribution in the optical fiber-based DAS. In this manner, the optical fiber-based DAS can easily be configured or reconfigured with different numbers and combinations of RIMs and OIMs, as needed or desired, for the optical fiber-based DAS to support the desired communications services and/or number of remote units.
In this regard,
As will be discussed in more detail below, when a RIM 66 or OIM 68 is inserted into a particular module slot 64 of the flexible head-end chassis 60 in
In this regard,
First, with reference to the RIMs 66(1), 66(2) in
With continuing reference to
With continuing reference to
With continuing reference to
Thus in summary, as illustrated in
With reference to
To provide the proper downlink connectivity between the module, whether it is a RIM 66 or OIM 68, inserted in a given module slot 64, a plurality of downlink switches 96(1)-96(8) are provided in the backplane 70 for each backplane interconnect 74(1)-74(8). Each downlink switch 96(1)-96(8) is configured to selectively couple either a respective backplane downlink input 88DI(1)-88D1(8) or a respective backplane downlink output 88DO(1)-88DO(8) to the installed module. If the installed module is a RIM 66, the downlink switch 96 is configured to couple a respective backplane downlink input 88DI to a RIM downlink output 98DO for the downlink combiner 84D to receive the electrical downlink communications signal 76E-D from the RIM 66. However, if the installed module is an OIM 68, the downlink switch 96 is configured to couple a respective backplane downlink output 88DO to an OIM downlink input 100DI to receive the electrical split downlink communications signal 76E-D(S) from the downlink splitter 86D.
To provide the proper uplink connectivity between the module, whether it is a RIM 66 or OIM 68, inserted in a given module slot 64, a plurality of uplink switches 102(1)-102(8) are provided in the backplane 70 for each backplane interconnect 74(1)-74(8). Each uplink switch 102(1)-102(8) is configured to selectively couple either a respective backplane uplink output 88UO(1)-88UO(8) or a respective backplane uplink input 88UI(1)-88U1(8) to the installed module. If the installed module is a RIM 66, the uplink switch 102 is configured to couple a respective backplane uplink output 88UO to a RIM uplink input 98UI, to couple the RIM uplink input 98UI to a splitter uplink output 94UO of the uplink splitter 86U for the uplink splitter 86U, to provide the electrical split uplink communications signal 76E-U(S) from the uplink splitter 86U to the RIM 66. However, if the installed module is an OIM 68, the uplink switch 102 is configured to couple a respective backplane uplink input 88UI to an OIM uplink output 100UO, to couple the OIM uplink output 100UO to a combiner uplink input 92UI of the uplink combiner 84U, for the OIM 68 to provide an electrical uplink communications signal 76E-U to the uplink combiner 84U.
With reference to
With continuing reference to
With continuing reference to
With continuing reference to
With continuing reference to
With continuing reference to
The flexible head-end chassis 60 for supporting the RIMs 66 and OIMs 68 provided in an optical fiber-based DAS 78 and automatically identifying and interconnecting a received RIM 66 or OIM 68, may be provided in an optical fiber-based DAS 150 in an indoor environment, as illustrated in
In one embodiment, the central unit 156 is configured to support up to twelve (12) RIMs 66. Each RIM 66 can be designed to support a particular type of radio source or range of radio sources (i.e., frequencies) to provide flexibility in configuring the central unit 156 and the optical fiber-based DAS 150 to support the desired radio sources. For example, one RIM 66 may be configured to support the Personal Communication Services (PCS) radio band. Another RIM 66 may be configured to support the 700 MHz radio band. In this example, by inclusion of these RIMs 66, the central unit 156 could be configured to support and distribute communications signals on both PCS and LTE 700 radio bands, as an example. RIMs 66 may be provided in the central unit 156 that support any frequency bands desired, including but not limited to the US Cellular band, Personal Communication Services (PCS) band, Advanced Wireless Services (AWS) band, 700 MHz band, Global System for Mobile communications (GSM) 900, GSM 1800, and Universal Mobile Telecommunication System (UMTS). The RIMs 66 may also be provided in the central unit 156 that support any wireless technologies desired, including but not limited to Code Division Multiple Access (CDMA), CDMA200, 1×RTT, Evolution-Data Only (EV-DO), UMTS, High-speed Packet Access (HSPA), GSM, General Packet Radio Services (GPRS), Enhanced Data GSM Environment (EDGE), Time Division Multiple Access (TDMA), Long Term Evolution (LTE), iDEN, and Cellular Digital Packet Data (CDPD).
The RIMs 66 may be provided in the central unit 156 that support any frequencies desired, including but not limited to US FCC and Industry Canada frequencies (824-849 MHz on uplink and 869-894 MHz on downlink), US FCC and Industry Canada frequencies (1850-1915 MHz on uplink and 1930-1995 MHz on downlink), US FCC and Industry Canada frequencies (1710-1755 MHz on uplink and 2110-2155 MHz on downlink), US FCC frequencies (698-716 MHz and 776-787 MHz on uplink and 728-746 MHz on downlink), EU R & TTE frequencies (880-915 MHz on uplink and 925-960 MHz on downlink), EU R & TTE frequencies (1710-1785 MHz on uplink and 1805-1880 MHz on downlink), EU R & TTE frequencies (1920-1980 MHz on uplink and 2110-2170 MHz on downlink), US FCC frequencies (806-824 MHz on uplink and 851-869 MHz on downlink), US FCC frequencies (896-901 MHz on uplink and 929-941 MHz on downlink), US FCC frequencies (793-805 MHz on uplink and 763-775 MHz on downlink), and US FCC frequencies (2495-2690 MHz on uplink and downlink).
In this regard, the computer system 170 in
The exemplary computer system 170 in this embodiment includes a processing device or processor 172, a main memory 174 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc.), and a static memory 176 (e.g., flash memory, static random access memory (SRAM), etc.), which may communicate with each other via a data bus 178. Alternatively, the processor 172 may be connected to the main memory 174 and/or static memory 176 directly or via some other connectivity means. The processor 172 may be a controller, and the main memory 174 or static memory 176 may be any type of memory.
The processor 172 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More particularly, the processor 172 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or other processors implementing a combination of instruction sets. The processor 172 is configured to execute processing logic in instructions for performing the operations and steps discussed herein.
The computer system 170 may further include a network interface device 180. The computer system 170 also may or may not include an input 182, configured to receive input and selections to be communicated to the computer system 170 when executing instructions. The computer system 170 also may or may not include an output 184, including but not limited to a display, a video display unit (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device (e.g., a keyboard), and/or a cursor control device (e.g., a mouse).
The computer system 170 may or may not include a data storage device that includes instructions 188 stored in a computer-readable medium 190. The instructions 188 may also reside, completely or at least partially, within the main memory 174 and/or within the processor 172 during execution thereof by the computer system 170, the main memory 174 and the processor 172 also constituting computer-readable medium. The instructions 188 may further be transmitted or received over a network 192 via the network interface device 180.
While the computer-readable medium 190 is shown in an exemplary embodiment to be a single medium, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term “computer-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.
The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.
The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.
Unless specifically stated otherwise and as apparent from the previous discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing,” “computing,” “determining,” “displaying,” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data and memories represented as physical (electronic) quantities within the computer system's registers into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatuses to perform the required method steps. The required structure for a variety of these systems will appear from the description above. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the embodiments as described herein.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a controller may be a processor. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The embodiments disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those of skill in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, that may be references throughout the above description, may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.
Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that any particular order be inferred.
It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and their equivalents.
This application claims the benefit of priority under 35 U.S.C. §119 of U.S. Provisional Application No. 62/054,543, filed on Sep. 24, 2014, the content of which is relied upon and incorporated herein by reference in its entirety.
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| Number | Date | Country | |
|---|---|---|---|
| 20160087725 A1 | Mar 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62054543 | Sep 2014 | US |
