Flexible head-end chassis supporting automatic identification and interconnection of radio interface modules and optical interface modules in an optical fiber-based distributed antenna system (DAS)

Description

BACKGROUND

The technology of the present disclosure relates generally to an optical fiber-based distributed antenna system (DAS), and more particularly to a flexible head-end chassis that includes a plurality of module slots each configured to flexibly receive either a radio interface module (RIM) or an optical interface module (OIM), and provide automatic identification and interconnection of the received RIM or OIM in the optical-fiber based DAS.

Wireless communication is rapidly growing, with ever-increasing demands for high-speed mobile data communication. As an example, local area wireless services (e.g., so-called “wireless fidelity” or “WiFi” systems) and wide area wireless services are being deployed in many different types of areas (e.g., coffee shops, airports, libraries, etc.). Distributed communications or antenna systems communicate with wireless devices called “clients,” “client devices,” or “wireless client devices,” which must reside within the wireless range or “cell coverage area” in order to communicate with an access point device. Distributed antenna systems are particularly useful to be deployed inside buildings or other indoor environments where client devices may not otherwise be able to effectively receive radio-frequency (RF) signals from a source, such as a base station for example. Example applications where distributed antenna systems can be used to provide or enhance coverage for wireless services include public safety, cellular telephony, wireless local access networks (LANs), location tracking, and medical telemetry inside buildings and over campuses.

One approach to deploying a distributed antenna system involves the use of RF antenna coverage areas, also referred to as “antenna coverage areas.” Antenna coverage areas can be formed by remotely distributed antenna units, also referred to as remote units (RUs). The remote units each contain or are configured to couple to one or more antennas configured to support the desired frequency(ies) to provide the antenna coverage areas. Antenna coverage areas can have a radius in the range from a few meters up to twenty meters as an example. Combining a number of remote units creates an array of antenna coverage areas. Because the antenna coverage areas each cover small areas, there typically may be only a few users (clients) per antenna coverage area. This arrangement generates a uniform high quality signal enabling high throughput supporting the required capacity for the wireless system users.

As an example, FIG. 1 illustrates distribution of communications services to coverage areas 10(1)-10(N) of a DAS 12, wherein ‘N’ is the number of coverage areas. These communications services can include cellular services, wireless services such as RFID tracking, Wireless Fidelity (WiFi), local area network (LAN), WLAN, and combinations thereof, as examples. The coverage areas 10(1)-10(N) may be remotely located. In this regard, the remote coverage areas 10(1)-10(N) are created by and centered on remote antenna units 14(1)-14(N) connected to a central unit 16 (e.g., a head-end controller or head-end unit). The central unit 16 may be communicatively coupled to a base station 18. If the DAS 12 is a broadband DAS, the central unit 16 receives downlink communications signals 20D in multiple frequency bands for different communications services from the base station 18 to be distributed to the remote antenna units 14(1)-14(N). The remote antenna units 14(1)-14(N) are configured to receive downlink communications signals 20D from the central unit 16 over a communications medium 22 to be distributed as downlink communications signals 20D to the respective coverage areas 10(1)-10(N) of the remote antenna units 14(1)-14(N). Each remote antenna unit 14(1)-14(N) may include an RF transmitter/receiver (not shown) and a respective antenna 24(1)-24(N) operably connected to the RF transmitter/receiver to wirelessly distribute the downlink communications signals 20D to client devices 26 within their respective coverage areas 10(1)-10(N). The remote antenna units 14(1)-14(N) in the DAS 12 are also configured to receive uplink communications signals 20U in multiple frequency bands from the client devices 26 in their respective coverage areas 10(1)-10(N). The uplink communications signals 20U can be filtered, amplified, and/or combined together into the combined uplink communications signals 20U to be distributed to the central unit 16, and separated into respective bands to distribute to the base station 18.

Optical fiber can also be employed in the DAS 12 in FIG. 1 to communicatively couple the central unit 16 to the remote antenna units 14(1)-14(N) for distribution of the downlink communications signals 20D and the uplink communications signals 20U. Benefits of optical fibers include extremely wide bandwidth and low noise operation. In this regard, FIG. 2 is a schematic diagram of an exemplary optical fiber-based DAS 30 (hereinafter “DAS 30”). The DAS 30 in this example is comprised of three (3) main components. One or more radio interfaces provided in the form of radio interface modules (RIMs) 32(1)-32(M) are provided in a central unit 34 to receive and process received electrical downlink communications signals 36D(1)-36D(R) prior to optical conversion into optical downlink communications signals. The notations “1-R” and “1-M” indicate that any number of the referenced component, 1-R and 1-M, respectively, may be provided. Each RIM 32(1)-32(M) can be designed to support a particular type of radio source or range of radio sources (i.e., frequencies) to provide flexibility in configuring the central unit 34 and the DAS 30 to support the desired radio sources. The electrical downlink communications signals 36D(1)-36D(R) are provided from the RIMs 32(1)-32(M) to a plurality of optical interfaces provided in the form of optical interface modules (OIMs) 38(1)-38(N). The OIMs 38(1)-38(N) each include electrical-to-optical (E/O) converters (not shown) to convert the electrical downlink communications signals 36D(1)-36D(R) into the downlink optical communications signals 40D(1)-40D(R). The optical downlink communications signals 40D(1)-40D(R) are communicated over optical downlink fiber communications medium 42D to a plurality of remote units 44(1)-44(S), which may be remote antenna units. The notation “1-S” indicates that any number of the referenced component, 1-S, may be provided. Optical-to-electrical (O/E) converters (not shown) provided in the remote units 44(1)-44(S) convert the optical downlink communications signals 40D(1)-40D(R) back into the electrical downlink communications signals 36D(1)-36D(R), which are provided to antennas 48(1)-48(S) in the remote units 44(1)-44(S) to client devices (not shown) in the reception range of the antennas 48(1)-48(S).

With continuing reference to FIG. 2, E/O converters (not shown) are also provided in the remote units 44(1)-44(S) to convert received electrical uplink communications signals 50U(1)-50U(S) received from client devices (not shown) through the antennas 48(1)-48(S) into optical uplink communications signals 40U(1)-40U(S). The remote units 44(1)-44(S) communicate the optical uplink communications signals 40U(1)-40U(S) over an uplink optical fiber communications medium 42U to the OIMs 38(1)-38(N) in the central unit 34. The OIMs 38(1)-38(N) include O/E converters (not shown) that convert the received uplink optical communications signals 40U(1)-40U(S) into electrical uplink communications signals 52U(1)-52U(S), which are processed by the RIMs 32(1)-32(M) and provided as electrical uplink communications signals 52U(1)-52U(S). The central unit 34 may provide the electrical uplink communications signals 52U(1)-52U(S) to a base station or other communications system.

With continuing reference to FIG. 2, the central unit 34 includes a dedicated RIM chassis 54 configured to house and support the RIMs 32(1)-32(M) and a dedicated OIM chassis 56 to house and support the OIMs 38(1)-38(N) as modular components. For example, the RIMs 32(1)-32(M) may be provided as circuit board cards that can be installed in circuit board card slots in the RIM chassis 54. When the RIMs 32(1)-32(M) are fully inserted in the RIM chassis 54, the RIMs 32(1)-32(M) connect to a backplane that provides interconnectivity within the optical fiber-based DAS 30. The OIMs 38(1)-38(N) may also be provided as circuit board cards that can be installed in circuit board card slots in the OIM chassis 56. When the OIMs 38(1)-38(N) are fully inserted in the OIM chassis 56, the OIMs 38(1)-38(N) connect to a backplane that provides interconnectivity within the optical fiber-based DAS 30. The number of RIMs 32(1)-32(M) provided in the central unit 34 is based on the number of communications services and/or remote units to be supported in the optical fiber-based DAS 30. The number of OIMs 38(1)-38(M) provided in the central unit 34 is based on the number of remote units 44(1)-44(S) supported by the optical fiber-based DAS 30. It may be desired to change the configuration of the optical fiber-based DAS 30 such that more RIMs 32(1)-32(M) or OIMs 38(1)-38(N) need to be provided in the central unit 34. However, if the RIM chassis 54 or OIM chassis 56 is full, it is not possible to install additional RIMs 32(1)-32(M) or OIMs 38(1)-38(N), respectively, without reconfiguring the optical fiber-based DAS 30, such as by providing additional chassis.

No admission is made that any reference cited herein constitutes prior art. Applicant expressly reserves the right to challenge the accuracy and pertinency of any cited documents.

SUMMARY

Embodiments disclosed herein include flexible head-end chassis supporting automatic identification and interconnection of radio interface modules (RIMs) and optical interface modules (OIMs) in an optical fiber-based distributed antenna system (DAS). Related methods and DASs are also disclosed. The flexible head-end chassis is provided as part of head-end equipment in an optical fiber-based DAS. In one embodiment, the flexible head-end chassis includes a plurality of module slots. Each of the module slots is configured to receive either a RIM or an OIM. The flexible head-end chassis includes a backplane configured to be interconnected with a RIM or OIM fully inserted into a module slot of the flexible head-end chassis. When a RIM or OIM is inserted into a module slot of the flexible head-end chassis and interconnected to the backplane, a chassis control system identifies the inserted RIM or OIM to determine which type of module is inserted in the module slot. Based on the identification of the inserted RIM or OIM, the chassis control system interconnects the inserted RIM or OIM to related signal routing circuitry (e.g., combiners and splitters) in the head-end equipment needed for the RIM or OIM to be capable of receiving downlink communications signals and uplink communications signals for processing and distribution in the optical fiber-based DAS. In this manner, the optical fiber-based DAS can easily be configured or reconfigured with different numbers and combinations of RIMs and OIMs, as needed or desired, for the optical fiber-based DAS to support the desired communications services and/or number of remote units.

One embodiment of the disclosure relates to a head-end chassis for an optical fiber-based DAS. The head-end chassis comprises a housing. The head-end chassis also comprises a plurality of module slots disposed in the housing. Each module slot among the plurality of module slots is configured to receive a connected module comprised of a radio interface module (RIM) or an optical interface module (OIM). The head-end chassis also comprises a backplane disposed in the housing. The backplane comprises a plurality of backplane interconnects each associated with a module slot among the plurality of module slots, each backplane interconnect among the plurality of backplane interconnects configured to interconnect with the connected module inserted into the module slot associated with the backplane interconnect. Each backplane interconnect among the plurality of backplane interconnects comprises a backplane downlink input configured to receive an electrical downlink communications signal from a RIM, a backplane downlink output configured to provide an electrical split downlink communications signal to an OIM, a backplane uplink input configured to receive an electrical uplink communications signal from an OIM, and a backplane uplink output configured to provide an electrical split uplink communications signal to a RIM. The backplane also comprises a plurality of combiner downlink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner downlink inputs is configured to receive a plurality of electrical downlink communications signals from a plurality of RIMs, combine the received plurality of electrical downlink communications signals into an electrical combined downlink communications signal, and provide the electrical combined downlink communications signal on a combiner downlink output. The backplane also comprises a downlink splitter comprising a splitter downlink input. The splitter downlink input is configured to receive the electrical combined downlink communications signal from the combiner downlink output, split the received electrical combined downlink communications signal into a plurality of electrical split downlink communications signals, and provide the plurality of electrical split downlink communications signals on a plurality of splitter downlink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The backplane also comprises an uplink combiner comprising a plurality of combiner uplink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner uplink inputs is configured to receive a plurality of electrical uplink communications signals from at least one OIM, combine the received plurality of electrical uplink communications signals into an electrical combined uplink communications signal, and provide the electrical combined uplink communications signal on a combiner uplink output. The backplane also comprises an uplink splitter comprising a splitter uplink input. The splitter uplink input is configured to receive the electrical combined uplink communications signal from the combiner uplink output, split the received electrical combined uplink communications signal into a plurality of electrical split uplink communications signals, and provide the plurality of electrical split uplink communications signals on a plurality of splitter uplink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects.

The backplane also comprises a plurality of downlink switches each configured to selectively couple, in response to a downlink switch selector, either the backplane downlink input of a backplane interconnect connected to a RIM, to a corresponding combiner downlink input among the plurality of combiner downlink inputs to provide the electrical downlink communications signal from the RIM to the downlink combiner; or the backplane downlink output of the backplane interconnect connected to an OIM, to a corresponding splitter downlink output among the plurality of splitter downlink outputs to provide the electrical split downlink communications signal to the OIM. The backplane also comprises a plurality of uplink switches each configured to selectively couple, in response to an uplink switch selector, either the backplane uplink output of a backplane interconnect connected to the RIM, to a corresponding splitter uplink output among the plurality of splitter uplink outputs to provide the electrical split uplink communications signal to the RIM; or the backplane uplink input of the backplane interconnect connected to the OIM, to a corresponding combiner uplink input among the plurality of combiner uplink inputs to provide the electrical uplink communications signal from the OIM to the uplink combiner.

Another embodiment of the disclosure relates to a method for interconnecting a connected module in a head-end chassis with head-end equipment in an optical fiber-based DAS. The method comprises detecting a connection of a connected module comprised of a RIM or an OIM, to a backplane interconnect of a module slot among a plurality of module slots in a head-end chassis. The method also comprises determining if the connected module in the module slot is a RIM or an OIM. If the connected module in the module slot is determined to be a RIM, the method comprises coupling the backplane interconnect connected to the RIM to a downlink combiner. The downlink combiner is configured to receive an electrical downlink communications signal from the RIM, combine the received electrical downlink communications signal into an electrical combined downlink communications signal and provide the electrical combined downlink communications signal to a downlink splitter. The method also comprises coupling the backplane interconnect connected to the RIM to an uplink splitter. The uplink splitter is configured to receive an electrical combined uplink communications signal from an uplink combiner, split the electrical combined uplink communications signal into the plurality of electrical split uplink communications signals, and provide the electrical split uplink communications signal to the RIM. If the connected module in the module slot is determined to be an OIM, the method comprises coupling the backplane interconnect connected to the OIM to a downlink splitter. The downlink splitter is configured to receive the electrical combined downlink communications signal from the downlink combiner, split the received electrical combined downlink communications signal into an electrical split downlink communications signal, and provide the electrical split downlink communications signal to the OIM. The method also comprises coupling the backplane interconnect connected to the OIM to an uplink combiner. The uplink combiner is configured to receive an electrical uplink communications signal from the OIM, combine the received electrical uplink communications signal into the electrical combiner uplink communications signal, and provide the electrical combined uplink communications signal to the uplink splitter.

Another embodiment of the disclosure relates to an optical fiber-based DAS. The optical fiber-based DAS comprises a central unit. The central unit comprises a plurality of RIMs each configured to receive an electrical downlink communications signal and receive an electrical split uplink communications signal from at least one OIM. The central unit also comprises a plurality of OIMs. Each OIM is configured to receive an electrical split downlink communications signal, convert the received electrical split downlink communications signal into an optical split downlink communications signal, distribute the optical split downlink communications signal to a plurality of remote units, receive a plurality of optical uplink communications signals from the plurality of remote units, and convert the received plurality of optical uplink communications signals to a plurality of electrical uplink communications signals. Each of the plurality of remote units is configured to receive the optical split downlink communications signal from the central unit, convert the received optical split downlink communications signal into an electrical split downlink communications signal, distribute the electrical split downlink communications signal to at least one client device, receive an electrical uplink communications signal from the at least one client device, convert the received electrical uplink communications signal into an optical uplink communications signal, and distribute the optical uplink communications signal to the central unit.

The central unit further comprises a head-end chassis. The head-end chassis comprises a housing. The head-end chassis also comprises a plurality of module slots disposed in the housing. Each module slot among the plurality of module slots configured to receive a connected module comprised of a RIM among the plurality of RIMs or an OIM among the plurality of OIMs. The head-end chassis further comprises a backplane disposed in the housing. The backplane comprises a plurality of backplane interconnects each associated with a module slot among the plurality of module slots. Each backplane interconnect among the plurality of backplane interconnects is configured to interconnect with the connected module inserted into the module slot associated with the backplane interconnect. Each backplane interconnect among the plurality of backplane interconnects comprises a backplane downlink input configured to receive the electrical downlink communications signal from a RIM among the plurality of RIMs, a backplane downlink output configured to provide an electrical split downlink communications signal to an OIM among the plurality of OIMs, a backplane uplink input configured to receive an electrical uplink communications signal from the OIM, and a backplane uplink output configured to provide an electrical split uplink communications signal to the RIM. The head-end chassis also comprises a downlink combiner comprising a plurality of combiner downlink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner downlink inputs is configured to receive a plurality of electrical downlink communications signals from the plurality of RIMs, combine the received plurality of electrical downlink communications signals into an electrical combined downlink communications signal, and provide the electrical combined downlink communications signal on a combiner downlink output. The head-end chassis also comprises a downlink splitter comprising a splitter downlink input. The splitter downlink input is configured to receive the electrical combined downlink communications signal from the combiner downlink output, split the received electrical combined downlink communications signal into a plurality of electrical split downlink communications signals, and provide the plurality of electrical split downlink communications signals on a plurality of splitter downlink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The head-end chassis also comprises an uplink combiner comprising a plurality of combiner uplink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects. The plurality of combiner uplink inputs is configured to receive a plurality of electrical uplink communications signals from the plurality of OIMs, combine the received plurality of electrical uplink communications signals into an electrical combined uplink communications signal, and provide the electrical combined uplink communications signal on a combiner uplink output. The head-end chassis also comprises an uplink splitter comprising a splitter uplink input. The splitter uplink input is configured to receive the electrical combined uplink communications signal from the combiner uplink output, split the received electrical combined uplink communications signal into a plurality of electrical split uplink communications signals, and provide the plurality of electrical split uplink communications signals on a plurality of splitter uplink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects.

The head-end chassis also comprises a plurality of downlink switches each configured to selectively couple, in response to a downlink switch selector, either the backplane downlink input of a backplane interconnect connected to a RIM, to a corresponding combiner downlink input among the plurality of combiner downlink inputs to provide the electrical downlink communications signal from the RIM to the downlink combiner; or the backplane downlink output of the backplane interconnect connected to an OIM, to a corresponding splitter downlink output among the plurality of splitter downlink outputs to provide the electrical split downlink communications signal to the OIM. The head-end chassis also comprises a plurality of uplink switches each configured to selectively couple, in response to an uplink switch selector, either the backplane uplink output of a backplane interconnect connected to the RIM, to a corresponding splitter uplink output among the plurality of splitter uplink outputs to provide the electrical split uplink communications signal to the RIM; or the backplane uplink input of the backplane interconnect connected to the OIM, to a corresponding combiner uplink input among the plurality of combiner uplink inputs to provide the electrical uplink communications signal from the OIM to the uplink combiner.

Additional features and advantages will be set forth in the detailed description which follows, and in part, will be readily apparent to those skilled in the art from the description or recognized by practicing the embodiments as described in the written description and claims hereof, as well as the appended drawings.

It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understand the nature and character of the claims.

The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description serve to explain the principles and operation of the various embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an exemplary distributed antenna system (DAS) capable of distributing radio-frequency (RF) communications services to client devices;

FIG. 2 is a schematic diagram of an exemplary optical fiber-based DAS including head-end equipment that includes remote interface modules configured to receive and process electrical communications signals in supported frequency bands and optical interface modules providing an optical interface for the electrical communications signals;

FIG. 3 is a schematic diagram of a flexible head-end chassis in an optical fiber-based DAS, wherein the flexible head-end chassis includes a plurality of module slots each configured to flexibly receive either a radio interface module (RIM) or an optical interface module (OIM), and provide automatic interconnection of the received RIM or OIM in the optical fiber-based DAS;

FIG. 4 is a schematic diagram of an exemplary optical fiber-based DAS employing the flexible head-end chassis in FIG. 3 and illustrating exemplary interconnectivity of RIMs and OIMs through a backplane of the flexible head-end chassis;

FIG. 5 is a schematic diagram illustrating exemplary detail of a flexible head-end chassis configured to be provided in an optical fiber-based DAS, wherein the flexible head-end chassis includes a plurality of module slots each configured to flexibly receive either a RIM or an OIM, and provide automatic interconnection of the received RIM or OIM according to the exemplary interconnectivity of RIMs and OIMs in head-end equipment of the optical fiber-based DAS illustrated in FIG. 4;

FIG. 6 is a schematic diagram illustrating additional exemplary detail of a chassis controller that can be provided in the flexible head-end chassis in FIG. 5 to provide automatic identification and interconnection of received RIMs and OIMs in an optical-fiber based DAS according to the exemplary interconnectivity of RIMs and OIMs in head-end equipment in FIG. 4;

FIG. 7 is a flowchart illustrating an exemplary process of the chassis controller in FIG. 6 automatically identifying and interconnecting a received RIM or OIM in an optical fiber-based DAS according to the exemplary interconnectivity of RIMs and OIMs in head-end equipment in FIG. 4;

FIG. 8 is a partially schematic cut-away diagram of an exemplary building infrastructure in which an optical fiber-based DAS employing a flexible head-end chassis configured to flexibly receive either a RIM or an OIM, and provide automatic interconnection of the received RIM or OIM in the optical fiber-based DAS can be employed; and

FIG. 9 is a schematic diagram of an exemplary representation of a chassis controller for automatically identifying and interconnecting a received RIM or OIM in a flexible head-end chassis for an optical fiber-based DAS, wherein the exemplary computer system is adapted to execute instructions from an exemplary computer readable medium.

DETAILED DESCRIPTION

Various embodiments will be further clarified by the following examples.

Embodiments disclosed herein include flexible head-end chassis supporting automatic identification and interconnection of radio interface modules (RIMs) and optical interface modules (OIMs) in an optical fiber-based distributed antenna system (DAS). Related methods and DASs are also disclosed. The flexible head-end chassis is provided as part of head-end equipment in an optical fiber-based DAS. In one embodiment, the flexible head-end chassis includes a plurality of module slots (e.g., circuit board card slots). Each of the module slots is configured to receive either a RIM or an OIM. The flexible head-end chassis includes a backplane configured to be interconnected with a RIM or OIM fully inserted into a module slot of the flexible head-end chassis. When a RIM or OIM is inserted into a module slot of the flexible head-end chassis and interconnected to the backplane, a chassis control system identifies the inserted RIM or OIM to determine which type of module is inserted in the module slot. Based on the identification of the inserted RIM or OIM, the chassis control system interconnects the inserted RIM or OIM to related signal routing circuitry (e.g., combiners and splitters) in the head-end equipment needed for the RIM or OIM to be capable of receiving downlink communications signals and uplink communications signals for processing and distribution in the optical fiber-based DAS. In this manner, the optical fiber-based DAS can easily be configured or reconfigured with different numbers and combinations of RIMs and OIMs, as needed or desired, for the optical fiber-based DAS to support the desired communications services and/or number of remote units.

In this regard, FIG. 3 is a top view of an exemplary flexible head-end chassis 60 that can be provided in an optical fiber-based DAS. As will be discussed in more detail below, the flexible head-end chassis 60 is configured to be provided as part of head-end equipment in an optical fiber-based DAS in FIG. 4 to support both RIMs and OIMs. As shown in FIG. 3, the flexible head-end chassis 60 includes a housing 62 that includes a plurality of module slots 64(1)-64(Q) each configured to receive a RIM 66 or an OIM 68. The notation “1-Q” indicates that any number of the referenced component, 1-Q, may be provided. In this example, the housing 62 of the flexible head-end chassis 60 has eight (8) module slots 64(1)-64(8) to support any combination of eight RIMs 66 and OIMs 68. A backplane 70 is provided in the rear section 72 of the housing 62. The backplane 70 includes a backplane interconnect 74(1)-74(8),74(Q) for each module slot 64(1)-64(8),64(Q) to support an interconnection with a RIM 66 or OIM 68 fully inserted into a module slot 64(1)-64(Q). In this example, two RIMs 66(1), 66(2) are inserted into module slots 64(7) and 64(8) and interconnected with a backplane interconnects 74(7), 74(8). The RIMs 66(1), 66(2) are configured to receive electrical downlink communications signals 76E-D from outside of a DAS, such as from a base station (not shown). The RIMs 66(1), 66(2) process and distribute the received electrical downlink communications signal 76E-D through the respective backplane interconnects 74(7), 74(8) to the OIMs 68(1)-68(6). The OIMs 68(1)-68(6) provided in the module slots 64(1)-64(6) are interconnected to respective backplane interconnects 74(1)-74(6). The OIMs 68(1)-68(6) are configured to receive electrical downlink communications signals 76E-D from the RIMs 66(1), 66(2) through the backplane 70 and convert the received electrical downlink communications signals 76E-D into optical downlink communications signals 76O-D. The OIMs 68(1)-68(6) are configured to distribute the optical downlink communications signals 76O-D over an optical fiber communications medium 90 to remote units (not shown). The six (6) OIMs 68(1)-68(6) are also configured to receive optical uplink communications signals 76O-U from the remote units, convert the received optical uplink communications signals 76O-U into electrical uplink communications signals 76E-U, and distribute the electrical uplink communications signals 76E-U through the backplane interconnects 74(1)-74(6) to the RIMs 66(1), 66(2).

As will be discussed in more detail below, when a RIM 66 or OIM 68 is inserted into a particular module slot 64 of the flexible head-end chassis 60 in FIG. 3, a chassis control system described below detects which type of module is inserted in the module slot 64. Based on the identification of the inserted RIM 66 or OIM 68 in the module slot 64, the chassis control system configures the backplane interconnect 74 corresponding to the module slot 64 to interconnect the inserted RIM 66 or OIM 68 to related combiners and splitters in the head-end equipment needed for the RIM 66 or OIM 68 to be capable of receiving downlink communications signals 76D and uplink communications signals 76U for processing and distribution in an optical fiber-based DAS. In this manner, an optical fiber-based DAS employing the flexible head-end chassis 60 can easily be configured or reconfigured with different numbers and combinations of RIMs 66 and OIMs 68, as needed or desired, for the optical fiber-based DAS to support the desired communications services and/or number of remote units.

In this regard, FIG. 4 is a schematic diagram of an optical fiber-based DAS 78 employing the flexible head-end chassis 60 in FIG. 3. The flexible head-end chassis 60 can be provided in a central unit of the optical fiber-based DAS 78. FIG. 4 illustrates exemplary interconnectivity of the RIMs 66(1), 66(2) and OIMs 68(1)-68(4) to be provided through the backplane interconnects 74(1)-74(8) (shown in FIG. 3) of the backplane 70 of the flexible head-end chassis 60 to provide the optical fiber-based DAS 78. Note that only four OIMs 68(1)-68(4) are illustrated as being installed in the flexible head-end chassis 60 in FIG. 4 for illustrative purposes. FIGS. 5-7 will be described below to discuss examples of how the flexible head-end chassis 60 can be configured to automatically identify RIMs 66 and OIMs 68 inserted in the flexible head-end chassis 60 and automatically configure the backplane interconnects 74 to accomplish the exemplary interconnectivity illustrated in FIG. 4.

First, with reference to the RIMs 66(1), 66(2) in FIG. 4, the RIMs 66(1), 66(2) inserted in the flexible head-end chassis 60 are shown as interfacing with respective cells 80(1), 80(2) outside of the optical fiber-based DAS 78. For example, cell 80(1) may provide a first electrical downlink communications signal 76E-D(1) to RIM 66(1), and cell 80(2) may provide a second electrical downlink communications signal 76E-D(2) to RIM 66(2). RIM 66(1) may be configured to support a first frequency band supported by cell 80(1), and RIM 66(2) may be configured to support a second frequency band, which may be different than the first frequency band, supported by cell 80(2). The RIMs 66(1), 66(2) are configured to distribute the electrical downlink communications signals 76E-D(1), 76E-D(2) through the optical fiber-based DAS 78 to remote units 82 as the optical downlink communications signals 76O-D. As will be discussed below, the RIMs 66(1), 66(2) also receive electrical uplink communications signals 70E-U(1), 70E-U(2) as a result of the remote units 82 receiving electrical uplink communications signals 76E-U from client devices (not shown), to be distributed to the cells 80(1), 80(2).

With continuing reference to FIG. 4, for the RIMs 66(1), 66(2) inserted in the flexible head-end chassis 60, it is desired in the optical fiber-based DAS 78 to combine the multiple electrical downlink communications signals 76E-D(1), 76E-D(2) in a downlink combiner 84D into an electrical combined downlink communications signal 76E-D(C), which is then split in a downlink splitter 86D into multiple electrical split downlink communications signals 76E-D(S) each to be distributed to the OIMs 68(1)-68(4). To facilitate this interconnectivity in the flexible head-end chassis 60, the backplane interconnects 74(7), 74(8) (shown in FIG. 3) connected to the RIMs 66(1), 66(2) each include a backplane downlink input 88DI(1), 88DI(2) configured to receive the electrical downlink communications signals 76E-D(1), 76E-D(2) from the RIMs 66(1), 66(2). The RIMs 66(1), 66(2) are interconnected to the backplane downlink inputs 88DI(1), 88DI(2) as a result of the RIMs 66(1), 66(2) being interconnected to the backplane 70 when installed in the flexible head-end chassis 60. Note that in this example, all multiple electrical downlink communications signals 76E-D(1), 76E-D(2) are combined into a single electrical combined downlink communications signal 76E-D(C). However, note that the downlink combiner 84D could also be configured to selectively combine electrical downlink communications signals 76E-D(1), 76E-D(2), such as if it is desired to configured the optical fiber-based DAS 78 to different combinations/sectors of electrical downlink communications signals 76E-D to remote units 82.

With continuing reference to FIG. 4, the OIMs 68(1)-68(4) inserted in the flexible head-end chassis 60 are shown as interfacing with the remote units 82. In this example, each OIM 68(1)-68(4) interfaces with up to three remote units 82 over optical fiber communications medium 90. In this example, a separate downlink optical fiber communications medium 90D for distribution of optical downlink communications signals 76-D and a separate uplink optical fiber communications medium 90U for distribution of optical uplink communications signals 76-O is provided, but such is not required. For example, a common optical fiber communication medium could be employed using wave-division multiplexing (WDM). Thus, for example, OIM 68(1) interfaces with three (3) remote units 82(1)(1)-82(1)(3). OIM 68(4) interfaces with three (3) remote units 82(4)(1)-82(4)(3). The OIMs 68(1)-68(4) receive and convert the received electrical split downlink communications signals 76E-D(S), received over respective backplane downlink outputs 88DO(1)-88DO(4) provided in the backplane interconnects 74(1)-74(4) (FIG. 3), as a result of the interconnection of the OIMs 68(1)-68(4) to the backplane 70, to respective optical split downlink communications signals 76O-D(S). The optical split downlink communications signals 76O-D(S) are distributed over the downlink optical fiber communication medium 80D to remote units 82(1)(1)-82(4)(3) in this example. Note that the flexible head-end chassis 60 could alternatively be configured to selectively deliver the optical split downlink communications signals 76O-D(S) to different remote units 82(1)(1)-82(4)(3).

With continuing reference to FIG. 4, the remote units 82(1)(1)-82(4)(3) are each configured to receive electrical uplink communications signals, which are then converted to corresponding optical uplink communications signals 76O-U(1)(1)-76O-U(4)(3) and distributed to respective OIMs 68(1)-68(4) inserted in the flexible head-end chassis 60 over the uplink optical fiber communications medium 90U. The OIMs 68(1)-68(4) convert the received optical uplink communications signals 76O-U(1)(1)-76O-U(4)(3) into corresponding electrical uplink communications signals 76E-U(1)-76E-U(4), which are provided in backplane uplink inputs 88UI(1)-88UI(4) in the backplane interconnects 74(1)-74(4) (FIG. 3) connected to the OIMs 68(1)-68(4) as a result of the interconnection of the OIMs 68(1)-68(4) to the backplane 70. It is also desired in this exemplary optical fiber-based DAS 78 to combine the multiple electrical uplink communications signals 76E-U(1)-76E-U(4) in an uplink combiner 84U into an electrical combined uplink communications signal 76E-U(C), which is then split in an uplink splitter 86U into multiple electrical split uplink communications signals 76E-U(S). Each of the electrical split uplink communications signals 76E-U(S) are distributed over backplane uplink outputs 88UO(1)-88UO(2) as part of the backplane interconnects 74(7), 74(8) (FIG. 3) to the RIMs 66(1), 66(2) as a result of the interconnection of the RIMs 66(1), 66(2) to the backplane 70. The RIMs 66(1), 66(2) are each configured to filter the received electrical split uplink communications signals 76E-U(S) in their supported frequency band into respective electrical uplink communications signals 76E-U(1), 76E-U(2) to be distributed to their respective cells 80(1), 80(2).

Thus in summary, as illustrated in FIG. 4 and described above, each backplane interconnect 74(1)-74(8) (FIG. 3) in the backplane 70 corresponding to a module slot 64(1)-64(8) (FIG. 3) in the flexible head-end chassis 60 contains a backplane downlink input 88DI, a backplane downlink output 88DO, a backplane uplink input 88UI, and a backplane uplink output 88UO to allow for either a RIM 66 or OIM 68 to be flexibly installed in any module slot 64 (FIG. 3). If a RIM 66 is installed in a given module slot 64, backplane downlink input 88DI and backplane uplink output 88UO of the corresponding backplane interconnect 74 are configured to be connected to the installed RIM 66. This is so that the downlink combiner 84D receives electrical downlink communications signals 76E-D from the installed RIM 66, and so that the installed RIM 66 receives the electrical split uplink communications signal 76E-U(S) from the uplink splitter 86U. However, if an OIM 68 is installed in a given module slot 64 instead of a RIM 66, the backplane downlink output 88DO and the backplane uplink input 88UI of the corresponding backplane interconnect 74 are configured to be connected to the installed OIM 68. This is so that the uplink combiner 84U receives the electrical uplink communications signal 76E-U from the installed OIM 68, and so that the installed OIM 68 receives the electrical split downlink communications signal 76E-D(S) from the downlink splitter 86D. In this manner, a RIM 66 or OIM 68 may be installed in any module slot 64 in the flexible head-end chassis 60 and the desired interconnectivity with the backplane 70 and its distribution components to provide the optical fiber-based DAS 78 can be achieved in either case.

FIG. 5 is a schematic diagram illustrating exemplary detail of the flexible head-end chassis 60 to illustrate components that can be provided in the backplane 70 to allow backplane interconnects 74(1)-74(8) to automatically be configured to provide the interconnectivity for either a RIM 66 or an OIM 68, based on whether a RIM 66 or OIM 68 is inserted into a corresponding module slot 64(1)-64(8). Later below with regard to FIGS. 6 and 7, an exemplary chassis control system that can be provided in the backplane 70 is described to identify an installed RIM 66 or OIM 68 in a module slot 64 of the flexible head-end chassis 60. The chassis control system is configured to automatically configure the interconnectivity of a backplane downlink input 88DI, a backplane downlink output 88DO, an backplane uplink input 88UI, and a backplane uplink output 88UO for a given backplane interconnect 74, with regard to the downlink combiner 84D, downlink splitter 86D, uplink combiner 84U, and uplink splitter 86U, to allow for either a RIM 66 or OIM 68 to be flexibly installed in a given, corresponding module slot 64 according to the exemplary interconnectivity provided in FIG. 4.

With reference to FIG. 5, the downlink combiner 84D in the backplane 70 includes combiner downlink inputs 92DI(1)-92DI(8) for each backplane interconnect 74(1)-74(8). The combiner downlink inputs 92DI(1)-92DI(8) are each configured to receive an electrical downlink communications signals 76E-D from a RIM 66 if a RIM 66 is installed in the module slot 64 corresponding to the backplane interconnect 74(1)-74(8). The downlink combiner 84D is configured to combine received plurality of electrical downlink communications signals 76E-D from RIMs 66 installed in any module slots 64(1)-64(8) into the electrical combined downlink communications signal 76E-D(C), and provide the electrical combined downlink communications signal 76E-D(C) on a combiner downlink output 92DO to be provided to the downlink splitter 86D. The downlink splitter 86D in the backplane 70 includes splitter downlink outputs 94DO(1)-94DO(8) for each backplane interconnect 74(1)-74(8). The splitter downlink outputs 94DO(1)-94DO(8) are each configured to provide the electrical split downlink communications signal 76E-D(S) from the combiner downlink output 92DO of the downlink combiner 84D to an OIM 68 if an OIM 68 is installed in the module slot 64 corresponding to the backplane interconnect 74(1)-74(8).

To provide the proper downlink connectivity between the module, whether it is a RIM 66 or OIM 68, inserted in a given module slot 64, a plurality of downlink switches 96(1)-96(8) are provided in the backplane 70 for each backplane interconnect 74(1)-74(8). Each downlink switch 96(1)-96(8) is configured to selectively couple either a respective backplane downlink input 88DI(1)-88DI(8) or a respective backplane downlink output 88DO(1)-88DO(8) to the installed module. If the installed module is a RIM 66, the downlink switch 96 is configured to couple a respective backplane downlink input 88DI to a RIM downlink output 98DO for the downlink combiner 84D to receive the electrical downlink communications signal 76E-D from the RIM 66. However, if the installed module is an OIM 68, the downlink switch 96 is configured to couple a respective backplane downlink output 88DO to an OIM downlink input 100DI to receive the electrical split downlink communications signal 76E-D(S) from the downlink splitter 86D.

To provide the proper uplink connectivity between the module, whether it is a RIM 66 or OIM 68, inserted in a given module slot 64, a plurality of uplink switches 102(1)-102(8) are provided in the backplane 70 for each backplane interconnect 74(1)-74(8). Each uplink switch 102(1)-102(8) is configured to selectively couple either a respective backplane uplink output 88UO(1)-88UO(8) or a respective backplane uplink input 88UI(1)-88UI(8) to the installed module. If the installed module is a RIM 66, the uplink switch 102 is configured to couple a respective backplane uplink output 88UO to a RIM uplink input 98UI, to couple the RIM uplink input 98UI to a splitter uplink output 94UO of the uplink splitter 86U for the uplink splitter 86U, to provide the electrical split uplink communications signal 76E-U(S) from the uplink splitter 86U to the RIM 66. However, if the installed module is an OIM 68, the uplink switch 102 is configured to couple a respective backplane uplink input 88UI to an OIM uplink output 100UO, to couple the OIM uplink output 100UO to a combiner uplink input 92UI of the uplink combiner 84U, for the OIM 68 to provide an electrical uplink communications signal 76E-U to the uplink combiner 84U.

FIG. 6 is a schematic diagram illustrating additional exemplary detail of a chassis control system 103 that can be provided in the flexible head-end chassis 60 in FIG. 5 to provide automatic identification and interconnection of installed RIMs 66 and OIMs 68 in the optical fiber-based DAS 78 according to the exemplary interconnectivity of RIMs 66 and OIMs 68 in head-end equipment in FIG. 4. More specifically, as discussed in more detail below, the chassis control system 103 include a chassis controller 104 that is configured to cause the downlink switches 96(1)-96(8) and the uplink switches 102(1)-102(8) to be set to provide the correct interconnectivity between the installed module and the respective backplane interconnects 74(1)-74(8) based on whether a RIM 66 or OIM 68 is identified as the module inserted into a respective module slot 64(1)-64(8). Only module slots 64(1) and 64(8) are shown in FIG. 6 to simply the illustration and discussion of the exemplary chassis controller 104, but note that such is applicable for the other module slots 64(2)-64(7) as well.

With reference to FIG. 6, the chassis controller 104 is an electronic controller in this example that includes a module ID reader 106 and a switch controller 108. The module ID reader 106 is configured to identify the type of module inserted into each of the module slots 64(1)-64(8). For example, when the OIM 68 was installed in module slot 64(1), as shown in FIG. 6, the module ID reader 106 receives a signal on a module ID input 109(1) provided as part of the backplane interconnect 74(1) that interconnected with a module ID pin 110 on the OIM 68 when installed. The module ID reader 106 is able to determine that the OIM 68 is installed in module slot 64(1) based on the module ID signal 114 generated by the OIM 68 on module ID pin 110 coupled to the module ID input 109(1). The module ID reader 106 provides an indication of the detected OIM 68 in module slot 64(1) to the chassis controller 104. Similarly, when the RIM 66 was installed in module slot 64(8), as shown in FIG. 6, the module ID reader 106 receives a module ID signal 114 on a module ID input 109(8) provided as part of the backplane interconnect 74(8) that interconnected with a module ID pin 112 on the RIM 66 when installed. The module ID reader 106 is able to determine that the RIM 66 is installed in module slot 64(8) based on the module ID signal 114 generated by the RIM 66 on module ID pin 112 coupled to the module ID input 109(8). The module ID reader 106 provides an indication of the detected RIM 66 in module slot 64(8) to the chassis controller 104. As non-limiting examples, the activation of the module ID reader 106 to detect the module ID signal 114 may be poll driven or interrupt driven.

With continuing reference to FIG. 6, when the chassis controller 104 receives an indication of an installed module in a module slot 64 from the module ID reader 106 and the type of module installed in the module slot 64, the chassis controller 104 is configured to set the downlink and uplink switches 96, 102. The chassis controller 104 is configured to set the downlink and uplink switches 96, 102 corresponding to the module slot 64 with the newly installed module to provide the interconnectivity for the installed module based on whether the installed module is a RIM 66 or OIM 68. In this regard, in this example, the chassis control system 103 includes the switch controller 108. The switch controller 108 is configured to provide respective downlink switch selectors 105D(1)-105D(8) to each of the plurality of downlink switches 96(1)-96(8), and uplink switch selectors 105U(1)-105U(8) to each of the plurality of uplink switches 102(1)-102(8). As discussed above, if an installed module in a module slot 64 is a RIM 66, the chassis controller 104 is configured to cause the switch controller 108 to generate the downlink switch selector 105D corresponding to the module slot 64 to cause the downlink switch 96 corresponding to the module slot 64 with the installed RIM 66 to couple the backplane downlink input 88DI of the corresponding backplane interconnect 74 (FIG. 5) to the corresponding combiner downlink input 92DI. The chassis controller 104 is also configured to cause the switch controller 108 to generate the uplink switch selector 105U to cause the uplink switch 102 corresponding to the module slot 64 with the installed RIM 66 to couple the backplane uplink output 88UO of the corresponding backplane interconnect 74 (FIG. 5) with the installed RIM 66 to the corresponding splitter uplink output 94UO.

With continuing reference to FIG. 6, if an installed module in a module slot 64 is an OIM 68 instead of a RIM 66, the chassis controller 104 is configured to cause the switch controller 108 to generate the downlink switch selector 105D to cause the downlink switch 96 corresponding to the module slot 64 with the installed OIM 68 to couple the backplane downlink output 88DO of the corresponding backplane interconnect 74 (FIG. 5) to the corresponding splitter downlink output 94DO. The chassis controller 104 is also configured to cause the switch controller 108 to generate the uplink switch selector 105U to cause the uplink switch 102 corresponding to the module slot 64 with the installed OIM 68 to couple the backplane uplink input 88UI of the corresponding backplane interconnect 74 (FIG. 5) with the installed OIM 68 to the corresponding combiner uplink input 92UI.

FIG. 7 is a flowchart illustrating an exemplary process of the chassis controller 104 in FIG. 6 automatically identifying and interconnecting a received RIM 66 or OIM 68 in the flexible head-end chassis 60 in the optical fiber-based DAS 78 according to the exemplary interconnectivity in FIG. 4. In this regard, as illustrated in FIG. 7, after the flexible head-end chassis 60 is powered up (block 120), the chassis controller 104 reads the module ID for each module slot 64 in the flexible head-end chassis 60 (block 122). For each module slot 64, the chassis controller 104 determines if the module slot 64 has a RIM 66 installed, an OIM 68 installed, or no module installed (block 124). If the current module slot 64 is determined to have an installed RIM 66, as discussed above, the chassis controller 104 is configured to cause the switch controller 108 to generate the downlink switch selector 105D corresponding to the module slot 64 to cause the downlink switch 96 corresponding to the module slot 64 with the installed RIM 66 to couple the backplane downlink input 88DI of the corresponding backplane interconnect 74 to the corresponding combiner downlink input 92DI of the downlink combiner 84D (block 126). The chassis controller 104 is also configured to cause the switch controller 108 to generate the uplink switch selector 105U to cause the uplink switch 102 corresponding to the module slot 64 with the installed RIM 66 to couple the backplane uplink output 88UO of the corresponding backplane interconnect 74 with the installed RIM 66 to the corresponding splitter uplink output 94UO of the uplink splitter 86U (block 128).

With continuing reference to FIG. 7, the process continues by the chassis controller 104 reading the module slots 64 (block 130) to determine if a new module has been installed in the module slot 64 (block 132). If no new module has been installed in the module slot 64, the chassis controller 104 incurs a delay (block 134) before again determining if any new modules have been installed in any of the module slots 64 (block 130).

With continuing reference to FIG. 7, if current module slot 64 is determined to have an installed OIM 68 in block 124, as discussed above, the chassis controller 104 is configured to cause the switch controller 108 to generate the downlink switch selector 105D to cause the downlink switch 96 corresponding to the module slot 64 with the installed OIM 68 to couple the backplane downlink output 88DO of the corresponding backplane interconnect 74 to the corresponding splitter downlink output 94DO of the downlink splitter 86D (block 136). The chassis controller 104 is also configured to cause the switch controller 108 to generate the uplink switch selector 105U to cause the uplink switch 102 corresponding to the module slot 64 with the installed OIM 68 to couple the backplane uplink input 88UI of the corresponding backplane interconnect 74 with the installed OIM 68 to the corresponding combiner uplink input 92UI of the uplink combiner 84U (block 138). The process in blocks 130, 132, and 134 described above is carried out by the chassis controller 104 thereafter.

With continuing reference to FIG. 7, if current module slot 64 is determined to not have any installed module, in the example process in FIG. 7, the chassis controller 104 is configured to configure the downlink switch 96 and the uplink switch 102 corresponding to the backplane interconnect 74 for the module slot 64 as if a RIM 66 were installed. In this regard, the chassis controller 104 carries out the tasks in blocks 140 and 142, which are the same as tasks in blocks 126 and 128, respectively, in this example. Alternatively, the chassis controller 104 could be configured to treat a module slot 64 without an installed module as if an OIM 68 were installed in the module slot 64. In this alternative scenario, the chassis controller 104 would perform tasks in blocks 136 and 138 described above as if the module slot 64 has an installed OIM 68, in response to detection of no module installed in the module slot 64.

The flexible head-end chassis 60 for supporting the RIMs 66 and OIMs 68 provided in an optical fiber-based DAS 78 and automatically identifying and interconnecting a received RIM 66 or OIM 68, may be provided in an optical fiber-based DAS 150 in an indoor environment, as illustrated in FIG. 8. In this regard, FIG. 8 is a partially schematic cut-away diagram of a building infrastructure 152 employing a flexible head-end chassis having feature(s) like those described above. The building infrastructure 152 in this embodiment includes a first (ground) floor 154(1), a second floor 154(2), and a third floor 154(3). The floors 154(1)-154(3) are serviced by the central unit 156 to provide the antenna coverage areas 158 in the building infrastructure 152. The flexible head-end chassis 60 is provided as part of the central unit 156. The central unit 156 is communicatively coupled to the base station 160 to receive electrical downlink communications signals 76E-D from the base station 160. The central unit 156 is communicatively coupled to the remote units 162 to receive the electrical uplink communications signals 76E-U from the remote units 162. The electrical downlink and uplink communications signals 76E-D, 76E-U communicated between the central unit 156 and the remote units 162 are carried over a riser cable 164. The riser cable 164 may be routed through interconnect units (ICUs) 166(1)-166(3) dedicated to each floor 154(1)-154(3) that route the electrical downlink and uplink communications signals 76E-D, 76E-U to the remote units 162 and also provide power to the remote units 162 via array cables 168.

In one embodiment, the central unit 156 is configured to support up to twelve (12) RIMs 66. Each RIM 66 can be designed to support a particular type of radio source or range of radio sources (i.e., frequencies) to provide flexibility in configuring the central unit 156 and the optical fiber-based DAS 150 to support the desired radio sources. For example, one RIM 66 may be configured to support the Personal Communication Services (PCS) radio band. Another RIM 66 may be configured to support the 700 MHz radio band. In this example, by inclusion of these RIMs 66, the central unit 156 could be configured to support and distribute communications signals on both PCS and LTE 700 radio bands, as an example. RIMs 66 may be provided in the central unit 156 that support any frequency bands desired, including but not limited to the US Cellular band, Personal Communication Services (PCS) band, Advanced Wireless Services (AWS) band, 700 MHz band, Global System for Mobile communications (GSM) 900, GSM 1800, and Universal Mobile Telecommunication System (UMTS). The RIMs 66 may also be provided in the central unit 156 that support any wireless technologies desired, including but not limited to Code Division Multiple Access (CDMA), CDMA200, 1×RTT, Evolution-Data Only (EV-DO), UNITS, High-speed Packet Access (HSPA), GSM, General Packet Radio Services (GPRS), Enhanced Data GSM Environment (EDGE), Time Division Multiple Access (TDMA), Long Term Evolution (LTE), iDEN, and Cellular Digital Packet Data (CDPD).

The RIMs 66 may be provided in the central unit 156 that support any frequencies desired, including but not limited to US FCC and Industry Canada frequencies (824-849 MHz on uplink and 869-894 MHz on downlink), US FCC and Industry Canada frequencies (1850-1915 MHz on uplink and 1930-1995 MHz on downlink), US FCC and Industry Canada frequencies (1710-1755 MHz on uplink and 2110-2155 MHz on downlink), US FCC frequencies (698-716 MHz and 776-787 MHz on uplink and 728-746 MHz on downlink), EU R & TTE frequencies (880-915 MHz on uplink and 925-960 MHz on downlink), EU R & TTE frequencies (1710-1785 MHz on uplink and 1805-1880 MHz on downlink), EU R & TTE frequencies (1920-1980 MHz on uplink and 2110-2170 MHz on downlink), US FCC frequencies (806-824 MHz on uplink and 851-869 MHz on downlink), US FCC frequencies (896-901 MHz on uplink and 929-941 MHz on downlink), US FCC frequencies (793-805 MHz on uplink and 763-775 MHz on downlink), and US FCC frequencies (2495-2690 MHz on uplink and downlink).

FIG. 9 is a schematic diagram representation of additional detail illustrating a computer system 170 that could be employed in the chassis control system 103 or the chassis controller 104 discussed with regard to FIG. 6 above for automatically identifying and interconnecting a received RIM 66 or OIM 68 in the flexible head-end chassis 60 in an optical fiber-based DAS, including optical fiber-based DAS 78, 150 discussed above. In this regard, the computer system 170 is adapted to execute instructions from an exemplary computer-readable medium to perform these and/or any of the functions or processing described herein.

In this regard, the computer system 170 in FIG. 9 may include a set of instructions that may be executed to automatically identify and interconnect a received RIM 66 or OIM 68 in the flexible head-end chassis 60. The computer system 170 may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. While only a single device is illustrated, the term “device” shall also be taken to include any collection of devices that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. The computer system 170 may be a circuit or circuits included in an electronic board card, such as, a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

The exemplary computer system 170 in this embodiment includes a processing device or processor 172, a main memory 174 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc.), and a static memory 176 (e.g., flash memory, static random access memory (SRAM), etc.), which may communicate with each other via a data bus 178. Alternatively, the processor 172 may be connected to the main memory 174 and/or static memory 176 directly or via some other connectivity means. The processor 172 may be a controller, and the main memory 174 or static memory 176 may be any type of memory.

The processor 172 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More particularly, the processor 172 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or other processors implementing a combination of instruction sets. The processor 172 is configured to execute processing logic in instructions for performing the operations and steps discussed herein.

The computer system 170 may further include a network interface device 180. The computer system 170 also may or may not include an input 182, configured to receive input and selections to be communicated to the computer system 170 when executing instructions. The computer system 170 also may or may not include an output 184, including but not limited to a display, a video display unit (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device (e.g., a keyboard), and/or a cursor control device (e.g., a mouse).

The computer system 170 may or may not include a data storage device that includes instructions 188 stored in a computer-readable medium 190. The instructions 188 may also reside, completely or at least partially, within the main memory 174 and/or within the processor 172 during execution thereof by the computer system 170, the main memory 174 and the processor 172 also constituting computer-readable medium. The instructions 188 may further be transmitted or received over a network 192 via the network interface device 180.

While the computer-readable medium 190 is shown in an exemplary embodiment to be a single medium, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term “computer-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.

Unless specifically stated otherwise and as apparent from the previous discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing,” “computing,” “determining,” “displaying,” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data and memories represented as physical (electronic) quantities within the computer system's registers into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatuses to perform the required method steps. The required structure for a variety of these systems will appear from the description above. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the embodiments as described herein.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a controller may be a processor. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The embodiments disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

It is also noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those of skill in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, that may be references throughout the above description, may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that any particular order be inferred.

It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and their equivalents.

Claims

1. A chassis for a distributed antenna system (DAS), comprising: a housing;a plurality of module slots disposed in the housing, each module slot among the plurality of module slots configured to receive a connected module comprised of a radio interface circuit or an optical interface circuit;a backplane disposed in the housing, the backplane comprising: a plurality of backplane interconnects each associated with a circuit slot among a plurality of circuit slots, each backplane interconnect among the plurality of backplane interconnects configured to interconnect with a connected circuit inserted into the circuit slot associated with the backplane interconnect; each backplane interconnect among the plurality of backplane interconnects comprises: a backplane downlink input configured to receive an electrical downlink communications signal from a radio interface circuit;a backplane downlink output configured to couple an electrical split downlink communications signal to an optical interface circuit;a backplane uplink input configured to receive an electrical uplink communications signal from an optical interface circuit; anda backplane uplink output configured to couple an electrical split uplink communications signal to a radio interface circuit;a plurality of first downlink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects, the plurality of first downlink inputs configured to receive a plurality of electrical downlink communications signals from a plurality of radio interface circuits;a second downlink input configured to couple a plurality of electrical split downlink communications signals on a plurality of first downlink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects;a plurality of first uplink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects, the plurality of first uplink inputs configured to receive a plurality of electrical uplink communications signals from at least one optical interface circuit;a second uplink input configured to couple a plurality of electrical split uplink communications signals on a plurality of first uplink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects;a plurality of downlink switches each configured to selectively couple, in response to a downlink switch selector, either the backplane downlink input of a backplane interconnect connected to a radio interface circuit, to a corresponding first downlink input among the plurality of first downlink inputs to couple the electrical downlink communications signal from the radio interface circuit, or the backplane downlink output of the backplane interconnect connected to an optical interface circuit, to a corresponding first downlink output among the plurality of first downlink outputs to couple the electrical split downlink communications signal to the optical interface circuit; anda plurality of uplink switches each configured to selectively couple, in response to an uplink switch selector, either the backplane uplink output of a backplane interconnect connected to the radio interface circuit, to a corresponding first uplink output among the plurality of first uplink outputs to couple the electrical split uplink communications signal to the radio interface circuit, or the backplane uplink input of the backplane interconnect connected to the optical interface circuit, to a corresponding first uplink input among the plurality of first uplink inputs to couple the electrical uplink communications signal from the optical interface circuit.
2. The chassis of claim 1, further comprising a chassis control system configured to: provide the downlink switch selector to each of the plurality of downlink switches; andprovide the uplink switch selector to each of the plurality of uplink switches.
3. The chassis of claim 2, wherein the chassis control system comprises: a chassis controller; anda switch controller configured to provide the downlink switch selector to each of the plurality of downlink switches, and provide the uplink switch selector to each of the plurality of uplink switches;the chassis controller configured to: detect a connection of the connected circuit to a backplane interconnect of a circuit slot in the plurality of circuit slots;determine if the connected circuit is a radio interface circuit or an optical interface circuit;if the connected circuit is a radio interface circuit, the chassis controller configured to: instruct the switch controller to: generate the downlink switch selector to cause a downlink switch corresponding to the circuit slot to couple the backplane downlink input of the backplane interconnect connected to the radio interface circuit, to the corresponding first downlink input; andgenerate the uplink switch selector to cause an uplink switch corresponding to the module slot to couple the backplane uplink output of the backplane interconnect connected to the radio interface circuit, to a corresponding second uplink output;if the connected circuit is an optical interface circuit, the chassis controller configured to: instruct the switch controller to: generate the downlink switch selector to cause the downlink switch corresponding to the module slot to couple the backplane downlink output of the backplane interconnect connected to the optical interface circuit, to the corresponding first downlink output; andgenerate the uplink switch selector to cause the uplink switch corresponding to the module slot to couple the backplane uplink input of the backplane interconnect connected to the optical interface circuit to the corresponding first uplink input.
4. The chassis of claim 3, wherein the chassis controller is configured to automatically: detect the connection of the connected circuit to a backplane interconnect of a circuit slot in the plurality of circuit slots;determine if the connected circuit is a radio interface circuit or an optical interface circuit; andinstruct the switch controller to generate the downlink switch selector and the uplink switch selector.
5. The chassis of claim 3, wherein the chassis controller is configured to: detect the connection of the connected circuit to a backplane interconnect of a circuit slot in the plurality of circuit slots and determine if the connected circuit is a radio interface circuit or an optical interface circuit for each circuit slot among the plurality of circuit slots; andinstruct the switch controller to generate the downlink switch selector and the uplink switch selector corresponding to each circuit slot among the plurality of circuit slots, based on whether the connected circuit is a radio interface circuit or an optical interface circuit.
6. The chassis of claim 3, wherein each backplane interconnect among the plurality of backplane interconnects further comprises a circuit ID input configured to interconnect with a circuit ID output from a radio interface circuit or optical interface circuit inserted into the circuit slot associated with the backplane interconnect; the chassis controller configured to: detect the connection of the connected circuit to the backplane interconnect of the circuit slot in the plurality of circuit slots based on a circuit ID signal received from the circuit ID output on the circuit ID input; anddetermine if the connected circuit is a radio interface circuit or an optical interface circuit based on the circuit ID signal received on the circuit ID input.
7. The chassis of claim 3, wherein the chassis control is further configured to: determine if a backplane interconnect for a circuit slot among the plurality of circuit slots is unconnected; andif the backplane interconnect for the circuit slot is unconnected, the chassis controller is further configured to instruct the switch controller to: generate the downlink switch selector to cause the downlink switch corresponding to the circuit slot to couple the backplane downlink input of the unconnected backplane interconnect to the corresponding first downlink input; andgenerate the uplink switch selector to cause the uplink switch corresponding to the circuit slot to couple the backplane uplink output of the unconnected backplane interconnect to the corresponding first uplink output.
8. The chassis of claim 3, wherein the chassis control is further configured to: determine if a backplane interconnect for a circuit slot among the plurality of circuit slots is unconnected; andif the backplane interconnect for the circuit slot is unconnected, the chassis controller is further configured to instruct the switch controller to: generate the downlink switch selector to cause the downlink switch corresponding to the circuit slot to couple the backplane downlink output of the unconnected backplane interconnect to the corresponding first downlink output; andgenerate the uplink switch selector to cause the uplink switch corresponding to the circuit slot to couple the backplane uplink input of the unconnected backplane interconnect to the corresponding first uplink input.
9. The chassis of claim 1 provided in an indoor optical fiber-based DAS.
10. The chassis of claim 1, further comprising: a downlink combiner comprising the plurality of first downlink inputs;a downlink splitter comprising the second downlink input, the downlink splitter configured to receive an electrical combined downlink communications signal from a combiner downlink output, split the received electrical combined downlink communications signal into a plurality of electrical split downlink communications signals;an uplink combiner comprising the plurality of first uplink inputs and configured to combine the received plurality of electrical uplink communications signals into an electrical combined uplink communications signal; andan uplink splitter comprising the second uplink input and configured to split the received electrical combined uplink communications signal into a plurality of electrical split uplink communications signals.
11. A distributed antenna system (DAS), comprising: a central unit, comprising: a plurality of radio interface circuits each configured to: receive an electrical downlink communications signal;receive an electrical split uplink communications signal from at least one optical interface circuit;a plurality of optical interface circuits each configured to: receive an electrical split downlink communications signal;convert the received electrical split downlink communications signal into an optical split downlink communications signal;distribute the optical split downlink communications signal to a plurality of remote units;receive a plurality of optical uplink communications signals from the plurality of remote units;convert the received plurality of optical uplink communications signals to a plurality of electrical uplink communications signals;each of the plurality of remote units configured to: receive the optical split downlink communications signal from the central unit;convert the received optical split downlink communications signal into an electrical split downlink communications signal;distribute the electrical split downlink communications signal to at least one client device;receive an electrical uplink communications signal from the at least one client device;convert the received electrical uplink communications signal into an optical uplink communications signal; anddistribute the optical uplink communications signal to the central unit;the central unit further comprising a head-end chassis, comprising: a housing;a plurality of module slots disposed in the housing, each module slot among the plurality of module slots configured to receive a connected module comprised of a radio interface circuit or an optical interface circuit;a backplane disposed in the housing, the backplane comprising: a plurality of backplane interconnects each associated with a circuit slot among a plurality of circuit slots, each backplane interconnect among the plurality of backplane interconnects configured to interconnect with a connected circuit inserted into the circuit slot associated with the backplane interconnect;each backplane interconnect among the plurality of backplane interconnects comprises: a backplane downlink input configured to receive an electrical downlink communications signal from a radio interface circuit;a backplane downlink output configured to couple an electrical split downlink communications signal to an optical interface circuit;a backplane uplink input configured to receive an electrical uplink communications signal from an optical interface circuit; anda backplane uplink output configured to couple an electrical split uplink communications signal to a radio interface circuit;a plurality of first downlink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects, the plurality of first downlink inputs configured to receive a plurality of electrical downlink communications signals from a plurality of radio interface circuits;a second downlink input configured to couple a plurality of electrical split downlink communications signals on a plurality of first downlink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects;a plurality of first uplink inputs each corresponding to a backplane interconnect among the plurality of backplane interconnects, the plurality of first uplink inputs configured to receive a plurality of electrical uplink communications signals from at least one optical interface circuit;a second uplink input configured to couple a plurality of electrical split uplink communications signals on a plurality of first uplink outputs each corresponding to a backplane interconnect among the plurality of backplane interconnects;a plurality of downlink switches each configured to selectively couple, in response to a downlink switch selector, either the backplane downlink input of a backplane interconnect connected to a radio interface circuit, to a corresponding first downlink input among the plurality of first downlink inputs to couple the electrical downlink communications signal from the radio interface circuit, or the backplane downlink output of the backplane interconnect connected to an optical interface circuit, to a corresponding first downlink output among the plurality of first downlink outputs to couple the electrical split downlink communications signal to the optical interface circuit; anda plurality of uplink switches each configured to selectively couple, in response to an uplink switch selector, either the backplane uplink output of a backplane interconnect connected to the radio interface circuit, to a corresponding first uplink output among the plurality of first uplink outputs to couple the electrical split uplink communications signal to the radio interface circuit, or the backplane uplink input of the backplane interconnect connected to the optical interface circuit, to a corresponding first uplink input among the plurality of first uplink inputs to couple the electrical uplink communications signal from the optical interface circuit.
12. The DAS of claim 11, further comprising a chassis control system configured to: provide the downlink switch selector to each of the plurality of downlink switches; andprovide the uplink switch selector to each of the plurality of uplink switches;wherein the chassis control system comprises: a chassis controller; anda switch controller configured to provide the downlink switch selector to each of the plurality of downlink switches, and provide the uplink switch selector to each of the plurality of uplink switches;the chassis controller configured to: detect a connection of the connected circuit to a backplane interconnect of a circuit slot in the plurality of circuit slots;determine if the connected circuit is a radio interface circuit or an optical interface circuit;if the connected circuit is a radio interface circuit, the chassis controller configured to: instruct the switch controller to: generate the downlink switch selector to cause a downlink switch corresponding to the circuit slot to couple the backplane downlink input of the backplane interconnect connected to the radio interface circuit, to the corresponding first downlink input; and generate the uplink switch selector to cause an uplink switch corresponding to the module slot to couple the backplane uplink output of the backplane interconnect connected to the radio interface circuit, to a corresponding second uplink output;if the connected circuit is an optical interface circuit, the chassis controller configured to: instruct the switch controller to: generate the downlink switch selector to cause the downlink switch corresponding to the module slot to couple the backplane downlink output of the backplane interconnect connected to the optical interface circuit, to the corresponding first downlink output; and generate the uplink switch selector to cause the uplink switch corresponding to the module slot to couple the backplane uplink input of the backplane interconnect connected to the optical interface circuit to the corresponding first uplink input.
13. The DAS of claim 12, wherein the chassis controller is configured to automatically: detect the connection of the connected circuit to a backplane interconnect of a circuit slot in the plurality of circuit slots;determine if the connected circuit is a radio interface circuit or an optical interface circuit; andinstruct the switch controller to generate the downlink switch selector and the uplink switch selector.
14. The DAS of claim 12, wherein the chassis controller is configured to: detect the connection of the connected circuit to a backplane interconnect of a circuit slot in the plurality of circuit slots and determine if the connected circuit is a radio interface circuit or an optical interface circuit for each circuit slot among the plurality of circuit slots; andinstruct the switch controller to generate the downlink switch selector and the uplink switch selector corresponding to each circuit slot among the plurality of circuit slots, based on whether the connected circuit is a radio interface circuit or an optical interface circuit.
15. The DAS of claim 12, wherein each backplane interconnect among the plurality of backplane interconnects further comprises a circuit ID input configured to interconnect with a circuit ID output from a radio interface circuit or optical interface circuit inserted into the circuit slot associated with the backplane interconnect; the chassis controller configured to: detect the connection of the connected circuit to the backplane interconnect of the circuit slot in the plurality of circuit slots based on a circuit ID signal received from the circuit ID output on the circuit ID input; anddetermine if the connected circuit is a radio interface circuit or an optical interface circuit based on the circuit ID signal received on the circuit ID input.
16. The DAS of claim 12, wherein the chassis control is further configured to: determine if a backplane interconnect for a circuit slot among the plurality of circuit slots is unconnected; andif the backplane interconnect for the circuit slot is unconnected, the chassis controller is further configured to instruct the switch controller to: generate the downlink switch selector to cause the downlink switch corresponding to the circuit slot to couple the backplane downlink input of the unconnected backplane interconnect to the corresponding first downlink input; andgenerate the uplink switch selector to cause the uplink switch corresponding to the circuit slot to couple the backplane uplink output of the unconnected backplane interconnect to the corresponding first uplink output.
17. The DAS of claim 12, wherein the chassis control is further configured to: determine if a backplane interconnect for a circuit slot among the plurality of circuit slots is unconnected; andif the backplane interconnect for the circuit slot is unconnected, the chassis controller is further configured to instruct the switch controller to: generate the downlink switch selector to cause the downlink switch corresponding to the circuit slot to couple the backplane downlink output of the unconnected backplane interconnect to the corresponding first downlink output; andgenerate the uplink switch selector to cause the uplink switch corresponding to the circuit slot to couple the backplane uplink input of the unconnected backplane interconnect to the corresponding first uplink input.
18. The DAS of claim 11, wherein the chassis further comprises: a downlink combiner comprising the plurality of first downlink inputs;a downlink splitter comprising the second downlink input, the downlink splitter configured to receive an electrical combined downlink communications signal from a combiner downlink output, split the received electrical combined downlink communications signal into a plurality of electrical split downlink communications signals;an uplink combiner comprising the plurality of first uplink inputs and configured to combine the received plurality of electrical uplink communications signals into an electrical combined uplink communications signal; andan uplink splitter comprising the second uplink input and configured to split the received electrical combined uplink communications signal into a plurality of electrical split uplink communications signals.

PRIORITY APPLICATION

This is a continuation of U.S. patent application Ser. No. 14/855,896 filed on Sep. 16, 2015, which claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application No. 62/054,543, filed on Sep. 24, 2014, the contents of which are relied upon and incorporated herein by reference in their entireties.

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Related Publications (1)

	Number	Date	Country
	20170149506 A1	May 2017	US

Provisional Applications (1)

	Number	Date	Country
	62054543	Sep 2014	US

Continuations (1)

	Number	Date	Country
Parent	14855896	Sep 2015	US
Child	15427119		US

Flexible head-end chassis supporting automatic identification and interconnection of radio interface modules and optical interface modules in an optical fiber-based distributed antenna system (DAS)

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