Claims
- 1. A multi-channel redundancy block generation circuit for n logical data channels, comprising:
- an input bus selectively couplable to each of said n logical data channels for receiving a plurality of related data blocks and at least one associated redundancy block;
- a memory device partitioned into n data storage locations for said related data blocks and said at least one associated redundancy block for each of said n logical data channels;
- a multi-input redundancy block generator coupled to said memory device for receiving selected ones of said data blocks and at least one associated redundancy block corresponding to each of said n logical data channels in a timewise interleaved manner and generating updated redundancy block information in response thereto;
- a switching circuit coupled to said input bus and to said memory device for interleaving said related data blocks and said at least one associated redundancy block from a different one of said n logical data channels for input to said multi-input redundancy block generator; and
- an output bus operatively coupled to an output of said multi-input redundancy block generator for receiving said updated redundancy block information and applying said updated redundancy block information to a corresponding one of said n logical data channels.
- 2. The multi-channel redundancy block generation circuit of claim 1 wherein said memory device comprises n first-in/first-out registers.
- 3. The multi-channel redundancy block generation circuit of claim 1 wherein said memory device comprises a randomly accessible memory device having n non-overlapping data storage locations.
- 4. The multi-channel redundancy block generation circuit of claim 1 wherein said switching circuit further selectively applies said related data blocks and said at least one associated redundancy block for a selected one of said n logical data channels to said memory device.
- 5. The multi-channel redundancy block generation circuit of claim 1 wherein outputs from a particular one of said n data storage locations in said memory device corresponding to said selected one of said n logical data channels are output to said multi-input redundancy block generator.
- 6. The multi-channel redundancy block generation circuit of claim 1 further comprising:
- an addressing circuit coupled to an address input of said memory device for directing said plurality of related data blocks and said at least one associated redundancy block for each of said n logical data channels to a corresponding one of said n data storage locations.
- 7. The multi-channel redundancy block generation circuit of claim 6 wherein said addressing circuit further comprises:
- a counter associated with each of said plurality of logical data channels for providing a count to said addressing circuit indicating a pointer to a portion of one of said n data storage locations corresponding to a selected one of said n logical data channels.
- 8. The multi-channel redundancy block generation circuit of claim 6 wherein said counter is programmable with a block size of said data blocks on each of said n logical data channels.
- 9. The multi-channel redundancy block generation circuit of claim 1 wherein said switching circuit is configured for randomly interleaving said related data blocks and said at least one associated redundancy block from a different one of said n logical data channels for input to said multi-input redundancy block generator.
- 10. The multi-channel redundancy block generation circuit of claim 1 wherein said multi-input redundancy block generator is a two input redundancy block generator.
Parent Case Info
This is a continuation of application Ser. No. 08/555,331 (now U.S. Pat. No. 5,675,726), filed Nov. 8, 1995, which is a continuation of application Ser. No. 08/402,963, filed Mar. 10, 1995 (now U.S. Pat. No. 5,469,566), which is a continuation of application Ser. No. 07/851,428, filed Mar. 12, 1992 (now abandoned).
US Referenced Citations (35)
Foreign Referenced Citations (1)
Number |
Date |
Country |
9113404 |
Sep 1991 |
WOX |
Continuations (3)
|
Number |
Date |
Country |
Parent |
555331 |
Nov 1995 |
|
Parent |
402963 |
Mar 1995 |
|
Parent |
851428 |
Mar 1992 |
|