A memory cell array, such as a Dynamic Random Access Memory (DRAM) array, can be partitioned or divided (logically or physically) into memory banks or row segments. The memory banks or row segments contain groups of memory cells that are arranged in a row-column format. For example, a memory array arranged by rows or word lines (WL) and columns or bit lines (BL) can be further divided by grouping or partitioning a plurality of word lines into row segments. In such an arrangement, a group of bits of word lines that are provided along a column or bit line are segmented from another group of bits of word lines that are provided along the same column or bit line.
Each memory cell is structured for storing digital information in the form of a “1” or a “0” bit. To write (i.e., store) a bit into a memory cell, a memory address having portions identifying the cell's row (the “row address”) and column (the “column address”) is provided to address circuitry in the semiconductor memory to activate the memory cell, and the bit is then supplied to the memory cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the memory cell is again activated using the cell's memory address, and the bit is then output from the memory cell.
When the memory cells are arranged in row segments or banks, the binary memory address can include a row segment or bank address. For example, if the memory contains a plurality of memory cells arranged together in a segment or block of rows or word lines, the address can include additional bits identifying the row segment or block of the memory cell array to be accessed.
Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing or faulty memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows (word lines), redundant columns (bit lines), and/or segmented column lines (segmented bit lines).
When a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell's WL address is permanently stored (typically in predecoded form) on a chip on which the semiconductor memory is fabricated by programming a nonvolatile element (e.g., a group of fuses, antifuses, or FLASH memory cells) on the chip. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a WL address that corresponds to the WL address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant WL to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell's WL has the same WL address, every cell in the failing cell's WL, both operative and failing, is replaced by a redundant memory cell in the redundant row.
Similarly, when a redundant column (bit line) needs to be repaired in the semiconductor memory, the failing cell column is permanently stored (typically in predecoded form) on the chip by programming a nonvolatile element on the chip. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of the memory cell data identified by the received memory address. As every memory cell in the failing cell column has the same column address, every cell in the failing cell column, both operative and failing, is replaced by a redundant memory cell in the redundant column.
In current redundancy schemes, a defect in one row segment is corrected by using redundant locations either in the same row segment (intrablock) or in an adjacent row segment (interblock). This type of redundancy offers more options for repairing defects. However, in this type of scheme, the row or WL repair and the column or column select line (CSL) repair are interdependent which results in limited flexibility in repair.
According to the current redundancy scheme, the CSL repair region is selected during WL activation based on the row address. If an addressed WL needs to be replaced (i.e., it contains a faulty memory cell), it can be replaced with a WL within the same block or row segment (i.e., intrablock repair) or outside the block (i.e., interblock repair). If the CSL in the original row segment needs repair, a corresponding or identical CSL repair is made in the row segment into which the defective WL is replaced. The CSL replacement occurs whether or not the CSL in the new row segment is defective. Alternatively, it is possible that the CSL in the original row segment is operative while the CSL in the new row segment is defective. Since the CSL repair region is determined by the row address of the WL requiring repair, the defective CSL in the new row segment will not be repaired, and therefore a fault will occur. This arrangement limits the repair options. For such reasons, the current redundancy scheme limits flexibility in repair.
As a result of the above-described replacement scheme, operative memory cells can be unnecessarily replaced, thereby reducing overall memory yield during production.
A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in second memory block with a spare memory cell in the second memory block, based on a decoded address of a first memory block.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements and which together with a detailed description set forth herein are incorporated in and form part of the specification, serve to further illustrate various exemplary embodiments and to explain various principles and advantages in accordance with this application.
The following exemplary embodiments and aspects thereof are described and illustrated in conjunction with structures and methods that are meant to be exemplary and illustrative, and not limiting in scope. In the following description, numerous specific details are set forth, such as representative memory addresses, to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the embodiments described in this application can be practiced without such specific, but exemplary, details. In other embodiments, circuits have been shown in block diagram form in order not to obscure the embodiments described in this application in unnecessary detail. For the most part, details concerning timing considerations, the arrangement of sense amplifiers, transistors, storage capacitors, data lines and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the embodiments described in this application.
It is contemplated that memory repair schemes can be used to repair defective memory cells in DRAMs. However, the memory repair schemes described herein can also be used in SDRAM (synchronous DRAM), SRAM (static random access memory), as well as stand alone RAM (random access memory) and other types of memory devices.
The memory cells are arranged by word lines (WL) and columns or bit lines (BL), thereby forming a memory cell array. In this application, the terms “word line” or “WL” will be used interchangeably with the term “row.” The term “column” is interchangeable with the expression “bit line” or “BL.”
An embodiment of the present application is concerned with a WL and column repair scheme in which the column repair is independent of WL repair, such as where column select lines (CSL) are replaced by redundant column select lines.
In the redundant replacement schemes described in the embodiments of this application, the column select line repair region need not be selected based on the original row address, but is selected based on the select signal of the row segment actually used for WL repair or replacement. As a result, overall memory yield is increased, as CSL repair is based on the physical, not logical, address of a row segment address, so that good or properly functioning memory cells are not wasted.
Representative word lines are identified by reference numerals 125 and 140, and representative columns are identified by reference numerals 25 and 40. The word lines extend vertically, while the columns extend horizontally. Columns 25, 40 can extend horizontally across the entire memory array. In
The column select lines are divided by row segments 3, 2, 1 and 0. For example, 3-25 and 3-40 identify column select lines in row segment 3, while 2-25 and 2-40 identify CSLs in row segment 2. The areas in
A defective memory cell MX in a column segment associated with a CSL (i.e., defective CSL) can be replaced or remapped by replacing the defective CSL with a redundant CSL. Each time a defective CSL is addressed, a redundancy circuit, which can be included in a CSL repair circuit, activates the spare element or redundant CSL selected by an address programmed into the nonvolatile storage device or element (i.e., fuses) during production testing. A defective WL containing a defective or failing memory cell MX can be replaced by spare elements (i.e., redundant word lines) either within the same row segment or in any other row segment. The replacement of a WL in the same row segment (i.e., row segment 3, row segment 2, row segment 1 or row segment 0) is an intrablock (intrasegment) repair, while a replacement between different row segments is called an interblock (intersegment) repair. An interblock repair is shown by arrow A in
In the case of an interblock WL repair, where the WL, column and CSL addresses are used interdependently, errors can occur. This can happen when a WL replacement utilizes a redundant WL in a row segment having a CSL that needs to be replaced. For example, when making a repair for a row segment (i.e., row segment 3), the CSL repair region or segment is based on the row segment address and is active only for that row segment (i.e., row segment 3). If the redundant WL and thus active WL is in row segment 2 (i.e., by remapping or repair), the CSL repair will not take place when the WL and CSL repairs are interrelated or the addresses used therefor are interrelated. This is because the CSL repair circuit does not decode a match in row segment 2. This will cause fails that appear to be in row segment 3.
In other words, during a combined WL and CSL interdependent repair, a defective WL 125 is repaired via an interblock repair from one row segment into another row segment (i.e., from row segment 3 into row segment 2, as shown by arrow A). In this situation, CSL 2-25, which corresponds to a logically defective CSL 3-25, is replaced by a spare element or redundant CSL 2-40. This type of repair can cause the spare or redundant CSL 2-40 to become activated in segment 2 even when the original CSL 2-25 was passing (good). Also, in such an interdependent repair, the entire memory will fail if the spare or redundant CSL 2-40 in row segment 2 has a fail.
For example, assuming that a column select line repair was necessary for CSL 3-25 in row segment 3 and the CSL repair is based on the row segment address for row segment 3, an interdependent repair will cause the CSL replacement identified by arrow B to occur in row segment 2. Namely, the CSL corresponding to CSL 3-25 (i.e., 2-25) would be replaced by the CSL 2-40 in row segment 2. However, if a memory cell (MC) associated with corresponding CSL 2-40 was defective or faulty, the memory would fail. On the other hand, if the corresponding MC in a column segment corresponding to CSL 2-25 was a good or properly functioning memory cell, the CSL replacement identified by arrow B would not be necessary and such an interdependent repair or replacement would defeat the function of replacing bad or faulty bits or memory cells with good or properly functioning memory cells and prohibit the use of CSL 2-40 for another CSL repair, thereby limiting yield.
A flexible word line/column select line repair scheme provides for defective word line repair via interblock repair (arrow A), where any CSL repairs necessary along the redundant WL 140 will be based on the fact that the active (physical) WL is in row segment 2, rather than the fact that the logical address for WL 125 is in row segment 3. With the arrangement according to this embodiment of the application, no precaution is needed when deriving the repair solution, and the repair flexibility is not limited.
In the arrangement shown in
Decoded row segment signals from the row segment decoder 102 are sent to the CSL repair circuit 104 and are used as CSL repair region select signals. In this embodiment, the CSL repair is decoupled (separated) from the WL repair. This can be termed a “decoupled interblock repair.” No timing penalty is incurred with this arrangement, since the tRCD (row (WL) addressed to column address delay) is sufficiently long to transmit the decoded row segment information back into the CSL repair circuit 104.
In the decoupled interblock repair, a defective WL in a first row segment (first memory block) is repaired with a redundant WL in a second row segment (second memory block), the row segment address associated with the defective WL is decoded, and the decoded row segment address is used for CSL repair in the second row segment. The repair is decoupled in that the row segment address is decoded and the decoded address is used for CSL repair. In contrast, in the interdependent repair an address received by the memory is used for redundancy repair based on the initial relationship between the row segment address, row address and column address of the address received. Namely, in the interdependent repair the redundancy repair in the second row segment is based on the initial (logical) address of the first row segment, not the physical (decoded) address of the second row segment as described herein for the decoupled interblock repair.
A flow diagram illustrating a procedure for repairing a memory array according to an embodiment of this application is shown in
In the semiconductor device 100 shown in
The row segment decoder 102 includes a redundancy circuit having storage device 102A and comparison unit 102B, as shown in
As mentioned above, in addition to a WL address (i.e., X) supplied to the row decoder 102, a row segment address (i.e. XA) that can identify the logical level of the most significant bits of the row segment address is also supplied to the row segment decoder 102. The row segment address XA identifies the logical level of the most significant bits of the row segment address, for which a binary address can be “00” or “01” or “10” or “11” and which are used to identify row segments 0, 1, 2 and 3. In other words, the XA address can be the most significant bits of the ADR.
The row segment decoder 102 decodes the row segment address corresponding to the redundant WL used for the WL repair. The decoded row segment address and the column address are supplied to the CLS repair circuit 104 (CLS repair region decoder), which supplies the column address to the column decoder 105. The column decoder 105 activates the column address in response to the column address (i.e., Y) received from the CSL repair circuit 104.
In the embodiment shown in
The CSL repair circuit 104 can include a redundancy circuit. The redundancy circuit can include storage device 104A and comparison unit 104B, as shown in
For example, if the stored row segment address and column address for a particular CSL were not stored in the CSL repair circuit 104 (namely, the CSL is not defective), the CSL repair circuit 104 will not replace the CSL. Thus, if CSL 2-25 corresponding to redundant WL 140 was not defective (the addresses for CSL 2-25 were not stored in the CSL repair circuit 104), it would not be replaced. On the other hand, if CSL 2-25 was defective (the addresses for CSL 2-25 are stored in the CSL repair circuit 104), it would be replaced by, for example, redundant CSL 2-40. The arrangements of this embodiment of the present application assure that only defective CSLs are repaired or replaced. In addition, the arrangements of this embodiment of the present application allow greater flexibility for WL and CSL repair, because good and properly functioning CSLs are not replaced, thereby freeing unused redundant CSLs for replacement of other defective CSLs.
In view of the above, it will be seen that the embodiments of the invention are achieved and other advantageous results attained. As various changes could be made in the above constructions without departing from the scope of the flexible redundancy replacement scheme for memory described in this application, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.