Claims
- 1. A system under the control of a general-purpose computer for converting digital media assets into wire data packets for transmission to a client, the assets being stored on a digital media storage device comprising:
an input interface for retrieving digital media asset data from the storage device; a media buffer for receiving the digital media asset data from the storage interface, a programmable logic device adapted to transfer the digital media asset data from the input interface to the media buffer, to process the digital media asset data from the media buffer, and to generate wire data packets, a network interface coupled to the device and adapted to transmit the wire data packets to the client, and a general-purpose interface coupled to the device and adapted to receive control information from the general-purpose computer for storage in the media buffer and to enable the device to communicate with the general-purpose computer.
- 2. The system of claim 1, wherein the media buffer is further adapted to store control blocks comprising packet header formatting instructions and digital media asset payload information, and the programmable logic device is further adapted to generate packet headers from the instructions.
- 3. The system of claim 2, wherein the digital media asset payload information comprises a pointer to the digital media asset data.
- 4. The system of claim 2, wherein the digital media asset payload information comprises the digital media asset data.
- 5. The system of claim 1, wherein the programmable logic device is a field programmable gate array.
- 6. The system of claim 1, wherein the network interface comprises a Gigabit Ethernet interface.
- 7. The system of claim 1, wherein the data generation rate is greater than or equal to the data transmission rate, the programmable logic device data reception rate is greater than or equal to the data generation rate, and the media buffer data reception rate is greater than or equal to the programmable logic device data reception rate.
- 8. The system of claim 1, wherein two or more programmable logic devices cooperatively increase the data transmission rate of the system.
- 9. The system of claim 1, wherein the programmable logic device comprises an MPEG-2 stitching engine for targeted ad insertion.
- 10. The system of claim 1, wherein the programmable logic device is further adapted to encrypt the data stream thereby increasing the quality of content security.
- 11. A secure method of providing an upgrade package for changing the logic in a field programmable gate array used as an engine for streaming digital media, comprising:
encrypting the upgrade package, compressing the upgrade package, distributing the upgrade package, decompressing the upgrade package, decrypting the upgrade package, loading the package into the field programmable gate array, supplying a key to the field programmable gate array for decrypting the upgrade package, and rebooting the field programmable gate array, thereby installing the upgrade package.
- 12. A method of streaming a block of a digital media asset across a digital network using a hardware engine, comprising:
transferring the block of the asset into a media buffer; writing wire packet generation control instructions into the media buffer; fragmenting the block into one or more data packets; generating packet headers for a packet in accordance with the instructions; calculating a checksum for the packet; transmitting the packet onto the network; and repeating the generating, calculating, and transmitting steps until all the data packets have been transmitted.
- 13. The method of claim 12, further comprising the steps of:
receiving a message to process the instructions; and sending a message that the block has been sent.
- 14. A method for designing a streaming media hardware engine, comprising:
(a) identifying one or more components that comprise the hardware engine; (b) designing a last component having a fully saturated output bandwidth greater than or equal to the required bandwidth of the hardware engine; (c) calculating the input bandwidth required to fully saturate the designed component; (d) designing an adjacent preceding component having a fully saturated output bandwidth greater than or equal to the input bandwidth calculated in step (c); and recursively repeating steps (c) and (d) for remaining components identified in step (a).
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims benefit of U.S. provisional patent application serial No. 60/374,086, filed Apr. 19, 2002, entitled “Flexible Streaming Hardware,” U.S. provisional patent application serial No. 60/374,090, filed Apr. 19, 2002, entitled “Hybrid Streaming Platform,” U.S. provisional patent application serial No. 60/374,037, filed Apr. 19, 2002, entitled “Optimized Digital Media Delivery Engine,” and U.S. patent application Ser. No. 60/373,991, filed Apr. 19, 2002, entitled “Optimized Digital Media Delivery Engine,” each of which is hereby incorporated by reference for each of its teachings and embodiments.
Provisional Applications (4)
|
Number |
Date |
Country |
|
60374086 |
Apr 2002 |
US |
|
60374090 |
Apr 2002 |
US |
|
60373991 |
Apr 2002 |
US |
|
60374037 |
Apr 2002 |
US |