Patent Application
20250103072
The present disclosure generally relates to reference voltage generator circuits of the bandgap type and, in particular, a bandgap reference voltage generator circuit formed using only bipolar transistors to address flicker noise concerns and including a compensation circuit configured to compensate for bipolar base current effects.
Reference is made to
The current mirroring circuit 12 is formed by p-channel metal oxide semiconductor field effect transistor (MOSFET) devices M1, M2 and M3. The source terminals of transistors M1, M2 and M3 are coupled, preferably connected, to the supply node Vdd. The gate terminals of transistors M1, M2 and M3 are coupled, preferably connected, to each other and biased by a voltage Vout to generate mirrored currents. The drain terminal of transistor M1 outputs a first mirrored current, the drain terminal of transistor M2 outputs a second mirrored current, and the drain terminal of transistor M3 outputs a third mirrored current. The third mirrored current output from the drain terminal of transistor M3 is applied across resistor R3 to generate the bandgap reference voltage Vbg at an output node of the circuit 10. Resistor R3 has a first terminal coupled, preferably connected, to the drain of transistor M3 at the output node and a second terminal coupled, preferably connected, to the ground node Gnd.
The bandgap core circuit 14 includes a differential amplifier circuit 16, for example comprising an operational amplifier (OP-AMP), configured in a current control feedback loop that generates the bias voltage Vout which controls generation of the mirrored currents by the transistors M1, M2 and M3. The non-inverting (+) input of the differential amplifier circuit 16 receives a voltage V+ at the drain of the transistor M1 and the inverting (−) input of the differential amplifier circuit 16 receives a voltage V− at the drain of the transistor M2. The bandgap core circuit 14 further includes PNP bipolar transistors Q1 and Q2. The collector terminals of transistors Q1 and Q2 are coupled, preferably connected, to the ground node Gnd. The base terminals of transistors Q1 and Q2 are coupled, preferably connected, to each other and to the ground node Gnd. The transistors Q1 and Q2 of the bandgap core circuit 14 are thus each connected in diode-configuration. The emitter terminal of transistor Q1 is coupled, preferably connected, to an intermediate node 18. The emitter terminal of transistor Q2 is coupled, preferably connected, to the drain of transistor M2 at the inverting (−) input of the differential amplifier circuit 16. A resistor R1 has a first terminal coupled, preferably connected, to the intermediate node 18 and a second terminal coupled, preferably connected, to the drain of transistor M1 at the non-inverting (+) input of the differential amplifier circuit 16. A first resistor R2 has a first terminal coupled, preferably connected, to the drain of transistor M1 at the non-inverting (+) input of the differential amplifier circuit 16 and a second terminal coupled, preferably connected, to the ground node Gnd. A second resistor R2 has a first terminal coupled, preferably connected, to the emitter of transistor Q2 at the inverting (−) input of the differential amplifier circuit 16 and a second terminal coupled, preferably connected, to the ground node Gnd.
As an example, the differential amplifier circuit 16 includes a differential pair 20 of input transistors M5, M6 coupled to a current mirror load circuit 22 formed by transistors M7, M8. The input transistors M5, M6 are n-channel MOSFETs. The load transistors M7, M8 are p-channel MOSFETs. The common source terminals of the transistors M5 and M6 are coupled, preferably connected, to a tail current source 20 connected to the ground node Gnd. The gate terminal of input transistor M5 (at the non-inverting (+) input) receives the voltage V+ at drain of the transistor M1 and the gate terminal of the input transistor M6 (at the inverting (−) input) receives the voltage V− at drain of the transistor M2. The drain terminal of input transistor M5 is coupled, preferably connected to the drain and gate terminals of the load transistor M7. The drain terminal of input transistor M6 is coupled, preferably connected to the drain terminal of the load transistor M8 at the output of the amplifier. The gate terminals of the transistors M7, M8 are coupled, preferably connected, to each other. The transistor M7 is connected in diode-configuration. The output voltage Vout of the differential amplifier circuit 16 is generated at the common drain terminals of transistors M6, M8 and is a function of the difference between the voltages V+ and V−, and the magnitudes of the first, second and third mirrored currents at the drains of transistors M1, M2 and M3 is a function of the voltage Vout.
The principle of operation of the circuit 10 is to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage, and then add those voltage in a scaled proportion to achieve a cancelation of the positive and negative temperature coefficients.
The generating of the PTAT component uses the difference in base to emitter voltages (VBE) between two forward bias voltages having different current densities (m) using transistors Q1 and Q2. The voltage across resistor R1 is then PTAT in nature:
The current flowing through the resistor R2 is CTAT:
The output bandgap voltage Vbg can be expressed as follows:
The operating point of the circuit 10 can accordingly be scaled by setting of the resistances for resistors R2 and R3, and the temperature coefficient can be adjusted by setting of the resistances for resistors R1 and R2.
There is a recognized problem with the circuit 10. The MOSFETs M5, M6, M7 and M8 introduce flicker (1/f) noise which can perturb the output voltage Vbg. This is a concern when the output voltage Vbg provides a reference voltage for a noise sensitive circuit (like an analog-to-digital converter (ADC)).
To address the issue of flicker noise, there is a teaching in the art to use a chopper technique. See, for example, U.S. Patent Application Publication No. 2010/0295529 and U.S. Pat. No. 10,983,547 (both incorporated herein by reference). However, there are a number of drawbacks associated with the use of the chopper technique including the need for more complicated circuitry and a stable (for example, external) clock source to control the switching operations.
In an embodiment, a circuit comprises: a bandgap voltage generator circuit formed using only bipolar transistors, wherein the bandgap voltage generator circuit includes an output node at which a bandgap reference voltage is generated and a transconductance amplifier circuit in a current control feedback loop having a differential input which receives a base current; and a compensation current sink circuit configured to sink a compensation current from the output node corresponding to the base current at the differential input of the transconductance amplifier.
In an embodiment, a circuit comprising: a current mirroring circuit including a first bipolar transistor, a second bipolar transistor and a third bipolar transistor, wherein an output voltage is generated at an output node in response to a third mirrored current output by the third bipolar transistor; a bandgap core circuit including: a fourth bipolar transistor and fifth bipolar transistor coupled, respectively, to the first and second bipolar transistors and configured to use a difference in base to emitter voltages of the fourth and fifth bipolar transistors to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage from first and second mirrored currents output by the first and second bipolar transistors, respectively; and a transconductance amplification circuit having a differential input coupled, respectively, to the first and second bipolar transistors to receive a base current, and an output coupled to apply a bias current to base terminals of the first, second and third bipolar transistors; and a current sink circuit configured to sink a compensation current from the output node corresponding to the base current at the differential input of the transconductance amplification circuit.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.
Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.
In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “rear”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., unless specified otherwise, it is referred to the orientation of the drawings.
Reference is now made to
The current mirroring circuit 112 is formed by PNP bipolar transistors QA, QB and QC. The emitter terminals of transistors QA, QB and QC are coupled, preferably connected, to the supply node Vdd. The base terminals of transistors QA, QB and QC are coupled, preferably connected, to each other and biased by a bias current Ibias to generate mirrored currents. The collector terminal of transistor QA outputs a first mirrored current, the collector terminal of transistor QB outputs a second mirrored current, and the collector terminal of transistor QC outputs a third mirrored current. The third mirrored current output from the collector terminal of transistor QC is applied across resistor R3 to generate the bandgap reference voltage Vbg at an output node 134 of the circuit 110. Resistor R3 has a first terminal coupled, preferably connected, to the collector of transistor QC at the output node 134 and a second terminal coupled, preferably connected, to the ground node Gnd.
The bandgap core circuit 114 includes a differential operational transconductance amplifier (OTA) circuit 116 configured in a current control feedback loop that generates an output current Iout which controls generation of the mirrored currents by the transistors QA, QB and QC. The non-inverting (+) input of the differential OTA circuit 116 receives a voltage V+ at the collector of the transistor QA and the inverting (−) input of the differential OTA circuit 116 receives a voltage V− at the collector of the transistor QB. The bandgap core circuit 114 further includes PNP bipolar transistors Q1 and Q2. The collector terminals of transistors Q1 and Q2 are coupled, preferably connected, to a virtual ground node 150. The base terminals of transistors Q1 and Q2 are coupled, preferably connected, to each other and to the virtual ground node 150. The transistors Q1 and Q2 of the bandgap core circuit 114 are thus each connected in diode-configuration. The emitter terminal of transistor Q1 is coupled, preferably connected, to an intermediate node 118. The emitter terminal of transistor Q2 is coupled, preferably connected, to the collector of transistor QB at the inverting (−) input of the differential OTA circuit 116. A resistor R1 has a first terminal coupled, preferably connected, to the intermediate node 18 and a second terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 116. A first resistor R2 has a first terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 116 and a second terminal coupled, preferably connected, to the virtual ground node 150. A second resistor R2 has a first terminal coupled, preferably connected, to the emitter of transistor Q2 at the inverting (−) input of the differential OTA circuit 116 and a second terminal coupled, preferably connected, to the virtual ground node 150.
A resistor Rshift has a first terminal coupled, preferably connected, to the virtual ground node 150 and a second terminal coupled, preferably connected, to a circuit ground node Gnd. It will be noted that in an alternative implementation, the resistor Rshift may be omitted and the virtual ground node 150 and ground node Gnd would then be the same node. This alternative implementation is indicated in
The differential OTA circuit 116 includes a differential pair 120 of input transistors Q5, Q6 coupled to a current mirror load circuit 122 formed by transistors Q7, Q8. The input transistors Q5, Q6 are NPN bipolar transistors. The load transistors Q7, Q8 are PNP bipolar transistors. The common emitter terminals of the transistors Q5 and Q6 are coupled, preferably connected, to a tail current source 124 connected to the ground node Gnd. The base terminal of input transistor Q5 (at the non-inverting (+) input) receives the voltage V+ at collector of the transistor QA (as well as a base current Ib) and the base terminal of the input transistor Q6 (at the inverting (−) input) receives the voltage V− at collector of the transistor QB (as well as a base current Ib). The collector terminal of input transistor Q5 is coupled, preferably connected to the collector and base terminals of the load transistor Q7. The collector terminal of input transistor Q6 is coupled, preferably connected to the collector terminal of the load transistor Q8 at the output of the amplifier. The base terminals of the transistors Q7, Q8 are coupled, preferably connected, to each other. The transistor Q7 is connected in diode-configuration. The output current Iout of the differential OTA circuit 116 generated at the common collector terminals of transistors Q6 and Q8 is a function of the difference between the voltages V+ and V−. A stabilization capacitor Cs has a first terminal coupled, preferably connected, to the common collector terminals of transistors Q6 and Q8 and a second terminal coupled, preferably connected, to the ground node Gnd.
The use of an OTA amplifier 116 formed by bipolar transistor devices, as opposed to the differential amplifier 16 formed by MOSFET devices in
The current sink circuit 115 replicates one-half of the differential OTA circuit 116 with a bipolar PNP transistor QD (matching the transistor Q7), an NPN transistor QE (matching the transistor Q5), and a current source 140 (corresponding to the tail current source 124 but with a different current magnitude). The emitter terminal of transistor QD is coupled, preferably connected, to the supply node Vdd. The collector and base terminals of transistor QD are coupled, preferably connected, to each other at intermediate node 142. The transistor QD is connected in diode-configuration. The collector terminal of transistor QE is coupled, preferably connected, to intermediate node 142. The base terminal of transistor QE is coupled, preferably connected, to the output node 134 and is biased by the compensation current Ib′ corresponding to the base current Ib at the pair of transistors 120 in amplifier 116. The emitter terminal of transistor QE is coupled, preferably connected, to current source 140 connected to the ground node Gnd. Because the current sink circuit 115 replicates only one-half of the differential OTA circuit 116, the current source 140 sinks a current Is with a magnitude that is one-half the magnitude of the current 2 Is sunk by the current source 124.
Since the amplifier 116 is of the OTA-type, it cannot effectively drive a resistive load (i.e., it cannot sink with current Iout a current with a magnitude of 3 Ib from the connected bases of the transistors QA, QB and QC) without introducing a significant offset to the amplifier input. To address this issue, the bandgap core circuit 114 further includes a current buffer circuit 130. The output current Iout is buffered by the current buffer circuit 130 to generate the bias current Ibias. The magnitude of the first, second and third mirrored currents at the collectors of transistors QA, QB and QC is a function of the bias current Ibias.
The current buffer circuit 130 comprises a first follower circuit formed by a first transistor T1 having a control terminal coupled, preferably connected, to receive the amplifier output current Iout, a reference terminal coupled, preferably connected, to the ground node Gnd and a follower terminal coupled, preferably connected to receive a first source current Isrc generated by a first current source 150 coupled to the supply node Vdd. The current buffer circuit 130 further comprises a second follower circuit formed by a second transistor T2 having a control terminal coupled, preferably connected, to the follower terminal of the transistor T1, a reference terminal coupled, preferably connected, to the supply node Vdd and a follower terminal coupled, preferably connected to receive a sink current Isnk generated by a second current source 152 coupled to the ground node Gnd. The bias current Ibias is generated at the follower terminal of the transistor T2.
In a preferred implementation as shown in
The use of first and second follower circuits in the current buffer circuit 130 makes it possible to maintain approximately the same voltage at the collector terminals of transistors Q7, Q8 in order to guarantee the linear operation of transistor Q8 in generating the current Iout and thus avoid any early differential effect.
In the implementation which uses the resistor Rshift, the resistance of the resistor Rshift is selected as a function of the mirrored first and second currents (in transistors QA and QB) and the base current Ib so that the voltage drop across the resistor is equal or substantially equal (within design tolerances) to the voltage drop across the current source 124 in the amplifier 116.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
