Patent Application
20080258789
The present invention contains subject matter related to Japanese Patent Application JP 2006-331477 filed with the Japan Patent Office on Dec. 8, 2006, the entire contents of which being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the invention relates to a semiconductor integrated circuit capable of controlling part of the power being supplied to its flip-flops.
2. Description of the Related Art
MTCMOS (multi-threshold-voltage complementary metal oxide semiconductor) technology has been known as a way to save power in semiconductor integrated circuits. The circuit blocks to which the MTCMOS technology is applied include functional blocks with low thresholds for operating on low voltages and switches for shutting down leak currents in a standby state.
Illustratively, as shown in
If the power to all cells is stopped, the data held by flip-flop cells and latch cells will be lost. If these cells are each implemented as a non-MTCMOS functional block 920, then the data held therein is retained but logic gates 921 and 922 in the non-MTCMOS functional block 920 are powered continuously even while the MTCMOS switch 931 is being disconnected. This arrangement thus defeats the power-saving feature originally targeted by the MTCMOS technology.
In an attempt to bypass the difficulty above, MTCMOS flip-flops and MTCMOS latches have been proposed to make up a minimum of non-MTCMOS elements that keep data held intact in each cell. A similar technique involves having master flip-flops constituted by low-threshold transistors and slave flip-flops by high-threshold transistors that remain active in standby mode, thereby averting erasure of stored data (e.g., see Japanese Patent Laid-Open No. Hei 11-284493, with reference to FIG. 4).
However, if part of each flip-flop is made up of MTCMOS elements, it is difficult to regulate the timings between control signals on the one hand, and a data input signal and a clock signal on the other hand for the MTCMOS switch. Specifically, where the slave flip-flop is to hold data in standby mode, the master flip-flop could erroneously fetch the next data input signal when the clock signal is stopped or again activated. The timings need to be controlled adequately to prevent such a flip-flop malfunction. The controls involved thus make it difficult to utilize the MTCMOS technology in designing ASICs (application specific integrated circuits).
The present invention has been made in view of the above circumstances and provides arrangements for making the timing adjustments easier in partially stopping the supply of power to flip-flops.
In carrying out the present invention and according to one embodiment thereof, there is provided a flip-flop including: a clock supply circuit configured to output a clock signal alternating between a first state and a second state when a sleep signal is inactive, and to fix the clock signal in the first state when the sleep signal is active; a first holding circuit configured to fetch an input signal while the clock signal is indicating the first state, and to hold the input signal while the clock signal is indicating the second state; a second holding circuit configured to fetch a first signal output by the first holding circuit while the clock signal is indicating the second state, and to hold the first signal while the clock signal is indicating the first state; an input switching circuit configured to supply as the input signal a second signal output by the second holding circuit when a hold signal is active, and to supply an external signal as the input signal when the hold signal is inactive; and a power supply control circuit configured to supply power to the first holding circuit and the input switching circuit when a power supply control signal is active, and not to supply power to the first holding circuit and the input switching circuit when the power supply control signal is inactive. The flip-flop according to this embodiment of the present invention allows the second holding circuit to hold the signal while the first holding circuit and input switching circuit are not being powered, and to feed the signal back to the first holding circuit when the hold signal is active. With this embodiment, the power supply control circuit may be practiced preferably in the form of an MTCMOS switch.
Preferably, the flip-flop of the embodiment above may further include a clearing circuit configured to clear the signal held by the second holding circuit when a clear signal is active, or a preset circuit configured to preset the signal held by the second holding circuit when a preset signal is active. This preferred variation of the present invention allows the signal held by the second holding circuit to be set in the desired state. In another preferred structure of the invention, the clearing circuit may not clear the signal held by the second holding circuit or the preset circuit may not preset the signal held by the second holding circuit when an inhibit signal is active, regardless of what state the clear signal is or the preset signal is in.
According to another embodiment of the present invention, there is provided a flip-flop including: a clock supply circuit configured to output a clock signal alternating between a first state and a second state when a sleep signal is inactive, and to fix the clock signal in the first state when the sleep signal is active; a first holding circuit configured to fetch an input signal while the clock signal is indicating the first state, and to hold the input signal while the clock signal is indicating the second state; a second holding circuit configured to fetch a first signal output by the first holding circuit while the clock signal is indicating the second state, and to hold the first signal while the clock signal is indicating the first state; an input switching circuit configured to supply as the input signal a second signal output by the second holding circuit either when a hold signal is active or when an enable signal is inactive, and to supply an external signal as the input signal both when the hold signal is inactive and when the enable signal is active; and a power supply control circuit configured to supply power to the first holding circuit and the input switching circuit when a power supply control signal is active, and not to supply power to the first holding circuit and the input switching circuit when the power supply control signal is inactive. The flip-flop according to this embodiment of the present invention allows the second holding circuit to hold the signal while the first holding circuit and input switching circuit are not being powered, and to feed the signal back to the first holding circuit when the hold signal is active or the enable signal is inactive.
According to a further embodiment of the present invention, there is provided a flip-flop including: a clock supply circuit configured to output a clock signal alternating between a first state and a second state when a sleep signal is inactive, and to fix the clock signal in the first state when the sleep signal is active; a first holding circuit configured to fetch an input signal while the clock signal is indicating the first state, and to hold the input signal while the clock signal is indicating the second state; a second holding circuit configured to fetch a first signal output by the first holding circuit while the clock signal is indicating the second state, and to hold the first signal while the clock signal is indicating the first state; an input switching circuit configured to supply a scan-in signal as the input signal when a scan mode signal indicates that scan mode is in effect, to supply as the input signal a second signal output by the second holding circuit both when the scan mode signal indicates that scan mode is not in effect and when a hold signal is active, and to supply an external signal as the input signal when the hold signal is inactive; and a power supply control circuit configured to supply power to the first holding circuit and the input switching circuit when a power supply control signal is active, and not to supply power to the first holding circuit and the input switching circuit when the power supply control signal is inactive. A scan path is thus formed in the flip-flop according to the above embodiment wherein the second holding circuit is allowed to hold the signal while the first holding circuit and input switching circuit are not being powered and to feed the signal back to the first holding circuit in a suitably timed manner.
According to an even further embodiment of the present invention, there is provided a semiconductor integrated circuit including: a clock supply circuit configured to output a clock signal alternating between a first state and a second state when a sleep signal is inactive, and to fix the clock signal in the first state when the sleep signal is active; a first holding circuit configured to fetch an input signal while the clock signal is indicating the first state, and to hold the input signal while the clock signal is indicating the second state; a second holding circuit configured to fetch a first signal output by the first holding circuit while the clock signal is indicating the second state, and to hold the first signal while the clock signal is indicating the first state; an input switching circuit configured to supply as the input signal a second signal output by the second holding circuit when a hold signal is active, and to supply an external signal as the input signal when the hold signal is inactive; a power supply control circuit configured to supply power to the first holding circuit and the input switching circuit when a power supply control signal is active, and not to supply power to the first holding circuit and the input switching circuit when the power supply control signal is inactive; and a flip-flop control circuit configured to set the power supply control signal not to be active only when at least the sleep signal is active, and to set the power supply control signal to be active only when at least the hold signal is active. The semiconductor integrated circuit according to the embodiment above of the present invention allows the second holding circuit to hold the signal while the first holding circuit and input switching circuit are not being powered and to feed the signal back to the first holding circuit when the hold signal is active.
The present invention, when embodied illustratively as outlined above, makes it appreciably easier to adjust the timings for stopping in part the supply of power to flip-flops.
Further advantages of the present invention will become apparent upon a reading of the following description and appended drawings in which:
Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
In a non-MTCMOS functional block 920, logic gates 921 and 922 are connected to the power supply line VDD (902) and ground line VSS (901). Thus the supply of power is not cut off after the MTCMOS switch 931 is disconnected.
The present invention presupposes circuit blocks each having the MTCMOS functional block 910 coexisting with the non-MTCMOS functional block 920.
The flip-flop receives a data input signal D, a clock signal CK, a hold signal HLD, and a sleep signal SLP. The data input signal D is issued to input the data to be held by the flip-flop. The clock signal CK is used to provide the reference for synchronizing the flip-flop.
The hold signal HLD is a control signal that causes the flip-flop to hold data while interrupting the input from the outside. The sleep signal SLP is a control signal that renders the flip-flop inactive by cutting off the supply of the clock signal CK.
The MTCMOS switch 931 (
The clock signal CK and sleep signal SLP are input to the NAND gate 171. The NAND gate 171 is a circuit that generates a NAND between the clock signal CK and the sleep signal SLP. That is, the NAND gate 171 outputs an inverted signal of the clock signal CK unless and until the sleep signal SLP goes active. Being a negative logic signal, the sleep signal SLP remains High when not going active and is driven Low when going active. It follows that an inverted clock signal CKN output by the NAND gate 171 is the inverted signal of the clock signal CK when the sleep signal SLP is inactive, and that the NAND gate 171 has its output driven High while interrupting the clock signal CK when the sleep signal SLP goes active.
The output of the NAND gate 171 is connected to the inverter 172 whose output is a non-inverted clock signal CKP. The non-inverted clock signal CKP is furnished as the clock signal CK when the sleep signal SLP is inactive and becomes a Low output when the sleep signal SLP goes active.
The hold signal HLD is input to the inverter 181. The inverter 181 inverts the hold signal HLD so as to output an inverted hold signal HLDN.
The clocked inverters 111 and 112 constitute a circuit that controls the input to the flip-flop. That is, when the hold signal HLD is inactive, the clocked inverter 111 inputs an inverted signal of the data input signal D to the flip-flop. When the hold signal HLD goes active, the clocked inverter 112 inputs an inverted signal of the output from the inverter 151 to the flip-flop through a feedback loop. Because the clocked inverters 111 and 112 receive control signals with their phases opposite to each other, each of the inverters can input a mutually exclusive signal.
The inverter 131 and clocked inverter 132 are storage elements constituting a master flip-flop. When the non-inverted clock signal CKP is driven Low, the master flip-flop receives the input signal from the clocked inverter 111 or 112 at a leading edge of the clock signal. The master flip-flop holds the received signal while the non-inverted clock signal CKP remains High.
The input of the inverter 131 is connected to the outputs of the clocked inverters 121 and 132. While the non-inverted clock signal CKP is being Low, the clocked inverter 121 supplies the input of the inverter 131 with an inverted signal of the signal coming from the clocked inverter 111 or 112; while the non-inverted clock signal CKP is being High, the clocked inverter 132 supplies the input of the inverter 131 with an inverted signal of the output signal from the inverter 131. Because the clocked inverters 121 and 132 receive control signals with their phases opposite to each other, each of the inverters can supply a mutually exclusive signal.
The inverters 151 and 152 are storage elements that constitute a slave flip-flop. When the non-inverted clock signal CKP is driven High, the slave flip-flop receives the signal from the master flip-flop at a trailing edge of the clock signal. The slave flip-flop holds the received signal while the non-inverted clock signal CKP remains Low. The inverters 151 and 152 are kept powered after the MTCMOS switch 931 is disconnected, so that the data is held intact. This makes it possible for the slave flip-flop to supply the master flip-flop with the data being kept after a reset through the use of a feedback loop.
The input of the inverter 151 is connected to the outputs of the transmission gates 141 and 142. While the non-inverted clock signal CKP is being High, the transmission gate 141 supplies the input of the inverter 151 with the signal coming from the master flip-flop; while the non-inverted clock signal CKP is being Low, the transmission gate 142 supplies the input of the inverter 151 with the output signal from the inverter 152. Because the transmission gates 141 and 142 receive control signals with their phases opposite to each other, each of the gates can supply a mutually exclusive signal.
The input of the inverter 151 is connected to the input of the inverter 161. The output of the inverter 161 provides an output Q of the flip-flop.
The clock signal CK provides the reference for synchronizing the flip-flop and alternates between Low and High.
The hold signal HLD is a control signal that interrupts the input from the outside. When the hold signal HLD is inactive (Low), the data input signal D is input to the master flip-flop; when the hold signal HLD goes active (High), an output signal Ds of the slave flip-flop is input to the master flip-flop.
In the diagram of
The sleep signal SLP is a control signal that interrupts the supply of the clock signal CK. When the sleep signal SLP is inactive (High), the clock signal CK is supplied as the non-inverted clock signal CKP. When the sleep signal SLP gives active (Low), the clock signal CK is interrupted and the non-inverted clock signal CKP is driven Low. This stops the operation of the flip-flop and inhibits the output of the master flip-flop from getting input to the slave flip-flop.
The MTCMOS control signal PG is a control signal that turns on or off the connection of the MTCMOS switch 931 (
Referring to the diagram of
When the MTCMOS control signal PG again goes active (High), the data held by the slave flip-flop is fed to the master flip-flop to prepare for the flip-flop to operate again. When the sleep signal SLP goes inactive (High), the flip-flop resumes its operation in synchronism with the clock signal. When the hold signal HLD goes inactive (Low), the next input signal is supplied to the master flip-flop.
As described, the flip-flop is allowed to effect normal transition to standby mode when the hold signal HLD is first driven active (High) followed by the sleep signal SLP also driven active (Low), before the MTCMOS switch 931 is disconnected. To effect normal transition of the flip-flop from standby mode to operation mode involves first connecting the MTCMOS switch 931 and then driving the sleep signal SLP inactive (High) followed by the hold signal HLD also driven inactive (Low).
That is, the timings are ensured by a nesting arrangement in which the MTCMOS control signal PG is driven inactive (Low) only when at least the sleep signal SLP goes active (Low) and in which the sleep signal SLP is driven active (Low) only when at least the hold signal HLD goes active (High). This makes it significantly easier to adjust the timings involved in partially stopping the supply of power to the flip-flop.
In a traditional setup having no feedback loop ranging from the slave flip-flop to the master flip-flop as with the embodiment of this invention, it is not easy to adjust the timings for transition to standby mode solely by the method of interrupting the clock signal using the sleep signal SLP. For example, if the sleep signal SLP is driven active (Low) from inactive (High) while the clock signal CK remains High, then the non-inverted clock signal CKP is driven Low, causing the next data input signal to be erroneously received. This problem is bypassed by the embodiment of the invention making the state of the master flip-flop the same as that of the slave flip-flop by having the hold signal HLD driven active (High).
The same applies to the timings for transition from standby mode to operation mode. In a traditional setup, for example, if the sleep signal SLP is driven inactive (High) from active (Low) while the clock signal CK remains High, then the non-inverted clock signal CKP is driven High from Low, causing the next data input signal to be erroneously received. This problem is bypassed by the embodiment of the invention holding the data during the cycle where the hold signal HLD goes inactive (Low), i.e., until the next leading edge of the clock signal CK is reached.
The MTCMOS flip-flop 810 corresponds to the flip-flop discussed above in reference to
The MTCMOS control circuit 890 is a circuit that supplies control signals to the MTCMOS flip-flops 810 and MTCMOS switches 820. In this example, the MTCMOS control circuit 890 supplies the hold signal HLD and sleep signal SLP to the MTCMOS flip-flops 810 and the MTCMOS control signal PG to the MTCMOS switches 820.
The MTCMOS control circuit 890 thus manages the control signals in a unified manner. Alternatively, the same type of control signal may be divided and controlled independently. Illustratively, as shown in
In the setup of
The clear signal CL and inhibit signal INH are input to a NOR gate 191. The NOR gate 191 is a circuit that outputs the negative OR between the clear signal CL and the inhibit signal INH. The output of the NOR gate 191 is input to an inverter 192. The inverter 192 outputs a non-inverted clear signal CLP. That is, when the inhibit signal INH remains inactive (Low), the non-inverted clear signal CLP is output as the clear signal CL. When the inhibit signal INH goes active (High), the non-inverted clear signal CLP is fixed to the inactive state (held High). Because the NOR gate 191 and inverter 192 belong to a non-MTCMOS functional block 23, the supply of power is continued even after the MTCMOS switch 931 is disconnected.
In the first variation of the embodiment, an inverter 151 and a NAND gate 153 constitute a slave flip-flop. Whereas the inverter 151 corresponds to its counterpart in the example of
In the first variation of the embodiment, a NAND gate 133 and a clocked inverter 132 constitute a master flip-flop. Whereas the clocked inverter 132 corresponds to its counterpart in the example of
The gates in
In the setup of
The preset signal PR and inhibit signal INH are input to a NOR gate 193. The NOR gate 193 outputs the NOR calculated between the preset signal PR and the inhibit signal INH. The output of the NOR gate 193 is input to an inverter 194. The output of the inverter 194 is a non-inverted preset signal PRP. That is, when the inhibit signal INH remains inactive (Low), the non-inverted preset signal PRP is output as the preset signal PR. When the inhibit signal INH goes active (High), the non-inverted preset signal PRP is fixed to the inactive state (held High). Because the NOR gate 193 and inverter 194 belong to a non-MTCMOS functional block 25, the supply of power is continued even after the MTCMOS switch 931 is disconnected.
In the second variation of the embodiment, a NAND gate 154 and an inverter 152 constitute a slave flip-flop. Whereas the inverter 152 corresponds to its counterpart in the example of
In the second variation of the embodiment, an inverter 131 and a clocked NAND gate 134 constitute a master flip-flop. Whereas the inverter 131 corresponds to its counterpart in the example of
The gates in
In the setup of
The enable signal EN, along with the hold signal HLD, is input to a NOR gate 182. The NOR gate 182 is a circuit that outputs the NOR calculated between the enable signal EN and the hold signal HLD. The output of the NOR gate 182 is an inverted enable signal ENN that is input to an inverter 183. The output of the inverter 183 is a non-inverted enable signal ENP. That is, when the enable signal EN goes active (Low) with the hold signal HLD brought inactive (Low), the non-inverted enable signal ENP goes active (Low). When the hold signal HLD goes active (High) or when the enable signal EN is inactive (High), the non-inverted enable signal ENP is driven inactive (High). The reverse applies to the inverted enable signal ENN.
The non-inverted enable signal ENP and inverted enable signal ENN are input to clocked inverters 113 and 114. The clocked inverters 113 and 114 replace the clocked inverters 111 and 112 and control the input to the flip-flop. That is, when the non-inverted enable signal ENP remains inactive, the clocked inverter 113 inputs the inverted signal of the data input signal D to the flip-flop. When the non-inverted enable signal ENP goes active, the clocked inverter 114 inputs the inverted signal of the output of the inverter 151 to the flip-flop through a feedback loop. Because the clocked inverters 113 and 114 receive control signals with their phases opposite to each other, each of the inverters can input a mutually exclusive signal.
The gates in
In the setup of
The scan mode signal S is input to an inverter 201. In turn, the inverter 201 inverts the scan mode signal S so as to output an inverted scan mode signal SN.
In the fourth variation of the embodiment, a clocked inverter 211 and a transmission gate 212 are parallelly inserted upstream of the master flip-flop, i.e., on the input side of the clocked inverter 121. In this case, when the scan mode signal S goes active (High), the clocked inverter 211 inputs the scan-in signal SI to the clocked inverter 121; when the scan mode signal S is inactive (Low), the transmission gate 212 inputs either of the outputs of the clocked inverters 111 and 112 to the clocked inverter 121. Because the clocked inverter 211 and transmission gate 212 receive control signals with their phases opposite to each other, each of them can input a mutually exclusive signal.
An inverter 261 is connected to the output of the inverter 152. The inverter 261 is a circuit that outputs the inverted signal of the output of the inverter 152 as the scan-out signal SO.
According to the fourth variation outlined above, the scan path is set up by partially modifying the circuit structure of the MTCMOS flip-flop embodying the present invention. Although the fourth variation is shown to have a typical structure of the MTCMOS flip-flop provided with a basic scan path arrangement, this is not limitative of the invention. As discussed above in the form of the first through the third variations, the embodiment of the invention may also be furnished with the clearing function, preset function, or enable function.
According to the preferred embodiments of the present invention, when the hold signal HLD goes active, the output of the slave flip-flop under non-MTCMOS control is fed back to the master flip-flop under MTCMOS control. This arrangement makes it appreciably simple to adjust the timings for connecting and disconnecting the MTCMOS switch 931. This significantly facilitates utilization of the MTCMOS technology in ASIC designs.
What has been described above as the preferred embodiments of the present invention with reference to the accompanying drawings corresponds to the appended claims as follows: the description of the preferred embodiments basically provides specific examples supporting what is claimed. If any example of the invention described above as a preferred embodiment does not have an exactly corresponding claim, this does not mean that the example in question has no relevance to the claims. Conversely, if any example of the invention depicted above has a specifically corresponding claim, this does not mean that the example in question is limited to that claim or has no relevance to other claims.
Illustratively, in a flip-flop according to an embodiment of the present invention, the NAND gate 171 and the inverter 172 described above are corresponding to a clock supply circuit; the inverter 131 and the clocked inverter 132 to a first holding circuit; the inverters 151 and 152 to a second holding circuit; the clocked inverters 111 and 112 to an input switching circuit; and the MTCMOS switch 931 to a power supply control circuit.
Likewise, in a flip-flop according to an embodiment of the present invention, the NAND gates 133 and 151 are corresponding to a clearing circuit. The NOR gate 191 is alternatively corresponding to the clearing circuit.
In a flip-flop according to an embodiment of the present invention, the NAND gates 134 and 154 are illustratively corresponding to a preset circuit. The NOR gate 193 is alternatively corresponding to the preset circuit.
In a flip-flop according to an embodiment of the present invention, the clocked inverters 113 and 114 are alternatively corresponding to the input switching circuit.
In a flip-flop according to an embodiment of the present invention, as another alternative, the clocked inverters 111, 112 and 211 as well as the transmission gates 212 are corresponding to the input switching circuit.
Furthermore, in a flip-flop according to an embodiment of the present invention, the MTCMOS control circuit 890 is corresponding to a flip-flop control circuit.
The series of steps and processes discussed above as part of the embodiment may be construed as methods for carrying out such steps and processes, as programs for causing a computer to execute such methods, or as a recording medium that stores such programs.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2006-331477 | Dec 2006 | JP | national |
