Flip-flop circuit and frequency divider using the flip-flop circuit

Abstract

In a flip-flop circuit where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the conductivity of a first load transistor connected to the first output terminal is controlled by the signal from the second output terminal, and the conductivity of a second load transistor connected to the second output terminal is controlled by the signal from the first output terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will be described in detail based on the following figures, wherein:

FIG. 1 is a circuit diagram of a TFF pertaining to a first embodiment of the present invention;

FIG. 2 is a configural diagram of a ½ N frequency divider pertaining to the first embodiment of the present invention;

FIG. 3 is a diagram showing the result of a simulation using the 1/16 frequency divider of FIG. 2;

FIG. 4 is a circuit diagram of a TFF pertaining to a second embodiment of the present invention;

FIG. 5 is a configural diagram of a ½ N frequency divider pertaining to the second embodiment of the present invention;

FIG. 6 is a configural diagram of a frequency divider pertaining to a third embodiment of the present invention;

FIG. 7 is a circuit diagram of a conventional MCML TFF; and

FIG. 8 is a configural diagram showing a conventional ½ N frequency divider.

Claims

1. A flip-flop circuit comprising: a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals;a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows;a first load transistor that is connected between the first power supply potential and the first output terminal and whose conductive state is controlled by the signal of the second output terminal;a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal;a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by complementary first and second input pulses and complementary signals of first and second output nodes;a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows;a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows;a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node;a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node; anda second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals.

2. The flip-flop circuit of claim 1, wherein the first to fourth load elements and the first to fourth load transistors comprise PMOS.

3. The flip-flop circuit of claim 1, wherein the second power supply potential is a ground potential.

4. The flip-flop circuit of claim 1, wherein the first latch portion comprises a first transistor that is connected between the first output terminal and a first node and whose conductive state is controlled by the signal of the second output terminal,a second transistor that is connected between the first node and the second power supply potential and whose conductive state is controlled by the second input pulse,a third transistor that is connected between the first output terminal and a second node and whose conductive state is controlled by the signal of the second output node,a fourth transistor that is connected between the second node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifth transistor that is connected between the second output terminal and a third node and whose conductive state is controlled by the signal of the first output terminal,a sixth transistor that is connected between the third node and the second power supply potential and whose conductive state is controlled by the second input pulse,a seventh transistor that is connected between the second output terminal and a fourth node and whose conductive state is controlled by the signal of the first output node, andan eighth transistor that is connected between the fourth node and the second power supply potential and whose conductive state is controlled by the first input pulse, andthe second latch portion comprises a ninth transistor that is connected between the first output node and a fifth node and whose conductive state is controlled by the signal of the second output node,a tenth transistor that is connected between the fifth node and the second power supply potential and whose conductive state is controlled by the first input pulse,an eleventh transistor that is connected between the first output node and a sixth node and whose conductive state is controlled by the signal of the first output terminal,a twelfth transistor that is connected between the sixth node and the second power supply potential and whose conductive state is controlled by the second input pulse,a thirteenth transistor that is connected between the second output node and a seventh node and whose conductive state is controlled by the signal of the first output node,a fourteenth transistor that is connected between the seventh node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifteenth transistor that is connected between the second output node and an eighth node and whose conductive state is controlled by the signal of the second output terminal, anda sixteenth transistor that is connected between the eighth node and the second power supply potential and whose conductive state is controlled by the second input pulse.

5. The flip-flop circuit of claim 4, wherein the first to sixteenth transistors comprise NMOS.

6. A flip-flop circuit comprising: a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals;a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal;a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by complementary first and second input pulses and complementary signals of first and second output nodes;a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node;a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node; anda second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals.

7. The flip-flop of claim 6, wherein the first to fourth load transistors comprise PMOS.

8. The flip-flop circuit of claim 6, wherein the second power supply potential is a ground potential.

9. The flip-flop circuit of claim 6, wherein the first latch portion comprises a first transistor that is connected between the first output terminal and a first node and whose conductive state is controlled by the signal of the second output terminal,a second transistor that is connected between the first node and the second power supply potential and whose conductive state is controlled by the second input pulse,a third transistor that is connected between the first output terminal and a second node and whose conductive state is controlled by the signal of the second output node,a fourth transistor that is connected between the second node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifth transistor that is connected between the second output terminal and a third node and whose conductive state is controlled by the signal of the first output terminal,a sixth transistor that is connected between the third node and the second power supply potential and whose conductive state is controlled by the second input pulse,a seventh transistor that is connected between the second output terminal and a fourth node and whose conductive state is controlled by the signal of the first output node, andan eighth transistor that is connected between the fourth node and the second power supply potential and whose conductive state is controlled by the first input pulse, andthe second latch portion comprises a ninth transistor that is connected between the first output node and a fifth node and whose conductive state is controlled by the signal of the second output node,a tenth transistor that is connected between the fifth node and the second power supply potential and whose conductive state is controlled by the first input pulse,an eleventh transistor that is connected between the first output node and a sixth node and whose conductive state is controlled by the signal of the first output terminal,a twelfth transistor that is connected between the sixth node and the second power supply potential and whose conductive state is controlled by the second input pulse,a thirteenth transistor that is connected between the second output node and a seventh node and whose conductive state is controlled by the signal of the first output node,a fourteenth transistor that is connected between the seventh node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifteenth transistor that is connected between the second output node and an eighth node and whose conductive state is controlled by the signal of the second output terminal, anda sixteenth transistor that is connected between the eighth node and the second power supply potential and whose conductive state is controlled by the second input pulse.

10. The flip-flop circuit of claim 9, wherein the first to sixteenth transistors comprise NMOS.

11. A frequency divider comprising N stages (where N is an integer equal to or greater than 2) of cascade-connected circuit blocks comprising flip-flop circuits where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the frequency divider dividing the frequencies of the first and second input pulses into ½ N, wherein the circuit blocks comprise a first circuit block whose frequency is high and a second circuit block whose frequency is low,the first circuit block comprises a first flip-flop circuit,the first flip-flop circuit comprises a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals,a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by the first and second input pulses and complementary signals of first and second output nodes,a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows,a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows, anda second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals,the second circuit block comprises a second flip-flop circuit, andthe second flip-flop circuit comprises a fifth load element that is connected between the first output terminal and the first power supply potential and through which power supply current flows,a sixth load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,a first load transistor that is connected between the first power supply potential and the first output terminal and whose conductive state is controlled by the signal of the second output terminal,a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,the first latch portion,a seventh load element that is connected between the first power supply potential and the first output node and through which power supply current flows,an eighth load element that is connected between the first power supply potential and the second output node and through which power supply current flows,a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, andthe second latch portion.

12. The frequency divider of claim 11, wherein the first latch portion comprises a first transistor that is connected between the first output terminal and a first node and whose conductive state is controlled by the signal of the second output terminal,a second transistor that is connected between the first node and the second power supply potential and whose conductive state is controlled by the second input pulse,a third transistor that is connected between the first output terminal and a second node and whose conductive state is controlled by the signal of the second output node,a fourth transistor that is connected between the second node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifth transistor that is connected between the second output terminal and a third node and whose conductive state is controlled by the signal of the first output terminal,a sixth transistor that is connected between the third node and the second power supply potential and whose conductive state is controlled by the second input pulse,a seventh transistor that is connected between the second output terminal and a fourth node and whose conductive state is controlled by the signal of the first output node, andan eighth transistor that is connected between the fourth node and the second power supply potential and whose conductive state is controlled by the first input pulse, andthe second latch portion comprises a ninth transistor that is connected between the first output node and a fifth node and whose conductive state is controlled by the signal of the second output node,a tenth transistor that is connected between the fifth node and the second power supply potential and whose conductive state is controlled by the first input pulse,an eleventh transistor that is connected between the first output node and a sixth node and whose conductive state is controlled by the signal of the first output terminal,a twelfth transistor that is connected between the sixth node and the second power supply potential and whose conductive state is controlled by the second input pulse,a thirteenth transistor that is connected between the second output node and a seventh node and whose conductive state is controlled by the signal of the first output node,a fourteenth transistor that is connected between the seventh node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifteenth transistor that is connected between the second output node and an eighth node and whose conductive state is controlled by the signal of the second output terminal, anda sixteenth transistor that is connected between the eighth node and the second power supply potential and whose conductive state is controlled by the second input pulse.

13. The frequency divider of claim 11, wherein the drive capability of the first load element and the combined drive capability of the fifth load element and the first load transistor are substantially equal,the drive capability of the second load element and the combined drive capability of the sixth load element and the second load transistor are substantially equal,the drive capability of the third load element and the combined drive capability of the seventh load element and the third load transistor are substantially equal, andthe drive capability of the fourth load element and the combined drive capability of the eighth load element and the fourth load transistor are substantially equal.

14. A frequency divider comprising N stages (where N is an integer equal to or greater than 2) of cascade-connected circuit blocks comprising flip-flop circuits where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the frequency divider dividing the frequencies of the first and second input pulses into ½ N, wherein the circuit blocks comprise a first circuit block whose frequency is high and a second circuit block whose frequency is low,the first circuit block comprises a first flip-flop circuit,the first flip-flop circuit comprises a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals,a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by the first and second input pulses and complementary signals of first and second output nodes,a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows,a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows, anda second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals,the second circuit block comprises a second flip-flop circuit, andthe second flip-flop circuit comprises a first load transistor that is connected between the first output terminal and the first power supply potential and whose conductive state is controlled by the signal of the second output terminal,a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,the first latch portion,a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, andthe second latch portion.

15. The frequency divider of claim 14, wherein the first latch portion comprises a first transistor that is connected between the first output terminal and a first node and whose conductive state is controlled by the signal of the second output terminal,a second transistor that is connected between the first node and the second power supply potential and whose conductive state is controlled by the second input pulse,a third transistor that is connected between the first output terminal and a second node and whose conductive state is controlled by the signal of the second output node,a fourth transistor that is connected between the second node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifth transistor that is connected between the second output terminal and a third node and whose conductive state is controlled by the signal of the first output terminal,a sixth transistor that is connected between the third node and the second power supply potential and whose conductive state is controlled by the second input pulse,a seventh transistor that is connected between the second output terminal and a fourth node and whose conductive state is controlled by the signal of the first output node, andan eighth transistor that is connected between the fourth node and the second power supply potential and whose conductive state is controlled by the first input pulse, andthe second latch portion comprises a ninth transistor that is connected between the first output node and a fifth node and whose conductive state is controlled by the signal of the second output node,a tenth transistor that is connected between the fifth node and the second power supply potential and whose conductive state is controlled by the first input pulse,an eleventh transistor that is connected between the first output node and a sixth node and whose conductive state is controlled by the signal of the first output terminal,a twelfth transistor that is connected between the sixth node and the second power supply potential and whose conductive state is controlled by the second input pulse,a thirteenth transistor that is connected between the second output node and a seventh node and whose conductive state is controlled by the signal of the first output node,a fourteenth transistor that is connected between the seventh node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifteenth transistor that is connected between the second output node and an eighth node and whose conductive state is controlled by the signal of the second output terminal, anda sixteenth transistor that is connected between the eighth node and the second power supply potential and whose conductive state is controlled by the second input pulse.

16. The frequency divider of claim 14, wherein the drive capability of the first load element and the drive capability of the first load transistor are substantially equal,the drive capability of the second load element and the drive capability of the second load transistor are substantially equal,the drive capability of the third load element and the drive capability of the third load transistor are substantially equal, andthe drive capability of the fourth load element and the drive capability of the fourth load transistor are substantially equal.

17. A frequency divider comprising N stages (where N is an integer equal to or greater than 2) of cascade-connected circuit blocks comprising flip-flop circuits where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the frequency divider dividing the frequencies of the first and second input pulses into ½ N, wherein the circuit blocks comprise a first circuit block that operates at a high frequency, a second circuit block that operates at a low frequency, and a third circuit block that operates at an intermediate frequency,the first circuit block comprises a first flip-flop circuit,the first flip-flop circuit comprises a first load element through which power supply current flows and that is connected between a first power supply potential and a first output terminal, the first output terminal and a second output terminal outputting complementary signals,a second load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,a first latch portion that is connected between a second power supply potential different from the first power supply potential and the first and second output terminals, latches the signals of the first and second output terminals, and inverts the latched signals of the first and second output terminals by the first and second input pulses and complementary signals of first and second output nodes,a third load element that is connected between the first power supply potential and the first output node and through which power supply current flows,a fourth load element that is connected between the first power supply potential and the second output node and through which power supply current flows, anda second latch portion that is connected between the second power supply potential and the first and second output nodes, latches the signals of the first and second output nodes, and inverts the latched signals of the first and second output nodes by the first and second input pulses and the signals of the first and second output terminals,the second circuit block comprises a second flip-flop circuit,the second flip-flop circuit comprises a first load transistor that is connected between the first output terminal and the first power supply potential and whose conductive state is controlled by the signal of the second output terminal,a second load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,the first latch portion,a third load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,a fourth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, andthe second latch portion,the third circuit block comprises a third flip-flop circuit, andthe third flip-flop circuit comprises a fifth load element that is connected between the first output terminal and the first power supply potential and through which power supply current flows,a sixth load element that is connected between the first power supply potential and the second output terminal and through which power supply current flows,a fifth load transistor that is connected between the first power supply potential and the first output terminal and whose conductive state is controlled by the signal of the second output terminal,a sixth load transistor that is connected between the first power supply potential and the second output terminal and whose conductive state is controlled by the signal of the first output terminal,the first latch portion,a seventh load element that is connected between the first power supply potential and the first output node and through which power supply current flows,an eighth load element that is connected between the first power supply potential and the second output node and through which power supply current flows,a seventh load transistor that is connected between the first power supply potential and the first output node and whose conductive state is controlled by the signal of the second output node,an eighth load transistor that is connected between the first power supply potential and the second output node and whose conductive state is controlled by the signal of the first output node, andthe second latch portion.

18. The frequency divider of claim 17, wherein the first latch portion comprises a first transistor that is connected between the first output terminal and a first node and whose conductive state is controlled by the signal of the second output terminal,a second transistor that is connected between the first node and the second power supply potential and whose conductive state is controlled by the second input pulse,a third transistor that is connected between the first output terminal and a second node and whose conductive state is controlled by the signal of the second output node,a fourth transistor that is connected between the second node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifth transistor that is connected between the second output terminal and a third node and whose conductive state is controlled by the signal of the first output terminal,a sixth transistor that is connected between the third node and the second power supply potential and whose conductive state is controlled by the second input pulse,a seventh transistor that is connected between the second output terminal and a fourth node and whose conductive state is controlled by the signal of the first output node, andan eighth transistor that is connected between the fourth node and the second power supply potential and whose conductive state is controlled by the first input pulse, andthe second latch portion comprises a ninth transistor that is connected between the first output node and a fifth node and whose conductive state is controlled by the signal of the second output node,a tenth transistor that is connected between the fifth node and the second power supply potential and whose conductive state is controlled by the first input pulse,an eleventh transistor that is connected between the first output node and a sixth node and whose conductive state is controlled by the signal of the first output terminal,a twelfth transistor that is connected between the sixth node and the second power supply potential and whose conductive state is controlled by the second input pulse,a thirteenth transistor that is connected between the second output node and a seventh node and whose conductive state is controlled by the signal of the first output node,a fourteenth transistor that is connected between the seventh node and the second power supply potential and whose conductive state is controlled by the first input pulse,a fifteenth transistor that is connected between the second output node and an eighth node and whose conductive state is controlled by the signal of the second output terminal, anda sixteenth transistor that is connected between the eighth node and the second power supply potential and whose conductive state is controlled by the second input pulse.

19. The frequency divider of claim 17, wherein the drive capability of the first load element, the drive capability of the first load transistor, and the combined drive capability of the fifth load element and the fifth load transistor are substantially equal,the drive capability of the second load element, the drive capability of the second load transistor, and the combined drive capability of the sixth load element and the sixth load transistor are substantially equal,the drive capability of the third load element, the drive capability of the third load transistor, and the combined drive capability of the seventh load element and the seventh load transistor are substantially equal, andthe drive capability of the fourth load element, the drive capability of the fourth load transistor, and the combined drive capability of the eighth load element and the eighth load transistor are substantially equal.