BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit block diagram of a typical delay path in a digital circuit.
FIG. 2 is a clock diagram of the operating delay of the circuit block of FIG. 1.
FIG. 3 is a circuit block diagram of the conventional master-salve type flip-flop.
FIG. 4 is a circuit block diagram of the flip-flop having improved set-up time according to an embodiment of the present invention.
FIG. 5 is a circuit block diagram of the flip-flop having improved set-up time according to another embodiment of the present invention.
FIG. 6 is the method used with the flip-flop having improved set-up time according to an embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
FIG. 4 is a circuit block diagram of the flip-flop having improved set-up time according to an embodiment of the present invention. The flip-flop having improved set-up time 400 comprises selectors 41 and 44, master latches 42 and 43, and a slave latch 45. The control signal SEL41 controls the selector 41, such that after the plurality of non-critical data such as the non-critical data scan_in (scanning in) signal and the feedback signal are selected by the selector 41, one of the plurality of non-selective data is output to be a first selected data to the master latch 42, and the master latch 42 latches the first selected data. The critical data is input and stored to be latched in the maser latch 43. And the generating time of each of the non-critical data is shorter than the generating time of the critical data. The selector 44 receives the first selected data of the maser latch 42 and the critical data of the maser latch 43. The control signal SEL44 controls the selector 44 to output the second selected data, and the second selected data is input to the slave latch 45. Then the slave latch 45 latches second selected data the data and exports an output data.
The present invention uses two different master latches to separately process the critical data and the non-critical data, such that it is not required for the flip-flop to achieve the unification of the clock for the process of the critical data and the non-critical data. Further, the non-critical data with the shorter generating time quickly passes through the selector to the slave latch. Since the function of separate processing makes the slave latch process the non-critical data first, which is help to reduce the set-up time of the flip-flop.
FIG. 5 is a circuit block diagram of the flip-flop having improved set-up time according to another embodiment of the present invention. The flip-flop 500 comprises a selector 51, a positive latch 52, a positive latch 53, a selector 54, a slave latch 55, and inverters 501˜505, 511. A plurality of non-critical data passes through the selector controlled by the select signal SEL1, and a first select signal is input to the master latch 52 by the inverter 511. The master latch 52 comprises switches 521, 522 and inverters 523, 524. The switch 521 controls the master latch 52 to receive the first selected data, and the first selected data is latched by the inverters 523, 524 and the switch 522 through the twice inverting mechanism, and then the non-critical data is input to the selector 54. The clock signal CK generates a clock signal CKB through the inverter 502, and generates a clock signal CK1 through the inverter 503. The clock signal CKB and the clock signal CK1 are used to control the ON/OFF of the switch 521 and the switch 522. The master 52 can perform the latching function with this structure, and the critical data is inverted by the inverter 501 and input to the master latch 53. The master latch 53 has a structure same as that of the master latch 52. The master latch 522 comprises switches 531, 532 and inverters 533, 534, and is used to latch and output the inverted critical data to the selector 54.
The selector 54 receives the first selected data of the maser latch 52 and the critical data of the master latch 53. The selector 54 outputs the second selected data to the slave latch 55 through the control of the select signal SEL2. The slave latch 55 has a structure same as that of the master latch 52, and the slave latch 55 comprises switches 551, 552 and inverters 553, 554. The slave latch 55 latches the second selected data, and receives the second selected data through the inverters 504, 505, so as to generate the output signal Q and the inverted output signal QB.
The present invention uses a select signal to control a selector to filter the plurality of non-critical data, and uses another select signal to control another selector to filter the critical data and the non-critical data. Thus, the non-critical data and the critical data can be separately processed, and not required to follow the same clock, thereby enhancing the processing speed.
FIG. 6 is the method used with the flip-flop having improved set-up time according to an embodiment of the present invention. First, in step S601, a critical data is received and latched. At the same time, in step 603, a plurality of non-critical data is received, and a first selected data is output. Then, in step S605, the first selected data is latched. Next, in step S607, the critical data or the first selected data is selected to be a second selected data. In step S609, the second selected data is latched and output.
To sum up, according to the flip-flop having improved set-up time and the method used with provided by the present invention, since two different master latches are used with the selector to separately process the critical data and the non-critical data, such that the critical data and the non-critical data can be latched by different master latches without affecting each other, thereby improving the set-up time of the flip-flop and the time sequence of the critical path.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20080024184
