This application relates to improvements in the inventions disclosed in the following patents and copending U.S. patent applications, all of which are assigned to Texas Instruments and all of which are incorporated by reference: U.S. patent application Ser. No. 08/135,754 Oct. 12, 1993 entitled "MULTI-PROCESSOR WITH CROSSBAR LINK OF PROCESSORS AND MEMORIES AND METHOD OF OPERATION", a continuation of U.S. patent application Ser. No. 07/933,865 filed Aug. 21, 1992 and now abandoned, which is a continuation of U.S. patent application Ser. No. 07/435,591 filed Nov. 17, 1989 and now abandoned; U.S. Pat. No. 5,212,777, issued May 18, 1993, filed Nov. 17, 1989 and entitled "SIMD/MIMD RECONFIGURABLE MULTI-PROCESSOR AND METHOD OF OPERATION"; U.S. patent application Ser. No. 07/895,565 filed Jun. 5, 1992 entitled "RECONFIGURABLE COMMUNICATIONS FOR MULTI-PROCESSOR AND METHOD OF OPERATION," a continuation of U.S. patent application Ser. No. 437,856 filed Nov. 17, 1989 and now abandoned; U.S. patent application Ser. No. 07/437,852 filed Nov. 17, 1989 entitled "REDUCED AREA OF CROSSBAR AND METHOD OF OPERATION"; U.S. patent application Ser. No. 08/032,530 filed Mar. 15, 1993 entitled "SYNCHRONIZED MIMD MULTI-PROCESSING SYSTEM AND METHOD OF OPERATION," a continuation of U.S. patent application Ser. No. 07/437,853 filed Nov. 17, 1989 and now abandoned; U.S. Pat. No. 5,197,140 issued Mar. 23, 1993 filed Nov. 17, 1989 and entitled "SLICED ADDRESSING MULTI-PROCESSOR AND METHOD OF OPERATION"; U.S. patent application Ser. No. 437,857 filed Nov. 17, 1989 entitled "ARITHMETIC LOGIC UNIT ONES COUNTING LOGIC"; U.S. Pat. No. 5,239,654 issued Aug. 24, 1993 filed Nov. 17, 1989 and entitled "DUAL MODE SIMD/MIMD PROCESSOR PROVIDING REUSE OF MIMD INSTRUCTION MEMORIES AS DATA MEMORIES WHEN OPERATING IN SIMD MODE"; U.S. patent application Ser. No. 911,562 filed Jun. 29, 1992 entitled "IMAGING COMPUTER AND METHOD OF OPERATION", a continuation of U.S. patent application Ser. No. 437,854 filed Nov. 17, 1989 and now abandoned; and U.S. Pat. No. 5,226,125 issued Jul. 6, 1993 filed Nov. 17, 1989 and entitled "SWITCH MATRIX HAVING INTEGRATED CROSSPOINT LOGIC AND METHOD OF OPERATION". U.S. patent application Ser. No. 08/160,299 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT WITH BARREL ROTATOR"; U.S. patent application Ser. No. 08/158,742 filed Nov. 30, 1993 and entitled "ARITHMETIC LOGIC UNIT HAVING PLURAL INDEPENDENT SECTIONS AND REGISTER STORING RESULTANT INDICATOR BIT FROM EVERY SECTION"; U.S. patent application Ser. No. 08/160,118 filed Nov. 30, 1993 "MEMORY STORE FROM A REGISTER PAIR CONDITIONAL"; U.S. patent application Ser. No. 08/160,115 filed Nov. 30, 1993 and entitled "ITERATIVE DIVISION APPARATUS, SYSTEM AND METHOD FORMING PLURAL QUOTIENT BITS PER ITERATION"; U.S. patent application Ser. No. 08/159,285 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT FORMING MIXED ARITHMETIC AND BOOLEAN COMBINATIONS"; U.S. patent application Ser. No. 08/160,119 filed Nov. 30, 1993 and entitled "METHOD, APPARATUS AND SYSTEM FORMING THE SUM OF DATA IN PLURAL EQUAL SECTIONS OF A SINGLE DATA WORD"; U.S. patent application Ser. No. 08/159,359 filed Nov. 30, 1993 and entitled "HUFFMAN ENCODING METHOD, CIRCUITS AND SYSTEM EMPLOYING MOST SIGNIFICANT BIT CHANGE FOR SIZE DETECTION"; U.S. patent application Ser. No. 08/160,296 filed Nov. 30, 1993 and entitled "HUFFMAN DECODING METHOD, CIRCUIT AND SYSTEM EMPLOYING CONDITIONAL SUBTRACTION FOR CONVERSION OF NEGATIVE NUMBERS"; U.S. patent application Ser. No. 08/160,112 filed Nov. 30, 1993 and entitled "METHOD, APPARATUS AND SYSTEM FOR SUM OF PLURAL ABSOLUTE DIFFERENCES"; U.S. patent application Ser. No. 08/160,120 filed Nov. 30, 1993 and entitled "ITERATIVE DIVISION APPARATUS, SYSTEM AND METHOD EMPLOYING LEFT MOST ONE'S DETECTION AND LEFT MOST ONE'S DETECTION WITH EXCLUSIVE OR"; U.S. patent application Ser. No. 08/160,114 filed Nov. 30, 1993 and entitled "ADDRESS GENERATOR EMPLOYING SELECTIVE MERGE OF TWO INDEPENDENT ADDRESSES"; U.S. patent application Ser. No. 08/160,116 filed Nov. 30, 1993 and entitled "METHOD, APPARATUS AND SYSTEM METHOD FOR CORRELATION"; U.S. patent application Ser. No. 08/160,297 filed Nov. 30, 1993 and entitled "LONG INSTRUCTION WORD CONTROLLING PLURAL INDEPENDENT PROCESSOR OPERATIONS"; U.S. patent application Ser. No. 08/159,346 filed Nov. 30, 1993 and entitled "ROTATION REGISTER FOR ORTHOGONAL DATA TRANSFORMATION"; U.S. patent application Ser. No. 08/159,652 filed Nov. 30, 1993 "MEDIAN FILTER METHOD, CIRCUIT AND SYSTEM"; U.S. patent application Ser. No. 08/159,344 filed Nov. 30, 1993 and entitled "ARITHMETIC LOGIC UNIT WITH CONDITIONAL REGISTER SOURCE SELECTION"; U.S. patent application Ser. No. 08/160,301 filed Nov. 30, 1993 and entitled "APPARATUS, SYSTEM AND METHOD FOR DIVISION BY ITERATION" U.S. patent application Ser. No. 08/159,650 filed Nov. 30, 1993 and entitled "MULTIPLY ROUNDING USING REDUNDANT CODED MULTIPLY RESULT"; U.S. patent application Ser. No. 08/159,349 filed Nov. 30, 1993 and entitled "SPLIT MULTIPLY OPERATION"; U.S. patent application Ser. No. 08/158,741 filed Nov. 30, 1993 and entitled "MIXED CONDITION TEST CONDITIONAL AND BRANCH OPERATIONS INCLUDING CONDITIONAL TEST FOR ZERO"; U.S. patent application Ser. No. 08/160,302 filed Nov. 30, 1993 and entitled "PACKED WORD PAIR MULTIPLY OPERATION"; U.S. patent application Ser. No. 08/160,573 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT WITH SHIFTER" U.S. patent application Ser. No. 08/159,282 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT WITH MASK GENERATOR"; U.S. patent application Ser. No. 08/160,111 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT WITH BARREL ROTATOR AND MASK GENERATOR"; U.S. patent application Ser. No. 08/160,298 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT WITH SHIFTER AND MASK GENERATOR"; U.S. patent application Ser. No. 08/159,345 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT FORMING THE SUM OF A FIRST INPUT ADDED WITH A FIRST BOOLEAN COMBINATION OF A SECOND INPUT AND THIRD INPUT PLUS A SECOND BOOLEAN COMBINATION OF THE SECOND AND THIRD INPUTS"; U.S. patent application Ser. No. 08/160,113 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT FORMING THE SUM OF FIRST BOOLEAN COMBINATION OF FIRST, SECOND AND THIRD INPUTS PLUS A SECOND BOOLEAN COMBINATION OF FIRST, SECOND AND THIRD INPUTS"; U.S. patent application Ser. No. 08/159,640 filed Nov. 30, 1993 and entitled "THREE INPUT ARITHMETIC LOGIC UNIT EMPLOYING CARRY PROPAGATE LOGIC"; U.S. patent application Ser. No. 08/160,300 filed Nov. 30, 1993 and entitled "DATA PROCESSING APPARATUS, SYSTEM AND METHOD FOR IF, THEN, ELSE OPERATION USING WRITE PRIORITY"; U.S. patent application Ser. No. 08/208,413 filed Mar. 8, 1994 and entitled "TRANSPARENCY AND PLANE MASKING IN TP TRANSFER PROCESSOR"; U.S. patent application Ser. No. 08/208,161 filed Mar. 8, 1994 and entitled "PIXBLT WITH TRANSPARENCY"; U.S. patent application Ser. No. 08/208,171 filed Mar. 8, 1994 and entitled "MESSAGE PASSING AND BLAST INTERRUPT FROM PROCESSOR"; U.S. patent application Ser. No. 08/209,123 filed Mar. 8, 1994 and entitled "GUIDED TRANSFERS WITH X,Y DIMENSION AND VARIABLE STEPPING"; U.S. patent application Ser. No. 08/209,124 filed Mar. 8, 1994 and entitled "GUIDED TRANSFER LINE DRAWING"; U.S. patent application Ser. No. 08/208,517 filed Mar. 8, 1994 and entitled "TRANSFER PROCESSOR MEMORY INTERFACE CONTROLS DIFFERENT MEMORY TYPES SIMULTANEOUSLY"; and U.S. patent application Ser. No. 08/207,503 filed Mar. 8, 1994 and entitled "ARCHITECTURE OF TP TRANSFER PROCESSOR". U.S. patent application Ser. No. 08/207,987 filed Mar. 8, 1993 and entitled "MP VECTOR INSTRUCTIONS FP+LOAD/STORE"; U.S. patent application Ser. No. 08/207,992 filed Mar. 8, 1993 and entitled "NORMALIZATION METHOD FOR FLOATING POINT NUMBERS". This application is related to the following contemporaneously filed applications: U.S. patent application Ser. No. 08/399,083 (TI-18966) "LEFT AND RIGHT JUSTIFICATION OF SINGLE PRECISION MANTISSA IN A DOUBLE PRECISION ROUNDING UNIT".
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5493653 | Schmidt et al. | Feb 1996 | |
5497340 | Uramoto et al. | Mar 1996 | |
5534844 | Norris | Jul 1996 | |
5557708 | Herbert | Sep 1996 |