These and other features, aspects, and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
Preferred embodiments of the invention are described below with reference to the accompanying drawings.
The present embodiment is not limited to the present embodiment, and can variously be changed without departing from the scope of the present invention.
As shown in
The photographing lens 102 is a lens for focus adjustment included in a photographing optical system, and is driven in an optical axis direction (an arrow direction of
The lens driving section 103 has a motor and a driving circuit (a motor driver) of the motor. The lens CPU 104 is a control circuit which controls the lens driving section 103, and can communicate with an AF controller 121 disposed in the camera body 110 via communication connectors 105. From this lens CPU 104 to the AF controller 121, communication of lens data such as manufacturing fluctuation information of the photographing lens 102 and aberration information, for example these information is stored in the lens CPU 104 beforehand, is performed.
On the other hand, the camera body 110 is provided with a main mirror 111 positioned along an optical axis of the photographing lens 102. The main mirror 111 is rotatably disposed as a movable mirror. A middle portion of the main mirror is a half mirror, and a part of entering luminous fluxes passes through the portion of the half mirror.
When the main mirror 111 is disposed at a downward position as shown in
Furthermore, another part of the luminous fluxes which has reached the main mirror 111 passes through the half mirror portion, is reflected by a sub-mirror 115 installed on the back surface of the main mirror 111, and is guided into an AF optical system which performs automatic focus detection (AF). The AF optical system has a condenser lens 116, a reflection mirror 117, separator aperture stops 118 constituting two pairs of aperture stops and separator lenses 119 constituting two pairs of image re-forming lenses. This AF optical system will be described with reference to
The AF sensor 120 can detect focused states of a plurality of focusing points P1 to P23 in a photographing screen 131 shown in, for example,
A focus detection method of a TTL phase difference detection system has been described above. As described above, a part of the luminous fluxes from the subject passes through two pairs of separator aperture stops 118 and two pairs of pupil areas of the photographing lens 102 which is optically conjugate with respect to the primary image forming surface, and is received by the AF sensor 120.
In the AF sensor 120, the luminous fluxes from the subject are converted into an analog electric signal by photoelectric conversion. An output of the AF sensor 120 is input into the AF controller 121 which is a focus detecting section to calculate a defocus amount. An operation of this AF controller 121 is controlled by a system controller 122.
The defocus amount obtained by the AF controller 121 is transmitted to the lens CPU 104. The lens CPU 104 calculates a motor driving amount for driving the photographing lens 102 based on the received defocus amount. The lens CPU 104 drives focusing of the photographing lens 102 via the lens driving section 103 based on the calculated motor driving amount.
Furthermore, in
Next, the AF sensor 120 will be described.
Moreover, as shown in
Here, each of the horizontal base sensor array 120a-1 and the horizontal reference sensor array 120a-2 includes rows of 23 pixels constituted by alternately arranging a line sensor including a row of five pixels and a line sensor including a row of four pixels in accordance with the horizontal arrangement of 23 focusing points P1 to P23 shown in
Here, the charge reset circuit 152 disposed as a charge reset section outputs a reset signal ΦRS for resetting charges present in a charge accumulating section included in each sensor array as described later. In the present embodiment, the charge reset circuit 152 is provided with a wiring line so as to output the reset signal ΦRS in common to all the pixel rows included in the horizontal base sensor array 120a-1, the horizontal reference sensor array 120a-2, the vertical base sensor array 120b-1 and the vertical reference sensor array 120b-2.
The TG1 generation circuit 153 generates a pulse signal TG1 for transferring the charges from photodiodes described later to the charge accumulating section, and constitutes a charge transfer section together with a transfer switch. The TG1 generation circuit 153 emits independent outputs to the pixel rows disposed in the horizontal base sensor array 120a-1, the horizontal reference sensor array 120a-2, the vertical base sensor array 120b-1 and the vertical reference sensor array 120b-2, respectively.
The integration control circuit 151 disposed as an accumulation control section controls the accumulation (integration) of the pixel rows of the sections of the horizontal base sensor array 120a-1, the horizontal reference sensor array 120a-2, the vertical base sensor array 120b-1 and the vertical reference sensor array 120b-2 to acquire outputs corresponding to the respective pixel rows.
Here, each of the A/D converters 330, 331 is an A/D converter provided with a multiplexer section, and performs a function of switching the input analog data for two channels in a time division manner under control of the A/D converter control circuit 340. The A/D converter control circuit 340 controls a sampling operation of the analog signal in the A/D converters 330, 331.
On the other hand, the AF sensor 120 includes a timing generation control circuit 300 in addition to four sensor arrays 120a-1 to 120b-2. This timing generation control circuit 300 includes a charge transfer shift pulse generation circuit 301 and a sampling pulse generation circuit 302. The charge transfer shift pulse generation circuit 301 generates and outputs charge transfer shift pulses to successively transfer and output accumulated charges obtained for each pixel to the four sensor arrays 120a-1 to 120b-2, respectively. The sampling pulse generation circuit 302 generates sampling pulses for A/D conversion start timings when A/D converters 330, 331 sample analog data input from the AF sensor 120 to convert the data into digital data. The A/D converter control circuit 340 controls sampling operations (A/D converting operations) of the A/D converters 330, 331 in response to the sampling pulses generated by the sampling pulse generation circuit 302.
Here, in the present embodiment, in order to improve focus detection precision, two line sensors 201, 202 per pixel row (island) are arranged so as to be displaced in a transverse direction. That is, with regard to the two line sensors 201, 202, the line sensor 202 is arranged so as to be displaced as much as a ½ pixel from the line sensor 201. In this manner, correlating calculation is performed in each of the line sensors 201, 202 for two lines arranged so as to be displaced from each other in the transverse direction to detect image deviation amounts and obtain an average value of the two image deviation amounts. In consequence, sensor noises (mainly shot noises) can be reduced to 1/(√2), and an amount of errors which appear in a one-pixel period can be reduced.
Moreover, as shown in
Furthermore, photodiodes 204 for monitoring are arranged in the vicinity of each line sensor 202. The photodiodes 204 for monitoring are arranged so as to perform a monitor operation of controlling an accumulation time of the photodiodes 201-1 of the respective pixel rows (islands). The photodiodes 204 for monitoring are arranged for island units so as to control the pixels of the same island so that the pixels have an equal accumulation time. The integration control circuit 151 into which outputs of the photodiodes 204 for monitoring are input judges, based on the outputs of the monitoring photodiodes 204 for each pixel row (island), whether or not the accumulation of each of the photodiodes 201-1 ends. In consequence, the integration control circuit 151 has a function of recognizing the first accumulated pixel row and the accumulation end timing of the row among all of the pixel rows.
It is to be noted that the integration control circuit 151 outputs a signal to end a charge accumulating operation (an integrating operation), even when the outputs of the photodiodes 204 for monitoring do not reach predetermined threshold values and a predetermined integration time elapses. The threshold value for ending the charge accumulating operation and the integration time can be changed.
In addition, the photodiodes 201-1 arranged for the respective pixel units obtain photo charges based on light quantities of the luminous fluxes of the subject which have entered the photodiodes 201-1. The photodiodes 201-1 constitute a light receiving section which receives the luminous fluxes transmitted through different pupil areas of the photographing lens 102 to generate the charges based on the quantities of the received lights. The charge accumulating section 201-2 temporarily accumulates the photo charges obtained by the photodiodes 201-1, respectively. Here, unnecessary charges of the charge accumulating section 201-2 are reset by setting, to an H-level, the reset signal ΦRS from the charge reset circuit 152 to the charge accumulating section 201-2.
The TG1 generation circuit 153 generates the pulse signal TG1 at the accumulation end timing of the photodiodes 201-1 of the respective islands based on the outputs of the photodiodes 204 for monitoring. In this case, the photo charges generated in the photodiodes 201-1 are transferred to the charge accumulating section 201-2 in the same island. The charge accumulating section 201-2 on an output side is connected to the charge transfer path 205 via the transfer switch 201-3. The transfer switch 201-3 outputs the charges accumulated in the charge accumulating section 201-2 once at a predetermined timing (not shown), and transfers the charges to the charge transfer path 205.
On an output side of the charge transfer path 205, a charge-voltage conversion amplifier 206 into which the photo charges are transferred as much as one pixel every time the charge transfer shift pulse is applied is disposed. On an output side of the charge-voltage conversion amplifier 206, an amplification circuit (AMP1) 207 and an output selection circuit 208 are arranged in order. After a voltage signal converted by the charge-voltage conversion amplifier 206 is amplified at a predetermined amplification factor (e.g., 1, 2, 4 or 8 folds is selected) in the amplification circuit 207, the signal is input into the output selection circuit 208. In the output selection circuit 208, after a temperature of the voltage signal input for the pixel unit is compensated based on the temperature detected by a temperature sensor (not shown), an output voltage VN is output to the A/D converter 330 or 331 of the AF controller 121 at the subsequent stage via a terminal VN.
Here, an operation control example of a charge reset operation of the charge accumulating section 201-2 of the focus detection device according to the present embodiment will be described in comparison with a conventional operation control example.
First, at the start of the accumulation operation, the accumulation operations of all of the islands are simultaneously started. The TG1 generation circuit 153 outputs the pulse signals TG1 to all of the islands at once. The pulse signals TG1 are output so as to transfer the charges from the photodiodes 201-1 to the charge accumulating section 201-2. Here, in a conventional technology shown in
On the other hand, in the present embodiment, as shown in
Especially in the present embodiment, in a case where the island α which has first ended the accumulation is detected from all of the islands under monitoring control of the integration control circuit 151, the charge reset circuit 152 cancels the reset signal ΦRS to the charge accumulating section 201-2 for all of the islands at the accumulation end timing of the island α regardless of the end of the accumulation of the other island β. That is, the charge accumulating section 201-2 has a reset state (the H-level) even from the start of the accumulation to the end of the first accumulation, and the unnecessary charges of the charge accumulating section 201-2 are not accumulated.
After the charge reset of the charge accumulating section 201-2 is canceled based on the accumulation end timing, the TG1 generation circuit 153 successively outputs the pulse signals TG1 for charge transfer of each island to transfer the charges from the photodiodes 201-1 to the charge accumulating section 201-2. After the charges are transferred, the transfer switch 201-3 is closed, the photo charges accumulated in the charge accumulating section 201-2 are transferred to the charge transfer path 205, and the above-mentioned processing is subsequently performed.
According to the present embodiment, a timing to cancel the reset of the charge accumulating section 201-2 by the charge reset circuit 152 is not set to the start of the accumulation but is set to the end of the accumulation of the island α immediately before the charge transfer. Therefore, for a time ta shown in
Here, the end of the accumulation of each of the islands is judged, the charge accumulating section 201-2 is beforehand individually provided with a signal line of the reset signal ΦRS, and the reset signal ΦRS is individually canceled at the end of the accumulation, so that the dark currents of the charge accumulating sections 201-2 of all of the islands can be minimized. However, in this case, reset signal lines as many as the islands are required, and a wiring line becomes complicated. Therefore, in the present embodiment, the charge reset circuit 152 outputs the reset signals ΦRS to the charge accumulating sections 201-2 for all of the islands via one common reset signal line, so that the number of the reset signal lines is minimized.
Next, control of the charge transfer shift pulse and the sampling pulse according to the present embodiment will be described. In
Moreover, in the present embodiment, the sampling pulse generation circuit 302 generates the sampling pulse for the horizontal direction and the sampling pulse for the vertical direction at timings having phases which deviate from each other as in the charge transfer shift pulse generation circuit 301. Specifically, as shown in
A data processing control example of such a constitution with an AF operation will be described. In the charge transfer paths 205 of the respective sensor arrays 120a-1 to 120b-2 of the AF sensor 120, every time the charge transfer shift pulse output from the charge transfer shift pulse generation circuit 301 is applied, the accumulated photo charges are transferred pixel by pixel to the charge-voltage conversion amplifier 206, and converted into a voltage signal. In this case, the horizontal charge transfer shift pulses to be input into the horizontal base sensor array 120a-1 and the horizontal reference sensor array 120a-2 among the sensor arrays 120a-1 to 120b-2 are output at the phase which deviates as much as the ¼ phase from the phase of the vertical charge transfer shift pulses to be input into the vertical base sensor array 120b-1 and the vertical reference sensor array 120b-2.
Moreover, after the voltage signal converted by the charge-voltage conversion amplifier 206 is amplified at a predetermined amplification factor in the amplification circuit 207, the signal is output toward the AF controller 121. At this time, the analog data (horizontal base analog data, horizontal reference analog data, vertical base analog data and vertical reference analog data) to be output to the AF controller 121 from channels of the horizontal base sensor array 120a-1, the horizontal reference sensor array 120a-2, the vertical base sensor array 120b-1 and the vertical reference sensor array 120b-2 is output as the signal having the phase which deviates as much as the ¼ phase in the horizontal direction and the vertical direction as shown in
As shown in
On the other hand, when the vertical analog sampling pulse from the sampling pulse generation circuit 302 changes (from the L-level to the H-level or the H-level to the L-level), the A/D converter control circuit 340 instructs the A/D converter 331 to start the A/D conversion of the vertical base analog data. Moreover, the multiplexer section of the A/D converter 331 selects the vertical base analog data corresponding to the vertical base sensor array 120b-1 as the analog data to be subjected to time division processing to start the A/D conversion of the data. Simultaneously, the A/D converter control circuit 340 instructs the A/D converter 330 to start the A/D conversion of the vertical reference analog data, and the multiplexer section of the A/D converter 330 selects the vertical reference analog data corresponding to the vertical reference sensor array 120b-2 as the analog data to be subjected to the time division processing to start the A/D conversion of the data.
In these A/D converting operations, the A/D converters 330, 331 execute the A/D conversion at a speed twice or more that of the sampling pulse of the analog signal output from the AF sensor 120.
As described above, in the focus detection device of the present embodiment, the phase of the horizontal charge transfer shift pulses to be input into at least the pair of sensor arrays 120a-1, 120a-2 among the plurality of pairs of sensor arrays 120a-1 to 120b-2 is set to deviate as much as the ¼ phase from the phase of the vertical charge transfer shift pulses to be input into the other pair of sensor arrays 120b-1, 120b-2. Therefore, since the one pair and the other pair among the plurality of pairs of sensor arrays 120a-1 to 120b-2 share the A/D converters 330, 331, respectively, the number of the A/D converters is limited to two at minimum, and the speed of charge transfer processing from the respective sensor arrays 120a-1 to 120b-2 can be increased.
Moreover, with regard to the sampling pulses for sampling of the analog signals to the A/D converters 330, 331, the phase of the horizontal sampling pulses for the analog signals corresponding to at least the pair of horizontal sensor arrays 120a-1, 120a-2 among the plurality of pairs of sensor arrays 120a-1 to 120b-2 is set to deviate as much as the ¼ phase from the phase of the vertical sampling pulses for the analog signals corresponding to the other pair of vertical sensor arrays 120b-1, 120b-2. Therefore, the speed of A/D conversion processing can be increased. As shown in
It is to be noted that in the present embodiment, as the A/D converters 330, 331, the A/D converters provided with the multiplexers are used, but a multiplexer section may separately be disposed at an input stage of the A/D converter.
While there has been shown and described what are considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention not be limited to the exact forms described and illustrated, but constructed to cover all modifications that may fall within the scope of the appended claims.
Number | Date | Country | Kind |
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2006-271976 | Oct 2006 | JP | national |
2006-272812 | Oct 2006 | JP | national |