Focus layer jump control circuits and methods of controlling focus layer jumps used by the same

Abstract

A focus layer jump control circuit may include a signal processing block that converts an analog focus error (FE) signal into a digital FE signal, in response to the analog FE signal and a FE selection signal; a layer jump control block that outputs a second control signal, in response to the digital FE signal and a reference clock signal; a focus main filter block that outputs first and second compensation signals that amplify the digital FE signal and that compensate for a phase of the digital FE signal, in response to an internal selection signal; an exponent signal generator that generates an exponent signal, in response to a focus layer jump indicating signal and a first control signal; and an output circuit that outputs a first-order difference signal using the exponent signal, the first compensation signal, and the second compensation signal, in response to the second control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects and advantages will become more apparent and more readily appreciated from the following detailed description of example embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a waveform for generating a kick/brake signal in performing a related art layer jump using a FE signal;

FIG. 2 is a block diagram of a focus layer jump control circuit according to an example embodiment;

FIG. 3 is a waveform of an internal signal of an exponent signal generator of FIG. 2;

FIG. 4 is a waveform for explaining the focus layer jump control circuit of FIG. 2;

FIG. 5 is a circuit diagram of the exponent signal generating circuit of FIG. 2 according to an example embodiment;

FIG. 6 is a circuit diagram of the exponent signal generating circuit of FIG. 2 according to another example embodiment;

FIG. 7 is a circuit diagram of the exponent signal generating circuit of FIG. 2 according to yet another example embodiment; and

FIG. 8 is a flowchart of a method of controlling a focus layer jump according to an example embodiment.

Claims

1. A focus layer jump control circuit, comprising: a signal processing block that converts an analog focus error (FE) signal into a digital FE signal, in response to the analog FE signal and a FE selection signal;a layer jump control block that outputs a second control signal, in response to the digital FE signal and a reference clock signal;a focus main filter block that outputs first and second compensation signals that amplify the digital FE signal and that compensate for a phase of the digital FE signal, in response to an internal selection signal;an exponent signal generator that generates an exponent signal, in response to a focus layer jump indicating signal and a first control signal; andan output circuit that outputs a first-order difference signal using the exponent signal, the first compensation signal, and the second compensation signal, in response to the second control signal.

2. The circuit of claim 1, wherein the signal processing block comprises: an analog-to-digital converter that converts the analog FE signal into a digital signal output;a high-pass filter that can remove a direct-current offset from the digital signal output by the analog-to-digital converter; anda first multiplexer that selects the digital signal output by the analog-to-digital converter or a signal output by the high-pass filter, in response to the FE selection signal, and that outputs the digital FE signal.

3. The circuit of claim 1, wherein the layer jump control block comprises: a duty counter that detects an accelerating speed of a focus actuator using the digital FE signal and the reference clock signal;an error peak detector that detects a peak value of the digital FE signal; anda layer jump overtime controller that measures a layer jump time using signals output by the duty counter and the error peak detector, and that outputs the second control signal.

4. The circuit of claim 3, wherein the error peak detector comprises at least three shift registers.

5. The circuit of claim 1, wherein the focus main filter block comprises: a focus main filter that outputs first and second signals that amplify the digital FE signal and that compensate for the phase of the digital FE signal;a first adder that logically adds the first and second signals;a first-order difference average filter that outputs an average value of signals output by the first adder; anda second multiplexer that selects a signal output by the first-order difference average filter or the second signal, in response to the internal selection signal, and that outputs the selected signal.

6. The circuit of claim 5, wherein the focus main filter comprises: an alternating-current filter that amplifies the digital FE signal, that compensates for the phase of the digital FE signal, and that outputs the first signal; anda direct-current filter that amplifies the digital FE signal, that compensates for the phase of the digital FE signal, and that outputs the second signal.

7. The circuit of claim 5, wherein the first-order difference average filter comprises a direct-current low-pass filter.

8. The circuit of claim 1, wherein the exponent signal generator comprises: a step signal generating circuit that is enabled when the focus layer jump indicating signal is applied, and that is disabled when a second S-shaped curve of the analog FE signal starts;an exponent signal generating circuit that outputs the exponent signal that exponentially decreases from a high state to a low state when a step signal output by the step signal generating circuit transitions from a logic low state to a logic high state, and exponentially increases from the low state to the high state when the step signal output by the step signal generating circuit transitions from the logic high state to the logic low state; anda second multiplexer that selects a signal output by the step signal generating circuit or the exponent signal generating circuit, in response to the first control signal.

9. The circuit of claim 8, wherein the exponent signal generating circuit comprises at least one of a high-pass filter, a low-pass filter, and a sinusoidal synthesizer.

10. The circuit of claim 8, wherein the first control signal controls a kick signal that maintains a specific enabled voltage level and then exponentially increases or decreases the specific enabled voltage level.

11. The circuit of claim 1, wherein the output circuit comprises: a second adder that logically adds the exponent signal and the second compensation signal; anda fourth multiplexer that selects a signal output by the second adder or the first compensation signal, in response to the second control signal, and that outputs the first-order difference signal.

12. The circuit of claim 1, wherein the first-order difference signal is used to control a focus actuator.

13. A method of controlling a focus layer jump from a present layer to another layer in response to a focus layer jump indicating signal, the method comprising: generating a step signal in response to the focus layer jump indicating signal;generating a kick signal using the step signal and exponentially decreasing or increasing a voltage level of the kick signal using a first S-shaped curve of an analog FE signal;generating a brake signal using a second S-shaped curve of the analog FE signal; anddetermining whether a focus actuator satisfies focus on conditions and instructing the focus actuator to enter a focus on mode.

14. The method of claim 13, wherein the exponentially decreasing or increasing a voltage level of the kick signal comprises: generating the kick signal using the step signal;operating the focus actuator using the kick signal;comparing a voltage level of the first S-shaped curve of the analog FE signal generated from operation of the focus actuator to a second reference voltage until a magnitude of the voltage level of the first S-shaped curve is greater than a magnitude of the second reference voltage; andgenerating an off kick signal until a magnitude of a voltage level of the second S-shaped curve is greater than a magnitude of a third reference voltage;wherein the off kick signal is exponentially decreased or increased from the voltage level of the kick signal.

15. The method of claim 13, wherein the generating a brake signal comprises: comparing a voltage level of the second S-shaped curve of the analog FE signal to a third reference voltage until a magnitude of the voltage level of the second S-shaped curve is greater than a magnitude of the third reference voltage; andgenerating the brake signal when the magnitude of the voltage level of the second S-shaped curve is greater than the magnitude of the third reference voltage.

16. The method of claim 14, wherein a magnitude of the brake signal is determined based on time required to operate the focus actuator after generating the off kick signal.

17. The method of claim 13, wherein the instructing the focus actuator to enter the focus on mode comprises: determining if a state of the focus actuator satisfies the focus on conditions; andif the state of the focus actuator satisfies the focus on conditions, entering the focus on mode.

18. The method of claim 17, wherein the focus on conditions comprise one of: a duty over time, extracted from the first S-shaped curve of the analog FE signal, passes;at least one of three points of the second S-shaped curve of the analog FE signal represents a voltage value past a peak value of the second S-shaped curve by comparing voltage levels of the three points; anda specific time passes after a command indicating the focus layer jump is applied.

19. The method of claim 18, wherein the duty over time indicates a time period where a magnitude of a voltage value of the first S-shaped curve is greater than a magnitude of a first reference voltage.

20. The method of claim 19, wherein a magnitude of the first reference voltage is smaller than a magnitude of a second reference voltage at which an off kick signal is generated.

21. The method of claim 18, wherein the voltage levels of the three points of the second S-shaped curve are stored in three shift registers.