1. Technical Field
The present disclosure relates to shutdown circuits, and particularly, to a forced shutdown circuit used in an electronic device.
2. Description of the Related Art
When an operating system of a computer stops functioning, a mechanical power button of the computer can generate signals in response to the operations of the user to signal a central processing unit (CPU) of the computer to shut down the operating system. However, if the CPU is also in an abnormal state, a reset button may be employed to forcibly reboot the operating system. The reset button is usually arranged within a host of the computer, and a through hole is defined in the host for users to press the reset button. As the reset button is within the host, the users should use a tool to press the reset button, which may be inconvenient for the users.
Therefore, there is room for improvement within the art.
The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of a forced shutdown circuit. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
Referring to
When the CPU is in a normal state, the CPU 13 controls the on and off of the first switch circuit 11 to control the power source 15 to power the load 16. When the CPU is in an abnormal state, a user presses the switch 10 for a preset time such as 10 seconds to activate the RC delay circuit 14. When the RC delay circuit 14 is activated, the CPU 13 turns on the second switch circuit 12 to turn off the first switch circuit 11, thus the power supply to the load 16 is cut off, an the operating system of the electronic device is enforcedly shut down. When the switch 10 is released, the second switching circuit 12 sets the RC delay circuit 14 to an initial state. Thus, the operating system of the electronic device can be restarted via pressing the mechanical switch 10.
Referring to
To start the operating system of the electronic device when the CPU is in the normal state, the SW 10 is pressed for a short time. When the SW 10 is pressed, the SW 10 is ground. The PWR_DET detects a low voltage level, and the CPU 13 controls the PWR_HOLD port to generate a high voltage level to turn on the field-effect transistor Q4. After the field-effect transistor Q4 is turned on, a voltage drop is generated between the source and the gate of the field-effect transistor Q3, and the field-effect transistor Q3 is correspondingly turned on. Thus, the operating system is started.
To shut down the operating system of the electronic device when the CPU is in the normal state, the SW 10 is pressed again for a short time. When the SW 10 is pressed, the SW 10 is grounded. The PWR_DET detects a low voltage level, and the CPU 13 controls the PWR_HOLD port to generate a low voltage level to turn off the field-effect transistor Q4, and the field-effect transistor Q3 is correspondingly turned off. Thus, the operating system is shut down.
To shut down the operating system of the electronic device when the CPU is in the abnormal state, the SW 10 is pressed for the preset time. The preset time is longer than the short time. When the SW 10 is pressed, the SW 10 is ground for the preset time, thus the voltage of the base of the BJT U1 becomes low, and the BJT U1 is turned off. The voltage of the gate of the field-effect transistor Q1 becomes high, and the field-effect transistor Q1 is correspondingly turned off. Thus, when the capacitor C5 of the RC delay circuit 14 discharges continuously for the preset time, it causes the voltage of the gate of the field-effect transistor Q2 to become low allowing the field effect transistor Q2 to turn on. A voltage difference between the source and the gate of the field-effect transistor Q3 decreases as the field-effect transistor Q2 is turned on, thus the field-effect transistor Q3 is correspondingly turned off. Therefore, the operating system is enforcedly shut down.
To restart the operating system of the electronic device when the operating system is enforcedly shut down, the SW 10 is released, thus the voltage of the base of the BJT U1 becomes high, and the BJT U1 is turned on. The gate of the field-effect transistor Q1 is ground via the turned-on BJT U1, and the field-effect transistor Q1 is correspondingly turned on. Thus, the capacitor C5 is charged by the VCC via the turned-on field-effect transistor Q1, causing the voltage of the gate of the field-effect transistor Q2 to become high and turn off the field-effect transistor Q2. Therefore, the operating system can be restarted via pressing the SW 10 for a short time.
It is understood that the present disclosure may be embodied in other forms without departing from the spirit thereof. Thus, the present examples and embodiments are to be considered in all respects as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein.
Number | Date | Country | Kind |
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201010612225.4 | Dec 2010 | CN | national |