This application is a divisional application of commonly assigned, co-pending U.S. patent application Ser. No. 09/479,392 invented by F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli, and Steven P. Young entitled “FPGA WITH A PLURALITY OF INPUT REFERENCE VOLTAGE LEVELS” filed Jan. 6, 2000, which is a divisional application of U.S. patent application Ser. No. 09/187,666 invented by F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli, and Steven P. Young entitled “FPGA WITH A PLURALITY OF I/O VOLTAGE LEVELS” filed Nov. 5, 1998 and issued Apr. 11, 2000 as U.S. Pat. No. 6,049,227, which is a divisional application of U.S. patent application Ser. No. 08/837,023 invented by F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli, and Steven P. Young entitled “FPGA WITH A PLURALITY OF I/O VOLTAGE LEVELS” filed Apr. 11, 1997 and issued Mar. 2, 1999, as U.S. Pat. No. 5,877,632, all of which are incorporated herein by reference.
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