Patent Application
20070268405
In accordance with the illustrative embodiment, clock source 101 is a crystal oscillator that generates a 27 MHz clock signal on lead 111, in well-known fashion. It will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention in which clock source 101 has a different frequency. Furthermore, it will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention that use something other than a crystal for clock source 101.
In accordance with the illustrative embodiment, clock multiplier 102-1 receives:
i. the 27 MHz clock signal from clock source 101 on lead 111, and
ii. a control signal, which is in a first state, on lead 113-1
and generates a 148.50000 MHz HD reference signal on lead 112-1, as described in detail and in the accompanying figures. It will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention in which the output of clock multiplier 102-1 has a different frequency.
In accordance with the illustrative embodiment, clock multiplier 102-2 receives:
i. the 27 MHz clock signal from clock source 101 on lead 111, and
ii. a control signal, which is in a second state, on lead 113-2
and generates a 148.35164 MHz SD reference signal on lead 112-2, as described in detail and in the accompanying figures. It will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention in which the output of clock multiplier 102-2 has a different frequency. Although the illustrative embodiment comprises two clock multipliers, it will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention that comprise any number of clock multipliers.
In accordance with the illustrative embodiment, HD/SD decoder 103 receives the 148.50000 MHz HD reference signal on lead 112-1 and the 148.35164 MHz SD reference signal on lead 112-2 and uses them, in well-known fashion, to decode an HD or SD encoded signal, as appropriate, for display on display 104.
In accordance with the illustrative embodiment, display 104 is a liquid crystal display that displays the image provided by HD/SD decoder 103. It will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention in which display 104 uses another technology.
Clock multiplier 102-i is a fractional phrase-locked loop whose output is N times the input frequency. When the control signal on lead 113-i is in the first state:
and when the control signal on lead 113-i is in the second state:
Clock multiplier 102-i comprises: phase detector 201, low-pass filter 202, voltage-controlled oscillator 203, and fractional divider 204, interconnected as shown.
In accordance with the illustrative embodiment, phase detector 201 outputs a signal to low-pass filter 202 that is based on the phase difference between the 27 MHz clock signal on lead 111 and the output of fractional divider 204. It will be clear to those skilled in the art how to make and use phase detector 201.
In accordance with the illustrative embodiment, low-pass filter 202 filters the output of phase detector 201 in well-known fashion. It will be clear to those skilled in the art how to make and use low-pass filter 202.
In accordance with the illustrative embodiment, voltage-controlled oscillator 203 creates a clock signal whose frequency is dependent on the output of low-pass filter 202 in well-known fashion. It will be clear to those skilled in the art how to make and use voltage-controlled oscillator 203.
In accordance with the illustrative embodiment, fractional divider 204 divides the output of voltage-controlled oscillator 203 by the value N and passes the decimated signal to phase detector 201. In accordance with the illustrative embodiment, the value N is represented in fractional divider 204 by a mixed fraction.
In general, when the control signal on lead 113-i is in the first state, the numerator is an integral multiple of 11 and the denominator is an integral power of 2, and when the control signal on lead 113-i is in the second state, the numerator is an integral multiple of 500 and the denominator is an integral multiple of 91. In particular, when the control signal on lead 113-i is in the first state, the numerator is 360,448 and the denominator is 65,536, and when the control signal on lead 113-i is in the second state, the numerator is 360,000 and the denominator is 65,520. Because the difference in the denominators in both states is small and the difference in the numerators in both states is small, the task of designing one circuit to effectively operate with both pairs of numerators and denominators is greatly simplified.
It will be clear to those skilled in the art, after reading this specification, how to make and use alternative embodiments of the present invention that have other combinations of numerators and denominators, such as those presented in Table 1. Note that in each case, the fraction in the first state equals 11/2 exactly and the fraction in the second state equals 500/91 exactly.
It is to be understood that the above-described embodiments are merely illustrative of the present invention and that many variations of the above-described embodiments can be devised by those skilled in the art without departing from the scope of the invention. For example, in this Specification, numerous specific details are provided in order to provide a thorough description and understanding of the illustrative embodiments of the present invention. Those skilled in the art will recognize, however, that the invention can be practiced without one or more of those details, or with other methods, materials, components, etc.
