Particular embodiments generally relate to phase lock loops (PLLs). Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
a discloses an example of a PLL 100. PLL 100 may be part of a transceiver that transmits/receives a radio frequency signal. PLL 100 generates a local oscillator (LO) signal that is used in upconversion or downconversion of a radio frequency signal in a transceiver. PLL 100 includes a crystal oscillator 102 (TCXO) configured to generate a reference clock signal. TCXO 102 may be an external component to a chip including PLL 100. Reference clock buffers 104 buffer the reference clock signal and output the signal to a phase frequency detector 106. Phase frequency detector 106 compares a phase difference between the clock signal and a feedback signal received in a feedback loop. Frequency detector 106 outputs a signal that represents the difference in phase between the two input signals.
A charge pump 108 and a loop filter 110 convert the phase information output by phase frequency detector 106 into a voltage or current. For example, a tuning voltage Vtune is a control signal input into a radio frequency voltage controlled oscillator (RF VCO). RF VCO generates a sinusoidal signal with a frequency controlled by tuning voltage Vtune. RF buffers 114 then output the RF signal generated by the RF VCO.
The sinusoidal signal output by RF VCO 112 is also fed back into an integer frequency divider 116. A sigma-delta (SD) modulator 118 and integer frequency divider 116 provide non-integer frequency division capability. A fractional average division factor may be achieved. The phase of the signal output by integer frequency divider 116 is compared with the phase from the input reference signal. The comparison is used to adjust the RF VCO frequency to keep phase lock.
Fractional spurs may be generated in PLL 100. Two main mechanisms may cause the generation. For example, a fractional spur may be generated due to sigma-delta modulator quantization noise combined with non-linearity of the PLL loop. A sigma-delta modulator may be used to drive the integer frequency divider division factor to obtain a fractional average division factor, which may introduce noise into PLL 100. Non-linearity of several blocks in PLL 100, such as integer frequency divider 116, phase frequency detector 106, and charge pump 108 may cause generation of fractional spurs.
Fractional spurs may also be generated by sub-sampling of a radio frequency (RF) carrier (RF attacker) by blocks of PLL 100 working at the reference frequency Fref. For example, frequency divider 116, phase frequency detector 106, charge pump 108, and reference clock buffers 104 are usually sensitive digital circuits clocked at reference frequency Fref. These blocks sub-sample the RF attacker and convert the RF attacker to baseband as a fractional spur. These spurs may be considered dominant in PLL 100. The spurs may be generated from RF attackers at the local oscillation (LO) frequency and the multiple/sub-multiples of the LO frequency.
b shows an example of the spectrum of the RF carrier generated by PLL 100, featuring phase noise and fractional spurs. At 120, an RF carrier is shown at the local oscillating frequency flo. At 122, phase noise is shown. Fractional spurs are shown at 124. The fractional /spurs are generated at an offset Δf from the RF carrier. If the offset Δf is smaller than the PLL bandwidth, the fractional spurs are not filtered by PLL 100 and can degrade the RF carrier spectrum and also system performance. A spectral emission mask can be violated in the transmitter because the baseband spectrum is up-converted around the fractional spurs. Also, reception in the presence of strong interferers (blockers) can be compromised in the receiver because fractional spurs down-convert the interferer to baseband.
c shows an example of the generation of fractional spurs. An RF attacker may be any RF carrier in the system that may result in spurious tones. RF attackers may be the RF signals distributed by RF VCO 112 and RF buffers 114 across a chip that includes the transmitter/receiver. The RF attackers may couple to blocks of PLL 100 that are implemented as digital circuits that are clocked at reference frequency Fref. These blocks are typically reference clock buffers 104, phase frequency detectors 106, charge pump 108, and frequency divider 116. Coupling may occur in different ways, such as substrate coupling, ground/supply coupling, magnetic coupling, etc.
If an RF attacker is superimposed on a clock signal of a frequency Fref, and this clock signal drives an edge-sensitive digital circuit, the RF attacker undergoes sub-sampling. The resulting signal is affected by jitter and may feature two sidebands at Δf from the clock signal fundamental frequency Fref.
In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
In one embodiment, the characteristic of the jitter adds a small amount of energy inside a bandwidth of the PLL to limit degradation of the RF signal spectrum.
In one embodiment, energy that is out of the PLL bandwidth is filtered out by the PLL.
In one embodiment, the characteristic of the jitter includes a magnitude comparable to a period of the RF attacker causing the fractional spur.
In one embodiment, the jitter eliminates the fractional spur.
In one embodiment, a system where the PLL is configured to receive the reference clock with the added jitter and output the LO signal based on the reference clock with the added jitter.
In one embodiment, the method includes receiving a reference clock. A control signal is received to control a characteristic of jitter added to the reference clock. The method adds the jitter to the reference clock based on the control signal and outputs the reference clock with the added jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
In one embodiment, adding the jitter includes selecting a delayed reference clock signal from a first delay line that includes a plurality of delay elements, wherein each delay element delays the reference clock by a delay amount.
In one embodiment, receiving the control signal includes receiving a selection code indicating which delayed reference clock signal from one of the delay elements should be selected.
In one embodiment, a sequence of selection codes is received to select different delayed reference signals to control the characteristic of the jitter.
The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention.
a shows an example of a PLL.
b shows an example of the RF carrier spectrum and also fractional spurs.
c shows an example of the generation of fractional spurs.
d shows the effects of an RF attacker.
a shows the effect of PLL filtering according to one embodiment.
b shows a 3 MHz offset spur at the PLL output due to the reference modulation according to one embodiment.
Described herein are techniques for a reference clock generation system. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
Jitter controller 204 drives jitter generator 202 and controls various characteristics of the jitter, such as amplitude, frequency, spectral characteristics, etc. In one embodiment, being controlled means that jitter features a small energy inside the PLL bandwidth so that the RF carrier spectrum degradation is small. By this means, out-of-band energy may be effectively filtered by the PLL input to output low pass transfer function. Thus, most jitter energy may be outside of the PLL bandwidth. Also, jitter magnitude (peak or root mean square (RMS), depending on the characteristics of jitter τ(t)) should be significant compared to the period of an RF attacker, 1/FRF.
Depending on the spectrum of jitter τ(t), a fractional spur may be attenuated or completely eliminated, and moved to a more convenient frequency offset (e.g., outside the PLL bandwidth) where the fractional spur can be more effectively filtered. Also, the fractional spur may be converted to a noise floor (e.g., white noise), which reduces the spectral emission per unit bandwidth. The noise floor may include the same energy as the fractional spur, but at a lower spectral density. Thus, instead of a large tone, a noise floor exists that may be filtered and in some cases be less detrimental for system performance.
The clock jitter is introduced to mitigate self-interference from RF signals (RF attackers) in RF transceiver 206. The clock signal is not the attacker in this case. Rather, the introduction of clock jitter reduces the effect of RF attackers on the transceiver's performance.
In one example, sinusoidal jitter is introduced into the reference clock. For example, sinusoidal jitter may have a peak amplitude Δt and modulation frequency Fm. The jitter may be defined by:
cos└2πFreft+2πFrefΔt·cos(2πFmt)┘
Fref=26 MHz, Fm=3 MHz
The RF attacker frequency is chosen to cause a fractional spur at Δf=400 kHz frequency offset:
FRF=K Fref+Δf with Δf=400 kHz
Thus, fractional spurs may appear as follows due to RF attacker sub-sampling in components of PLL 201:
The amplitude of the fractional spur at 400 kHz offset relative to the amplitude of the fractional spur at 400 kHz offset as described in the background (the case with no jitter added to the reference clock signal) is reduced as shown in
In one embodiment, by increasing the jitter peak magnitude with respect to the RF attacker period, the 400 KHz spur can be reduced significantly and even eliminated for some Δt/TRF ratios. Also, the energy of the spurs is transferred to tones at higher offsets where filtering of PLL 201 can be more effective. For example,
b shows a 3 MHz modulation spur at the PLL output due to the reference modulation according to one embodiment. A 3 MHz modulation spur also appears at a <55 dBc level. The magnitude of the modulation spur at 3 MHz may be reduced by increasing modulation frequency Fm. Also, by proper choice of the modulation frequency Fm of the jitter, newly generated tones can be arranged in a more convenient way (e.g., avoiding the 600 KHz tone, moving the tones to higher offsets, etc.).
A clean reference clock is generated by a reference clock generator 508. This is input into delay line 502. Delay line 502 includes a number of delay elements 510a-510N. Each delay element 510 may be of the same unit of delay, such as a delay τ. Delay line 502 creates a set of delayed replicas of the clean reference clock.
Edge selector 504 includes N inputs and one output that go to PLL 201. The N inputs are from each delay element 510. Thus, N delayed replicas of the clean reference clock are input into edge selector 504. Edge selector 504 then selects one of the N delayed replicas according to a value of an edge selection code received from digital sequence generator 506. In one embodiment, the edge selection code is updated once every reference clock period l/Fref. Timing may be provided to guarantee a glitch-free output of the reference clock with jitter.
Digital sequence generator 506 generates a sequence qk of edge selection codes to introduce the desired amount of jitter onto the clean reference clock signal with the desired spectral characteristics. The digital sequence generator is clocked at the clock frequency Fref to update the edge selection code once every reference period. The jitter introduced can be expressed as qk*τ, with qk=1 . . . N. Digital sequence generator 506 generates the edge selection code to select a different delay element. The selection of different delayed replicas of the clean reference clock includes jitter on the reference clock output by edge selector 504.
Digital sequence generator 506 may be implemented in different ways. For example,
Digital sigma-delta modulator 602 may be an Lth order digital sigma-delta modulator. For example, a multi-stage noise shaping (MASH) sigma-delta modulator may be used. A ΣΔ input (not shown) may be received at digital sigma-delta modulator 602. Digital sigma-delta modulator 602 then codes the ΣΔ input into the edge selection code. The number of delay elements N may be equal to the number of levels at the ΣΔ output of the edge selection code. That is, the output would have a bit specific to a delay element. Digital sigma-delta modulator 602 may introduce quantization noise, which may corrupt the reference clock spectrum. However, the noise-shaping capability of digital sigma-delta modulator 602 pushes the quantization noise energy to high frequencies. For example, the quantization noise energy from digital sigma-delta modulator 602 is high pass shaped and pushed around the frequency Fref/2. The input to output low pass transfer function of PLL 201 can attenuate the noise, since the PLL bandwidth is usually much smaller than the reference clock frequency Fref. In this case, filtering of PLL 201 can suppress this noise at the PLL output. Also, the ΣΔ input can be selected to optimize spectral performance and add dithering to avoid idle tones.
Digital sigma-delta modulator 602 may be configured to convert a fractional spur into white noise.
The energy of the spur is converted into a noise floor that has the same energy, but has a lower spectral density.
The spectral power reduction may be optimized when the unit delay of the reference clock with jitter is centered around 0.5*Trf (half the period of the RF attacker). In some cases, more RF attackers are present at super- or sub-harmonics of the local oscillator frequency. For a given RF channel, only one attacker may be generating the spur closest to the carrier. Particular embodiments may add programmability to delay line 502 to optimize the delay for the most dangerous RF attacker in a channel-dependent way.
Second block 812 includes a slave delay line 814, edge selector 504, and digital sequence generator 506. Slave delay line 814 receives a reference clock signal from reference clock generator 202. First block 802 and second block 812 may be used in a master/slave configuration to tune/calibrate the unit delay to be as close as possible to 0.5 TRF against process-voltage-temperature (PVT) variations and Tref variations. In this case, the appropriate delay τ can be achieved to introduce the desired jitter. The DLL is used to tune/calibrate the unit delay to be as close to 0.5TRF as possible.
As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.
The present disclosure claims priority to U.S. Provisional App. No. 61/368,459 entitled “A PLL Fractional Spurs Reduction” filed Jul. 2010, which is incorporated herein by reference in its entirety for all purposes.
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