Patent Application
20130147822
1. Field of the Art
The disclosure generally relates to a video display system. More specifically, the disclosure relates to a self-refresh feature in video receivers and display timing controllers.
2. Description of the Related Art
In many video display systems, a page flipping method is utilized to prevent screen tearing. A frame buffer uses a first section of memory to display a current frame. While the data in that memory is being displayed, a second section of memory is filled with data for the next frame. Once the second section of memory is filled, the frame buffer is instructed to look at the second section of memory and display that data. The process continues with the next video frame being loaded into memory in the first section of memory. This ensures that a frame of video is always fully loaded before displaying the frame. For this to be accomplished, memory capable of storing two entire frames of video must be available to a display system.
The disclosed embodiments have other advantages and features which will be more readily apparent from the detailed description, the appended claims, and the accompanying figures (or drawings). A brief introduction of the figures is below.
The Figures (Figs.) and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is disclosed.
Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the disclosed system (or method) for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.
The display device 120 may be a liquid crystal display (LCD), light emitting diode (LED) or plasma based display, or another screen suitable for video display. A sink device 108 is configured to receive a plurality of video frames over the video link 106 and implement a self-refresh feature. In one embodiment, the sink device 108 is part of the display device 120. The sink device 108 may also be external from the display device 120. The video receiver 110 is configured to receive the plurality of video frames transmitted over the video link 106 and perform any processing to enable processing within the sink device 108. The self-refresh controller 114 is configured to display an image or series of images continuously on the display device 120. The frame buffer 120 is used to support the self-refresh feature. The sink device 108 stores a static image locally in the frame buffer 112 and displays the saved frame from the frame buffer while the video source and/or video link are disable and/or turned off to save power. The data pipes 116 may be a video or display processing unit such as timing controller data pipes. The transmitter 118 is, in one example embodiment, a low voltage differential signaling (LVDS) transmitter or similar panel interface transmitter.
The Self-refresh features include the following functions:
Self-refresh (SR) entry: Source device 100 instructs the sink device 108 to enter a SR active state. Sink device 108 captures a static frame from the video link to frame buffer and sink device 108 switches to locally regenerated timings and display video frame from frame buffer.
Self-refresh (SR) exit: Source device 100 instructs the sinke device 108 to transition SR state from active to inactive. Sink device 108 device continues to drive display on locally generated timings until timing re-synchronization is completed. When re-sync is completed, sink device 108 drives display on source timings and displays video frames as they are received from the source device 100.
Single Frame Update: A source will transmit a static frame to update the frame buffer without exiting SR active state. The source will send new static video frame on the video link. A sink captures the new static video frame to a frame buffer. The sink continues driving a display on locally generated timings and displays the newly received single frame utilizing the self-refresh controller.
Burst Single Frame Update: The single frame update mechanisms can be extended to multiple consecutive frames. A source may send single frame updates for multiple consecutive frames to achieve burst single frame updates without exiting SR active state Each of the single frames received during the burst single frame update is then displayed and self-refreshed until a subsequent frame of the burst single frame update is received.
For the above single frame updates and burst single frame updates, screen tearing can occur if special care is not taken for frame buffer management. Screen tearing is a visual artifact in a video where partial information from two or more different frames is shown in a display device in a single screen display.
One example of a system configured for self-refresh includes some embodiments of embedded DisplayPort implementations. The disclosed system and method also apply to any other digital video display receivers which have similar self-refresh function built-in. The system limits the size of memory needed to prevent screen tearing. Locally generated timing adjusts to balance throughput between video data flow on a video link and display data flow with self-refresh to prevent memory over-run or under-run.
Static frame capture 206 is configured to receive and capture a static frame recovered by the video recovery block 204 and write the frame to frame buffer 210. The frame buffer management module 208 governs writes to and accesses from the frame buffer 210. Frame buffer management will manage write and read addresses within the frame buffer 210 to prevent screen tearing for single frame update or burst frame update while in self-refresh active state. Static frame display 212 is used to retrieve a static frame from the frame buffer 210. Line lock DPLL 214 generates a self-refresh line clock. The self-refresh line clock is adjusted so that the frame read throughput will match the frame write throughput to prevent frame buffer over-run or under-run during single frame update or burst frame update while in self-refresh active state.
Local display timing generator 216 generates displaying timing information for self-refresh and the timing information is locked to the self-refresh line clock generated by the line clock DPLL 214. Self-Refresh MUX 218 is used to select video data and video timing source. It may select video data and timing from the video recovery block 204 to display frames as they are received from the video source 100 or from the static frame display block 212 to display frames that are being self-refreshed.
If no self-refresh exit command is received 313, the system continues to display the static image while also detecting any single frame update command that is received 323. If the single frame update command is received, the line lock DPLL is set to sync mode and the new static frame is captured 325. The new static frame is appended to the previous static frame in memory. If another single frame update is received as part of a burst frame command 329, the system returns to block 325 to capture the additional static frame module for display. When no additional single frame updates are received, the system returns line lock DPLL to coast mode and again waits for a self-refresh exit 319 or single frame update command.
In one embodiment, the frame buffer 210 is used as a first in first out (FIFO) buffer. The size of the frame buffer is a larger than one frame. For example, the memory size can be chosen as follows:
For static frame display, in one embodiment a frame image is retrieved from the memory location for the previous static frame. For static frame capture, when a second (2nd) static frame is written to the frame buffer, the new static frame is appended to the end of the previous static frame. For a frame buffer write, when the memory end address is reached, the memory address is wrapped to the memory start address and some part of the previous static frame begins to be overwritten. The overwritten portion has already been displayed and will not be used in the future. The static frame display block will display from the new static frame for the next display frame.
The static frame display block is configured to read a static frame from beginning to end. When the static frame display block reaches the end of a static frame a check is performed to see if a new static frame is written in the frame buffer and how many lines are written in the frame buffer. If there are enough lines written to the frame buffer of the new static frame, the static frame display block can begin to read from the new static frame. If not, the static frame display block again reads from the previous static frame for display. The lines for switching frame read start address are defined in one embodiment as the threshold to switch the frame read start address.
For example, there is n-line in a video frame and the extra buffer needs to save eight lines of video data. Then the memory size needed is n-line+8-line. The threshold for switching memory start address is defined as 4-line. In this case, when the static frame capture starts to write new static frame to frame buffer, the static frame display is displaying video line x from previous static frame. Line x is within 1 to n. If the frame read speed can be kept the same as, or close to, the frame write speed, the frame read address will not cross frame write address and thus the screen tearing will not occur.
There are three relatively extreme cases for frame buffer writing.
Even with extra buffer in the memory, special care may be necessary to avoid overflow or underflow. To avoid overflow and under flow a line lock DPLL to match the static frame display throughput with the static frame capture throughput may be used.
The line lock DPLL will generate self-refresh line clock for local display timing generator. There are two modes for the line lock DPLL: coast mode and sync mode. In the coast mode, the DPLL does not check video line clock. It generates the line clock by pre-defined parameter only. In the sync mode, the line clock is adjusted to keep the local generated line clock sync to the line clock from video source. The local display timing generator is locked to self-refresh line clock which is generated by line lock DPLL. The static frame display block will read frame images from the frame buffer according to locally generated display timing which is generated by the local display timing generator. The static frame display block can keep the same throughput as the throughput of the static frame capture block and screen tearing is prevented.
The first signal corresponds with a START 1201 signal. When the DPLL works in sync mode, the START 1201 signal is asserted. When DPLL enter coast mode, the START 1201 signal is de-asserted.
The next signal line is a line clock 1202. The line clock 1202 is a horizontal synchronization signal for video display.
The next signal line is self-refresh line clock 1203. It references horizontal total time (HT or HTOTAL), which is counted in number of pixels.
The next signal lines is phase update 1204. When this signal is asserted, the frequency error indication can be obtained from an up-down counter 1205.
When DPLL exits coast mode, it starts to detect the frequency error between video source line clock 1202 and self-refresh line clock 1203. A counter counts the HTOTAL for both video source line clock and self-refresh line clock. When START=0, the up-down counter is reset to 0. After one HTOTAL is counted for the video source line clock, the source HTOTAL is added to the up-down counter 1205. After one HTOTAL for self-refresh line clock is counted, the self-refresh HTOTAL is subtracted from the up-down counter.
Line counters are included for source video line clock and self-refresh video line clock. When source line counter=self-refresh line counter, the Phase Update 1204 signal is asserted and the content in the up-down counter 1205 can be used as indication for the frequency error. When source line counter−self-refresh line counter>=2, that means source line clock is too fast and the error information for up-down counter is clamped to the minimum negative value. When source line counter−self-refresh line counter<=−2, that means source line clock is too slow and the error information for up-down counter is clamped to the maximum positive value.
The Loop Filter block will generate M_delta Control signal for DTO according to input error signals.
M_delta1=Gain1*error
M_delta2=Gain2*(accumulation of previous errors+current error)
M_delta=M_delta1+M_delta2
The error signal can be positive or negative and the M_delta can be positive or negative too. The DTO block is used to generate self-refresh line clock. First the adjusted pixel clock is generated according to following formula:
Adjusted pixel clock=(M+M_delta)/M*pixel clock
M is a parameter for pixel clock adjustment. It is chosen according to a design requirement. With the higher parameter M, there may be a higher precision for the video clock tuning For example, if M=4096, the adjusted video clock can be increased or decreased by 1/4096 of the original video clock. A self-refresh line clock is obtained according to following formula:
Line clock=adjusted pixel clock/P—HTOTAL
The P_HTOTAL is a parameter for horizontal total time in pixels. Normally, P_HTOTAL is set according to the self-refresh video timing format. In one embodiment, the above formulas are combined to get one formula for generating line clock as follows:
A discrete time oscillator (DTO) is used in one embodiment to generate the line clock. P is the numerator of the DTO, which is equal to (M+M_delta). Q is the denominator, which is equal to (M*P_HTOTAL).
The disclosed system and method provide the solution for the memory management and self-refresh control in the self-refresh display function. Along with the line lock DPLL to adjust self-refresh line clock to match the source video line clock, screen tearing during single frame update, burst frame update and other similar frame update features can be prevented. It only need increase the frame buffer size by 2 or more lines thus can reduce the system cost. It also can reduce the power consumption. The disclosed system and method offer a flexible and general solution to all kinds of self-refresh display systems. And it also has the room to extend for any future self-refresh display system and features.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Certain embodiments are described herein as including logic or a number of components, modules, or mechanisms, for example, as described in
In various embodiments, a hardware module may be implemented mechanically or electronically. For example, a hardware module may comprise dedicated circuitry or logic that is permanently configured (e.g., as a special-purpose processor, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)) to perform certain operations. A hardware module may also comprise programmable logic or circuitry (e.g., within a general-purpose processor or other programmable processor) that is temporarily configured by software to perform certain operations. It will be appreciated that the decision to implement a hardware module mechanically, in dedicated and permanently configured circuitry, or in temporarily configured circuitry (e.g., configured by software) may be driven by cost and time considerations.
The various operations of example methods described herein may be performed, at least partially, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations using instructions (e.g., corresponding to the processes described in
Unless specifically stated otherwise, discussions herein using words such as “processing,” “computing,” “calculating,” “determining,” “presenting,” “displaying,” or the like may refer to actions or processes of a machine (e.g., a computer) that manipulates or transforms data represented as physical (e.g., electronic, magnetic, or optical) quantities within one or more memories (e.g., volatile memory, non-volatile memory, or a combination thereof), registers, or other machine components that receive, store, transmit, or display information.
As used herein any reference to “one embodiment” or “an embodiment” means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase “in one embodiment” in various places in the specification is not necessarily all referring to the same embodiment.
Some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. For example, some embodiments may be described using the term “coupled” to indicate that two or more elements are in direct physical or electrical contact. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments are not limited in this context.
As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).
In addition, use of the “a” or “an” are employed to describe elements and components of the embodiments herein. This is done merely for convenience and to give a general sense of the invention. This description should be read to include one or at least one and the singular also includes the plural unless it is obvious that it is meant otherwise. Upon reading this disclosure, those of skill in the art will appreciate still additional alternative structural and functional designs for a system and method for frame buffer management and self-refresh control in a self-refresh display System through the disclosed principles herein. Thus, while particular embodiments and applications have been illustrated and described, it is to be understood that the disclosed embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope of the disclosure.
This application claims the benefit of, and priority to, U.S. Provisional Application No. 61/568,072, filed Dec. 7, 2011, which is incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61568072 | Dec 2011 | US |
