Claims
- 1. A buffer, comprising:
- a plurality of sequentially ordered input modes, each node operable to receive one bit of a data word;
- a plurality of sequentially ordered multiplexing circuits, each multiplexing circuit having a first input coupled to a respective input node;
- first control circuitry for selectively coupling a second input of each multiplexer circuit to an output of a selected one of a plurality of subsequent multiplexing circuits, each of said plurality of subsequent multiplexing circuits separated from said multiplexer circuit by a predetermined number of multiplexing circuits equal to 2.sup.N, where N is a positive integer, said multiplexer circuits not having such a subsequent multiplexer circuit having said second input not connected;
- second control circuitry coupled to each said multiplexing circuit for selecting between said first and second inputs; and
- a plurality of outputs coupled to said multiplexing circuits for outputting the groups of bits, each group of bits having a predetermined number of bits.
- 2. The frame buffer of claim 1, wherein said first control circuitry comprises:
- a plurality of first latches, each said first latch coupled between a respective one of said multiplexing circuits and a respective one of said outputs; and
- at least one transmission gate associated with a second input of each multiplexing circuit for coupling a second input of said associated multiplexing circuit to said output of said subsequent multiplexing circuit.
- 3. The frame buffer of claim 2, and further comprising a plurality of second latches, each of said second latches having an input connected to a respective said output of a selected one of said first latches.
- 4. The frame buffer of claim 2, wherein said multiplexing circuits comprise a sequentially ordered array k of multiplexing circuits, said first latches comprising a sequentially ordered array k of latches, each said multiplexing circuit associated with a respective sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2.sup.m-1)th one of said multiplexing circuits operable to couple an input of said (n-2.sup.m-1) multiplexing circuit to an output of an nth one of said first latches, j, k, m, and n are positive integers, j and k are constants, m is a variable between l and j, and n is a variable that is greater than 2.sup.m-1.
- 5. The buffer of claim 4, wherein j equals 4.
- 6. The buffer of claim 4, wherein k equals 32.
- 7. The buffer of claim 4, wherein k/j is an integer.
- 8. The buffer of claim 7, wherein k/j is a power of two.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 07/723,342, filed Jun. 28, 1991.
The following patent application, assigned to Texas Instruments Incorporated, the assignee of the present application, and is cross-reference and incorporated into present application by reference.
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Continuations (1)
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Number |
Date |
Country |
Parent |
723342 |
Jun 1991 |
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